CN116137259A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN116137259A
CN116137259A CN202211412144.9A CN202211412144A CN116137259A CN 116137259 A CN116137259 A CN 116137259A CN 202211412144 A CN202211412144 A CN 202211412144A CN 116137259 A CN116137259 A CN 116137259A
Authority
CN
China
Prior art keywords
solder
copper
copper block
semiconductor device
electrode terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211412144.9A
Other languages
English (en)
Inventor
作元祥太朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN116137259A publication Critical patent/CN116137259A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及半导体装置。目的在于提供一种能够抑制焊料从铜块剥离的技术。将铜块经由第一焊料接合至铜图案之上，将电极端子经由第二焊料接合至铜块之上。封装树脂将铜图案、第一焊料、铜块、第二焊料、电极端子以及半导体元件覆盖。铜块中的由第一焊料接合的部分的面积大于铜块中的由第二焊料接合的部分的面积。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
作为功率半导体装置等半导体装置，提出有将半导体元件和厚度比较大的导电块即铜块通过封装树脂封装起来的半导体装置(例如，专利文件1)。
专利文件1：日本特开2013-131592号公报
发明内容
半导体装置要求在高温环境下也进行工作。然而，在制造时如果使高温工作用的封装树脂硬化，则从硬化开始时的温度到室温的温差大，因此封装树脂的热膨胀以及收缩应力比较大。其结果，封装树脂的应力集中在用来接合铜块的焊料，焊料有可能会从铜块剥离。
于是，本发明是鉴于上述问题而提出的，其目的是提供能够抑制焊料从铜块剥离的技术。
本发明涉及的半导体装置具有：铜图案；铜块，其经由第一焊料接合至所述铜图案之上；电极端子，其经由第二焊料接合至所述铜块之上；半导体元件，其与所述铜图案电连接；以及封装树脂，其将所述铜图案、所述第一焊料、所述铜块、所述第二焊料、所述电极端子以及所述半导体元件覆盖，所述铜块中的由所述第一焊料接合的部分的面积大于所述铜块中的由所述第二焊料接合的部分的面积。
发明的效果
根据本发明，铜块经由第一焊料接合至铜图案之上，电极端子经由第二焊料接合至铜块之上，铜块中的由第一焊料接合的部分的面积大于铜块中的由第二焊料接合的部分的面积。根据这样的结构，能够抑制焊料从铜块剥离。
附图说明
图1是示出实施方式1涉及的半导体装置的结构的剖视图。
图2是示出实施方式2涉及的半导体装置的结构的剖视图。
图3是示出实施方式3涉及的半导体装置的结构的剖视图。
图4是示出实施方式4涉及的半导体装置的结构的剖视图。
具体实施方式
以下一边参考附图一边说明实施方式。通过以下的各实施方式来说明的特征是示例，并非所有的特征都是必须的。另外，在以下示出的说明中，在多个实施方式中对同样的结构要素标注相同或类似的标号，主要说明不同的结构要素。另外，在以下记载的说明中，“上”、“下”、“左”、“右”、“表”或“背”等特定的位置以及方向与实际实施时的位置以及方向并非必须一致。
<实施方式1>
图1是示出本实施方式1涉及的半导体装置的结构的剖视图。图1的半导体装置具有绝缘性基底基板1、铜图案2、第一焊料3、铜块4、第二焊料5、电极端子6、第三焊料7、半导体元件8、导线9、电极端子10、粘合部件11、外壳12和封装树脂13。
绝缘性基底基板1包含铜基底板1a和树脂绝缘层1b。树脂绝缘层1b设置在铜基底板1a之上，与铜基底板1a一体化。
铜图案2设置在树脂绝缘层1b之上。此外，铜图案2也可以包含于绝缘性基底基板1。
铜块4经由第一焊料3而接合至铜图案2之上。在本实施方式1中，铜块4的厚度大于铜图案2的厚度。
电极端子6经由第二焊料5而接合至铜块4之上。此外，铜块4中的由第一焊料3接合的部分的面积大于铜块4中的由第二焊料5接合的部分的面积。
半导体元件8包含半导体开关元件以及二极管中的至少一个。半导体开关元件例如是IGBT(Insulated Gate Bipolar Transistor)、RC-IGBT(Reverse Conducting-IGBT)、MOSEFT(Metal Oxide Semiconductor Field Effect Transistor)，二极管是例如PND(PNjunction Diode)、SBD(Schottky Barrier Diode)。下面，以半导体元件8是半导体开关元件的情况为例来说明。
半导体元件8的材料可以是普通的硅(Si)，也可以是碳化硅(SiC)、氮化镓(GaN)、金刚石等宽带隙半导体。在半导体元件8的材料是宽带隙半导体的情况下，能够实现高温下以及高压下的稳定工作、以及通断速度的高速化。
半导体元件8与铜图案2电连接。在本实施方式1中，半导体元件8经由第三焊料7与铜图案2接合而电连接到铜图案2。由此，半导体元件8经由铜图案2而电连接到铜块4以及电极端子6，电极端子6例如作为半导体元件8的集电极(collecor)电极(electrode)起作用。
半导体元件8经由导线9而与电极端子10电连接，电极端子10例如作为半导体元件8的发射极电极起作用。导线9的材料例如是铝。通过导线9的连接和第一焊料3、第二焊料5以及第三焊料7的接合，在由外壳12包围的空间内形成电路。
外壳12通过粘合部件11与绝缘性基底基板1的端部粘合。外壳12的材料例如是绝缘性树脂。在图1的例子中，电极端子6的中央部以及电极端子10的中央部埋设于外壳12。
封装树脂13填充于由外壳12包围的空间，覆盖铜图案2、第一焊料3、铜块4、第二焊料5、电极端子6以及半导体元件8等。封装树脂13具有超过半导体元件8的工作温度的玻璃化转变温度(Tg)。
<实施方式1的总结>
就本实施方式1涉及的半导体装置而言，铜块4中的由第一焊料3接合的部分的面积大于铜块4中的由第二焊料5接合的部分的面积。根据这样的结构，第一焊料3和铜块4的接合面积比较大，因此能够抑制第一焊料3从铜块4剥离。
另一方面，第二焊料5与第一焊料3相比位于更靠近封装树脂13的上表面处。越是靠近封装树脂13的上表面，越能够将封装树脂13的应力释放到封装树脂13的上方的空间，因此第二焊料5从封装树脂13承受到的应力小于第一焊料3从封装树脂13承受到的应力。为此，即使第二焊料5和铜块4的接合面积比较小，也能够抑制第二焊料5从铜块4剥离。
此外，在本实施方式1中，铜块4的厚度大于铜图案2的厚度。根据这种结构，能够使第二焊料5进一步靠近封装树脂13的上表面，因此能够进一步抑制第二焊料5从铜块4剥离。此外，铜块4和封装树脂13的接触面积比较大，因此能够抑制封装树脂13从铜块4剥离。
<实施方式2>
图2是示出本实施方式2涉及的半导体装置的结构的剖视图。在本实施方式2中，在铜块4的由第二焊料5接合的面设置有凹凸4a。即，铜块4的由第二焊料5接合的面被粗糙化。
凹凸4a的范围只要是第二焊料5润湿扩展的范围即可，例如是直径为200～300μm的圆形状的范围、或一边为200～300μm的四方形状的范围等。凹凸4a的高低差例如是200μm左右，在形成凹凸4a时例如使用壁板沟槽(router)加工。除了以上的点之外，本实施方式2的结构与实施方式1的结构相同。
根据以上的本实施方式2涉及的半导体装置，能够得到与实施方式1相同的效果。此外，在本实施方式2中，通过铜块4的凹凸4a，在第二焊料5和铜块4之间产生锚定效应，因此能够抑制第二焊料5从铜块4剥离。
此外，虽然没有图示，但是也可以通过在电极端子6的由第二焊料5接合的表面也设置凹凸，由此抑制第二焊料5从电极端子6剥离。
<实施方式3>
图3是示出本实施方式3涉及的半导体装置的结构的剖视图。在图3中，实施方式1的封装树脂13的上表面的位置由双点划线来表示。在本实施方式3中，电极端子6的由第二焊料5接合的部分上方的封装树脂13的厚度D大于或等于2.0mm而小于或等于2.5mm。即，从电极端子6中的不与第二焊料5相接的上部到封装树脂13的上表面为止的厚度D大于或等于2.0mm而小于或等于2.5mm，比较薄。除了以上的点之外，本实施方式3的结构与实施方式1的结构相同。
根据以上的本实施方式3涉及的半导体装置，能够得到与实施方式1相同的效果。此外，在本实施方式3中，电极端子6的由第二焊料5接合的部分上方的封装树脂13的厚度D比较薄，因此能够降低第二焊料5从封装树脂13承受到的应力，能够抑制第二焊料5从铜块4剥离。此外，能够促进封装树脂13的硬化。此外，本实施方式3的结构也可以应用于实施方式2。
<实施方式4>
图4是示出本实施方式4涉及的半导体装置的结构的剖视图。在本实施方式4中，将涂膜14设置在铜块4和封装树脂13之间。此外，在图4的例子中，在树脂绝缘层1b、铜图案2、半导体元件8以及导线9各自与封装树脂13之间也设置有涂膜14。涂膜14的材料例如是聚酰亚胺，涂膜14的厚度例如小于或等于100nm。涂膜14的热膨胀系数优选与铜的热膨胀系数相等。除了以上的点之外，本实施方式4的结构与实施方式1的结构相同。
根据以上的本实施方式4涉及的半导体装置，能够得到与实施方式1相同的效果。此外，在本实施方式4中，通过涂膜14，能够提高铜块4和封装树脂13之间的密接性，因此能够抑制封装树脂13从铜块4剥离。此外，根据如图4所示的结构，能够抑制封装树脂13从树脂绝缘层1b、铜图案2、半导体元件8以及导线9剥离。此外，本实施方式4的结构也可以应用于实施方式2、3。
此外，能够将各实施方式以及各变形例自由组合，将各实施方式以及各变形例适当地变形、省略。
标号的说明
2铜图案，3第一焊料，4铜块，4a凹凸，5第二焊料，6电极端子，8半导体元件，13封装树脂，14涂膜。

Claims (5)

1.一种半导体装置，其具有：
铜图案；
铜块，其经由第一焊料接合至所述铜图案之上；
电极端子，其经由第二焊料接合至所述铜块之上；
半导体元件，其与所述铜图案电连接；以及
封装树脂，其将所述铜图案、所述第一焊料、所述铜块、所述第二焊料、所述电极端子以及所述半导体元件覆盖，
所述铜块中的由所述第一焊料接合的部分的面积大于所述铜块中的由所述第二焊料接合的部分的面积。
2.根据权利要求1所述的半导体装置，其中，
所述铜块的厚度大于所述铜图案的厚度。
3.根据权利要求1或2所述的半导体装置，其中，
在所述铜块的由所述第二焊料接合的面设置有凹凸。
4.根据权利要求1至3中任一项所述的半导体装置，其中，
所述电极端子的由所述第二焊料接合的部分上方的所述封装树脂的厚度大于或等于2.0mm而小于或等于2.5mm。
5.根据权利要求1至4中任一项所述的半导体装置，其中，
还具有涂膜，该涂膜设置在所述铜块和所述封装树脂之间。
CN202211412144.9A 2021-11-16 2022-11-11 半导体装置 Pending CN116137259A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-186172 2021-11-16
JP2021186172A JP2023073616A (ja) 2021-11-16 2021-11-16 半導体装置

Publications (1)

Publication Number Publication Date
CN116137259A true CN116137259A (zh) 2023-05-19

Family

ID=86144413

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211412144.9A Pending CN116137259A (zh) 2021-11-16 2022-11-11 半导体装置

Country Status (4)

Country Link
US (1) US20230154814A1 (zh)
JP (1) JP2023073616A (zh)
CN (1) CN116137259A (zh)
DE (1) DE102022124463A1 (zh)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013131592A (ja) 2011-12-21 2013-07-04 Mitsubishi Electric Corp リード端子およびこれを用いた半導体装置

Also Published As

Publication number Publication date
JP2023073616A (ja) 2023-05-26
US20230154814A1 (en) 2023-05-18
DE102022124463A1 (de) 2023-05-17

Similar Documents

Publication Publication Date Title
US8466548B2 (en) Semiconductor device including excess solder
US20130049204A1 (en) Semiconductor device including diffusion soldered layer on sintered silver layer
US20120175755A1 (en) Semiconductor device including a heat spreader
CN104412382A (zh) 半导体装置
US20040222515A1 (en) Double-sided cooling isolated packaged power semiconductor device
US20220102249A1 (en) Dual side cooling power module and manufacturing method of the same
CN104064529A (zh) 半导体器件、半导体模块以及制造半导体器件和半导体模块的方法
US11935811B2 (en) Baseplate for a semiconductor module and method for producing a baseplate
CN104851843A (zh) 电力用半导体装置
CN107634036B (zh) 半导体装置
CN114078790A (zh) 功率半导体模块装置及其制造方法
US10848074B2 (en) High voltage bridge rectifier
CN113113391A (zh) 用于双面功率模块的引线框间隔件
CN116137259A (zh) 半导体装置
JP2012209469A (ja) 電力用半導体装置
US20230163093A1 (en) Semiconductor device
JP7489933B2 (ja) 半導体装置及びその製造方法
US20230028808A1 (en) Semiconductor device
US11462504B2 (en) Semiconductor apparatus
KR102459361B1 (ko) 파워 모듈 패키지
WO2024053084A1 (ja) 半導体装置
WO2023021589A1 (ja) 半導体装置
WO2015079808A1 (ja) 半導体装置
JP6827402B2 (ja) 半導体装置
CN114975331A (zh) 半导体装置及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination