CN116110970A - Metal oxide terminal diamond field effect transistor and preparation method thereof - Google Patents

Metal oxide terminal diamond field effect transistor and preparation method thereof Download PDF

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Publication number
CN116110970A
CN116110970A CN202310121971.0A CN202310121971A CN116110970A CN 116110970 A CN116110970 A CN 116110970A CN 202310121971 A CN202310121971 A CN 202310121971A CN 116110970 A CN116110970 A CN 116110970A
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metal oxide
metal
diamond
gate
oxide
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蔚翠
周闯杰
何泽召
郭建超
马孟宇
余浩
刘庆彬
杨玉章
冯志红
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CETC 13 Research Institute
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CETC 13 Research Institute
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66015Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045Field-effect transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

The application is applicable to the technical field of semiconductors, and provides a metal oxide terminal diamond field effect transistor and a preparation method thereof, wherein the metal oxide terminal diamond field effect transistor comprises: a diamond substrate; the source electrode and the drain electrode are respectively arranged on two sides of the upper surface of the diamond substrate; the metal oxide terminal is arranged on the upper surface of the diamond substrate and is positioned between the source electrode and the drain electrode; the gate dielectric layer is arranged on the upper surface of the metal oxide terminal; and the grid electrode is arranged on the upper surface of the grid dielectric layer. According to the lattice matching method for the metal oxide terminal and the gate dielectric, the interface state density can be effectively reduced, the quality of the gate dielectric deposited on the upper surface of the metal oxide terminal is improved, and then the metal oxide terminal diamond has high carrier mobility, so that the metal oxide terminal diamond field effect transistor has good direct current and radio frequency performance.

Description

Metal oxide terminal diamond field effect transistor and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a metal oxide terminal diamond field effect transistor and a preparation method thereof.
Background
The diamond has the advantages of materials such as wide band gap, high carrier mobility, high carrier saturation drift velocity, low dielectric constant, radiation resistance, corrosion resistance and the like, and is a final semiconductor material for realizing high-frequency power devices. Currently, diamond field effect transistors are mainly based on hydrogen terminated diamond, i.e. a layer of carbon atoms on the surface of the diamond is connected with a layer of hydrogen atoms to form a negative electron affinity system, electrons on the surface of the diamond are transferred to an adsorption layer, and a layer of two-dimensional hole gas (2 DHG) is generated at a near-surface position, i.e. a hydrogen termination is formed.
However, hydrogen terminated diamond field effect transistors typically employ aluminum oxide (Al 2 O 3 ) As a gate medium, the carrier mobility of the diamond at the hydrogen terminal is lower due to the high interface state density between the hydrogen terminal and the alumina and the low medium quality of the alumina, so that the direct current and radio frequency performance of the diamond field effect transistor is further limited, and meanwhile, as a carbon hydrogen bond is positioned on the outermost layer of the diamond, the medium deposition process of photoetching glue dirt, high-energy plasma or oxygen-containing atmosphere needs to be avoided in the preparation of a device, and the preparation process is complex.
Disclosure of Invention
The embodiment of the application provides a metal oxide terminal diamond field effect transistor and a preparation method thereof, so as to solve the technical problem that the current hydrogen terminal diamond field effect transistor has low direct current and radio frequency performance due to low carrier mobility of hydrogen terminal diamond.
The application is realized by the following technical scheme:
in a first aspect, embodiments of the present application provide a metal oxide termination diamond field effect transistor comprising: a diamond substrate; the source electrode and the drain electrode are respectively arranged on two sides of the upper surface of the diamond substrate; the metal oxide terminal is arranged on the upper surface of the diamond substrate and is positioned between the source electrode and the drain electrode; the gate dielectric layer is arranged on the upper surface of the metal oxide terminal; and the grid electrode is arranged on the upper surface of the grid dielectric layer.
With reference to the first aspect, in some possible implementations, the diamond substrate is single crystal diamond or polycrystalline diamond; the gate dielectric is silicon oxide, titanium oxide, aluminum oxide, copper oxide, nickel oxide or zinc oxide; the gate dielectric layer is a single dielectric layer or a multi-dielectric layer; the thickness of the gate dielectric layer is 1-500 nm; the shape of the grid electrode is one or a combination of a plurality of straight grid, T-shaped grid, TT-shaped grid, U-shaped grid and Y-shaped grid.
In a second aspect, embodiments of the present application provide a method for manufacturing a metal oxide termination diamond field effect transistor, including: and photoetching a source region and a drain region on the upper surface of the diamond substrate, depositing ohmic contact metal on the source region and the drain region, and performing first annealing treatment on the sample to enable the ohmic contact metal to react with the upper surface of the diamond substrate in the corresponding region so as to form a source electrode and a drain electrode. The source drain regions are positioned on two sides of the upper surface of the diamond substrate. And photoetching a mesa region on the upper surface of the diamond substrate, depositing metal or metal oxide in the mesa region, and performing second annealing treatment on the sample to enable the metal or metal oxide to react with the upper surface of the diamond substrate in the corresponding region to form a metal oxide terminal. The mesa region is located between the source and drain. And depositing a gate dielectric on the upper surface of the metal oxide terminal to form a gate dielectric layer. And photoetching a gate on the upper surface of the gate dielectric layer, depositing gate metal, and stripping the gate metal to form a gate.
With reference to the second aspect, in some possible implementations, photolithography of a source drain region on an upper surface of the diamond substrate, depositing ohmic contact metal on the source drain region, includes: coating photoresist on the upper surface of the diamond substrate except the source and drain regions; depositing ohmic contact metal in the source/drain region; the photoresist is removed.
With reference to the second aspect, in some possible implementations, photolithography of a mesa region on an upper surface of the diamond substrate, deposition of a metal or metal oxide in the mesa region, includes: coating photoresist on the upper surface of the diamond substrate except the table-board area; depositing a metal or metal oxide in the mesa region; the photoresist is removed.
With reference to the second aspect, in some possible implementations, the steps of photoetching a gate on an upper surface of the gate dielectric layer and depositing a gate metal, and stripping the gate metal to form a gate electrode include: coating photoresist on the upper surface of the gate dielectric layer, the upper surface of the source electrode and the upper surface of the drain electrode; a gate metal window is made on the photoresist on the upper surface of the gate dielectric layer through photoetching; forming a gate electrode by depositing and stripping gate metal; the photoresist is removed.
With reference to the second aspect, in some possible implementations, before the source drain region is etched on the upper surface of the diamond substrate, the method includes: cleaning the diamond substrate; and forming a carbon-hydrogen bond layer on the upper surface of the diamond substrate by adopting a microwave plasma chemical vapor deposition mode.
With reference to the second aspect, in some possible implementations, after performing the second annealing treatment on the sample, the method includes: and removing unreacted metal or metal oxide in the mesa region by adopting wet etching and/or dry etching.
With reference to the second aspect, in some possible implementations, the metal is titanium, aluminum, copper, nickel, or zinc; the metal oxide is titanium oxide, aluminum oxide, copper oxide, nickel oxide or zinc oxide; the thickness of the metal or metal oxide is 0.1-2 nm.
With reference to the second aspect, in some possible implementations, the annealing temperature in the first annealing treatment is 400-1000 ℃, and the annealing condition is a hydrogen atmosphere; in the second annealing treatment, the annealing temperature is 400-1000 ℃, and the annealing condition is oxygen, ozone or mixed gas atmosphere.
It will be appreciated that the advantages of the second aspect may be found in the relevant description of the first aspect, and will not be described in detail herein.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
according to the metal oxide terminal diamond field effect transistor, the metal oxide terminal and the gate dielectric are in lattice matching, so that the interface state density can be effectively reduced, the quality of the gate dielectric deposited on the upper surface of the metal oxide terminal is improved, the metal oxide terminal diamond has high carrier mobility, and the metal oxide terminal diamond field effect transistor has good direct current and radio frequency performance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a metal oxide termination diamond field effect transistor according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for fabricating a metal oxide termination diamond field effect transistor according to one embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional structure diagram corresponding to a method for manufacturing a metal oxide termination diamond field effect transistor according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Furthermore, references to "a plurality of" in the examples of this application should be interpreted as two or more.
Fig. 1 is a schematic cross-sectional view of a metal oxide termination diamond field effect transistor according to an embodiment of the present application. As shown in fig. 1, the metal oxide termination diamond field effect transistor comprises:
a diamond substrate 1; the source electrode 2 and the drain electrode 3 are respectively arranged on two sides of the upper surface of the diamond substrate 1; a metal oxide terminal 5 disposed on the upper surface of the diamond substrate 1 and located between the source electrode 2 and the drain electrode 3; the gate dielectric layer 6 is arranged on the upper surface of the metal oxide terminal 5; and a gate electrode 7 arranged on the upper surface of the gate dielectric layer 6.
Wherein the diamond substrate 1 is single crystal diamond or polycrystalline diamond. The gate dielectric is silicon oxide (SiO) x ) Titanium oxide (TiO) x ) Aluminum oxide (AlO) x ) Copper oxide (CuO) x ) Nickel oxide (NiO) x ) Or zinc oxide (ZnO) x ) Etc. The gate dielectric layer 6 is a single dielectric layer or a multi-dielectric layer, and the thickness of the gate dielectric layer 6 is 1-500 nm. The shape of the grid electrode 7 is one or a combination of a plurality of straight grid, T-shaped grid, TT-shaped grid, U-shaped grid and Y-shaped grid.
The method for manufacturing the metal oxide termination diamond field effect transistor according to the embodiment of the present application is described in detail below with reference to fig. 1.
Fig. 2 is a flow chart of a method for manufacturing a metal oxide termination diamond field effect transistor according to an embodiment of the present application. Fig. 3 is a schematic cross-sectional structure diagram corresponding to a method for manufacturing a metal oxide termination diamond field effect transistor according to an embodiment of the present application. Referring to fig. 2 and 3, the method is described in detail as follows:
and 101, photoetching a source region and a drain region on the upper surface of the diamond substrate, depositing ohmic contact metal on the source region and the drain region, and performing first annealing treatment on the sample to enable the ohmic contact metal to react with the upper surface of the diamond substrate in the corresponding region so as to form a source electrode and a drain electrode.
Wherein, referring to (a) - (b) in fig. 3, source and drain regions are located at both sides of the upper surface of the diamond substrate 1. Accordingly, the source electrode 2 and the drain electrode 3 are formed to be located on both sides of the upper surface of the diamond substrate 1, respectively. The ohmic contact metal reacts with the upper surface of the diamond substrate 1 in contact therewith to form a source electrode 2 and a drain electrode 3.
The annealing temperature in the first annealing treatment is 400-1000 ℃ and the annealing condition is hydrogen atmosphere. The ohmic contact metal may be Ti/Au, ti/Pt/Au, tiW/Pt/Au, pd/Au, cr/Au, etc.
In one possible implementation manner, source and drain regions are subjected to photoetching on the upper surface of the diamond substrate, and ohmic contact metal is deposited on the source and drain regions, which specifically can comprise:
coating photoresist on the upper surface of the diamond substrate except the source and drain regions; depositing ohmic contact metal in the source/drain region; the photoresist is removed.
And 102, photoetching a mesa region on the upper surface of the diamond substrate, depositing metal or metal oxide in the mesa region, and performing second annealing treatment on the sample to enable the metal or metal oxide to react with the upper surface of the diamond substrate in the corresponding region to form a metal oxide terminal.
Wherein, referring to (c) - (d) in fig. 3, the mesa region is located between the source electrode 2 and the drain electrode 3.
The annealing temperature in the second annealing treatment is, for example, 400 to 1000 ℃, and the annealing conditions are oxygen, ozone, a mixed gas of oxygen and argon, nitrogen, or the like, or a mixed gas atmosphere of ozone and argon, nitrogen, or the like.
For example, when a metal is deposited on the mesa region, the metal may be titanium, aluminum, copper, nickel, zinc, or the like, and the metal deposition method may be thermal evaporation, electron beam evaporation, atomic layer deposition, magnetron sputtering, or the like. When depositing metal oxide in the mesa region, the metal oxide may be titanium oxide, aluminum oxide, copper oxide, nickel oxide, zinc oxide, or the like, and the metal oxide deposition method may be atomic layer deposition, thermal evaporation, magnetron sputtering, metal autoxidation, or the like. The thickness of the deposited metal or metal oxide 4 is 0.1-2 nm.
Illustratively, the metal or metal oxide 4 deposited in the mesa region reacts with, i.e., alloys, the upper surface of the diamond substrate 1 in the corresponding region therebelow in a second annealing process, forming a layer of Two-dimensional hole gas (Two-dimensional hole gas, abbreviated as 2 DHG) on the upper surface of the diamond substrate 1, i.e., forming the metal oxide termination 5. A metal oxide termination 5 is formed on the upper surface of the diamond substrate 1, resulting in a metal oxide termination diamond as a conductive channel.
The lattice matching between the metal oxide terminal and the gate dielectric can effectively reduce the interface trap density, namely the interface state density, and simultaneously can ensure the high quality of the gate dielectric deposited on the upper surface of the metal oxide terminal, so that the metal oxide terminal diamond has high carrier mobility, and the metal oxide terminal diamond field effect transistor has good direct current and radio frequency performance and good temperature stability.
In one possible embodiment, the mesa region is lithographically formed on the upper surface of the diamond substrate, and the metal or metal oxide is deposited on the mesa region, which may include:
coating photoresist on the upper surface of the diamond substrate except the table-board area; depositing a metal or metal oxide in the mesa region; the photoresist is removed.
And 103, depositing a gate dielectric on the upper surface of the metal oxide terminal to form a gate dielectric layer.
Wherein, referring to (e) in fig. 3, the gate dielectric is silicon oxide, titanium oxide, aluminum oxide, copper oxide, nickel oxide, zinc oxide, or the like. The gate dielectric layer 6 is a single dielectric layer or a multi-dielectric layer, and the thickness of the gate dielectric layer 6 is 1-500 nm.
And 104, photoetching a gate on the upper surface of the gate dielectric layer, depositing gate metal, and stripping the gate metal to form a gate.
In a possible implementation manner, in step 104, the method specifically may include:
coating photoresist on the upper surface of the gate dielectric layer, the upper surface of the source electrode and the upper surface of the drain electrode; a gate metal window is made on the photoresist on the upper surface of the gate dielectric layer through photoetching; forming a gate electrode by depositing and stripping gate metal; the photoresist is removed.
Wherein, referring to (f) in fig. 3, the gate metal may be Al/Au or the like. The shape of the grid electrode 7 is one or a combination of a plurality of straight grid, T-shaped grid, TT-shaped grid, U-shaped grid and Y-shaped grid.
In one possible embodiment, before the source drain region is etched on the upper surface of the diamond substrate, the method includes: cleaning the diamond substrate; and forming a carbon-hydrogen bond layer on the upper surface of the diamond substrate by adopting a microwave plasma chemical vapor deposition mode.
Illustratively, a carbon-hydrogen bond layer is formed on the upper surface of the diamond substrate 1 to make it easier to form the metal oxide terminals 5 by reacting the metal or metal oxide 4 with the upper surface of the diamond substrate 1 in the corresponding region.
In one possible embodiment, after subjecting the sample to the second annealing treatment, the method comprises: and removing unreacted metal or metal oxide in the mesa region by adopting wet etching and/or dry etching.
According to the preparation method of the metal oxide terminal diamond field effect transistor, the metal oxide terminal is formed in the mesa area on the upper surface of the diamond substrate, so that the metal oxide terminal diamond is used as a conducting channel, and as the metal oxide terminal is in lattice matching with the gate dielectric, the interface trap density can be effectively reduced, namely the interface state density is reduced, and meanwhile, the high quality of the gate dielectric deposited on the upper surface of the metal oxide terminal can be ensured, so that the metal oxide terminal diamond has high carrier mobility, and the metal oxide terminal diamond field effect transistor has good direct current and radio frequency performance and good temperature stability. In addition, the metal oxide terminals are formed instead of the hydrogen terminals in the preparation method, and the medium deposition process of photoetching adhesive dirt, high-energy plasma or oxygen-containing atmosphere is not needed to be avoided, so that the preparation process is simple and easy to operate.
A simple example is based on an alumina-terminated diamond field effect transistor, which is prepared by the method of preparing a metal oxide terminated diamond field effect transistor of the present application comprising the steps of:
(1) And cleaning the monocrystalline diamond substrate, placing the cleaned diamond substrate in a hydrogen plasma atmosphere at 750 ℃, and treating the upper surface of the diamond substrate by adopting a microwave plasma chemical vapor deposition mode for 10 minutes to form a carbon-hydrogen bond layer.
(2) Photoetching a source region and a drain region on the upper surface of a diamond substrate, depositing ohmic contact metal Ti/Pt/Au on the source region and the drain region, placing a sample in a hydrogen atmosphere at 700 ℃ for annealing for 30 minutes, and forming a source electrode and a drain electrode by alloy.
(3) And photoetching a mesa region on the upper surface of the diamond substrate, wherein the mesa region is positioned between the source electrode and the drain electrode, depositing metal aluminum with the thickness of 1nm in the mesa region by an electron beam evaporation method, and placing a sample in an ozone atmosphere at 500 ℃ for annealing for 2 hours, so that the aluminum oxide terminal is formed by alloy. And removing unreacted metal aluminum and oxide thereof in the mesa region by a hydrofluoric acid wet etching mode.
(4) And placing the sample in a 400 ℃ environment, and depositing an aluminum oxide gate dielectric with the thickness of 50nm on the upper surface of the aluminum oxide terminal by adopting an atomic layer deposition mode to form a gate dielectric layer.
(5) And photoetching a gate on the upper surface of the gate dielectric layer, depositing and stripping gate metal Al/Au, and forming a T-shaped gate.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. A metal oxide termination diamond field effect transistor comprising:
a diamond substrate;
the source electrode and the drain electrode are respectively arranged on two sides of the upper surface of the diamond substrate;
the metal oxide terminal is arranged on the upper surface of the diamond substrate and is positioned between the source electrode and the drain electrode;
the gate dielectric layer is arranged on the upper surface of the metal oxide terminal;
and the grid electrode is arranged on the upper surface of the grid dielectric layer.
2. A metal oxide termination diamond field effect transistor according to claim 1, wherein the diamond substrate is single crystal diamond or polycrystalline diamond;
the gate dielectric is silicon oxide, titanium oxide, aluminum oxide, copper oxide, nickel oxide or zinc oxide; the gate dielectric layer is a single dielectric layer or a multi-dielectric layer; the thickness of the gate dielectric layer is 1-500 nm;
the shape of the grid is one or a combination of a plurality of straight grid, T-shaped grid, TT-shaped grid, U-shaped grid and Y-shaped grid.
3. A method of making a metal oxide termination diamond field effect transistor, comprising:
photoetching a source region and a drain region on the upper surface of a diamond substrate, depositing ohmic contact metal on the source region and the drain region, and performing first annealing treatment on a sample to enable the ohmic contact metal to react with the upper surface of the diamond substrate in a corresponding region so as to form a source electrode and a drain electrode; the source and drain regions are positioned on two sides of the upper surface of the diamond substrate;
photoetching a mesa region on the upper surface of the diamond substrate, depositing metal or metal oxide in the mesa region, and performing second annealing treatment on the sample to enable the metal or metal oxide to react with the upper surface of the diamond substrate in a corresponding region to form a metal oxide terminal; the mesa region is located between the source and drain electrodes;
depositing a gate dielectric on the upper surface of the metal oxide terminal to form a gate dielectric layer;
and photoetching a gate on the upper surface of the gate dielectric layer, depositing gate metal, and stripping the gate metal to form a gate.
4. A method of fabricating a metal oxide termination diamond field effect transistor according to claim 3, wherein the lithographically exposing a source drain region on the upper surface of the diamond substrate, depositing an ohmic contact metal on the source drain region, comprises:
coating photoresist on the upper surface of the diamond substrate except the source and drain regions;
depositing ohmic contact metal on the source/drain region;
and removing the photoresist.
5. A method of preparing a metal oxide terminated diamond field effect transistor according to claim 3, wherein said lithographically etching a mesa region on the upper surface of said diamond substrate, depositing a metal or metal oxide in said mesa region, comprises:
coating photoresist on the upper surface of the diamond substrate except the table-board area;
depositing a metal or metal oxide in the mesa region;
and removing the photoresist.
6. The method for preparing a metal oxide termination diamond field effect transistor according to claim 3, wherein the steps of performing a gate lithography and a gate metal deposition on the upper surface of the gate dielectric layer, and performing a lift-off of the gate metal to form a gate electrode comprise:
coating photoresist on the upper surfaces of the gate dielectric layer, the source electrode and the drain electrode;
a gate metal window is made on the photoresist on the upper surface of the gate dielectric layer through photoetching;
forming a gate electrode by depositing and stripping gate metal;
and removing the photoresist.
7. A method of fabricating a metal oxide termination diamond field effect transistor according to claim 3, comprising, prior to lithographically etching the source and drain regions on the upper surface of the diamond substrate:
cleaning the diamond substrate;
and forming a carbon-hydrogen bond layer on the upper surface of the diamond substrate by adopting a microwave plasma chemical vapor deposition mode.
8. A method of preparing a metal oxide termination diamond field effect transistor according to claim 3, comprising, after the second annealing the sample:
and removing unreacted metal or metal oxide in the mesa region by adopting wet etching and/or dry etching.
9. A method of preparing a metal oxide termination diamond field effect transistor according to claim 3 wherein the metal is titanium, aluminium, copper, nickel or zinc; the metal oxide is titanium oxide, aluminum oxide, copper oxide, nickel oxide or zinc oxide;
the thickness of the metal or metal oxide is 0.1-2 nm.
10. A method of preparing a metal oxide termination diamond field effect transistor according to claim 3, wherein the annealing temperature in the first annealing treatment is 400 to 1000 ℃, and the annealing condition is a hydrogen atmosphere; in the second annealing treatment, the annealing temperature is 400-1000 ℃, and the annealing condition is oxygen, ozone or mixed gas atmosphere.
CN202310121971.0A 2023-02-16 2023-02-16 Metal oxide terminal diamond field effect transistor and preparation method thereof Pending CN116110970A (en)

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CN202310121971.0A CN116110970A (en) 2023-02-16 2023-02-16 Metal oxide terminal diamond field effect transistor and preparation method thereof

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CN202310121971.0A CN116110970A (en) 2023-02-16 2023-02-16 Metal oxide terminal diamond field effect transistor and preparation method thereof

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CN116110970A true CN116110970A (en) 2023-05-12

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