CN116110790A - MOS device and preparation method thereof - Google Patents

MOS device and preparation method thereof Download PDF

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CN116110790A
CN116110790A CN202211086776.0A CN202211086776A CN116110790A CN 116110790 A CN116110790 A CN 116110790A CN 202211086776 A CN202211086776 A CN 202211086776A CN 116110790 A CN116110790 A CN 116110790A
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region
substrate
oxide layer
side wall
halo
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许昭昭
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a MOS device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a first substrate, a buried oxide layer and a second substrate; forming a grid structure; performing an ion implantation process to form a halo region, wherein a horizontal projection of the gate structure onto a plane of the second substrate overlaps the halo region; forming a protective oxide layer; forming a first side wall; performing an ion implantation process to form a lightly doped drain region; forming a second side wall; forming a source electrode and a drain electrode. After the grid structure is formed, halo implantation is directly carried out; and forming a protective oxide layer and a first side wall, and then performing LDD implantation. The LDD injection and the Halo injection are separated through the protective oxide layer and the first side wall, so that the interval from the junction position of the Halo region and the well region to the junction position of the LDD region and the Halo region is larger, the gradient of the LDD/Halo junction can be reduced, the electric field in the junction is reduced, and the GIDL current is reduced.

Description

MOS device and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a MOS device and a preparation method thereof.
Background
The switch tube DMOS (Double-diffused MOS) has the characteristics of high voltage resistance, high current driving capability, extremely low power consumption and the like, and is widely used in power management circuits at present.
In an LDMOS (Lateral Double-diffused MOS) device, on-state resistance r_sp and breakdown voltage BV, off-state leakage current i_off are important parameter indicators of the LDMOS device, wherein one type of off-state leakage current is GIDL (Gate induced drain leakage ). How to obtain higher breakdown voltage, lower R_sp and lower off-state leakage current can improve the competitiveness of LDMOS device products.
In the existing low-voltage-section switch device structure in the PD-SOI process, the LDD and Halo processes of the existing process are injected simultaneously, the formed LDD and Halo shapes are formed, and the range formed by Halo injection completely encloses the LDD. GIDL is generated at the junction formed by LDD and Halo, so that GIDL can be optimized by optimizing the junction, but Halo implantation regions in the existing device structure are narrower, so that the LDD region and Halo implantation regions are both very heavily doped, resulting in that the junction surface of the device is easy to generate higher GIDL current.
Disclosure of Invention
The application provides a MOS device and a preparation method thereof, which can solve the problem that the junction surface of the device is easy to generate higher GIDL current.
In one aspect, an embodiment of the present application provides a method for manufacturing a MOS device, including:
providing a substrate, the substrate comprising: the first substrate, the buried oxide layer and the second substrate are stacked in sequence; a shallow trench isolation structure and a well region positioned between the shallow trench isolation structures are formed in the second substrate; a gate oxide layer and a polysilicon layer which are stacked in sequence are formed on the second substrate;
etching the polysilicon layer and the gate oxide layer to the surface of the second substrate to obtain a gate structure, and exposing a source drain region;
performing an ion implantation process on the source-drain region to form a halo region in the well region, wherein a horizontal projection of the gate structure onto a plane where the second substrate is located overlaps with the halo region;
forming a protective oxide layer, wherein the protective oxide layer covers the side wall and the upper surface of the grid structure;
forming a first side wall, wherein the first side wall is positioned on the surface of the source drain region at the side of the protective oxide layer;
performing an ion implantation process on the source-drain region to form a lightly doped drain region in the halo region, wherein the lightly doped drain region is far away from a well region at the bottom of the gate structure;
forming a second side wall, wherein the second side wall is positioned on the surface of the source-drain region at the side of the first side wall;
and performing an ion implantation process on the source-drain region to form a source electrode and a drain electrode in the lightly doped drain region respectively.
Optionally, in the method for manufacturing the MOS device, a lateral dimension of an overlapping region between the halo region and a horizontal projection of the gate structure onto a plane on which the second substrate is located is
Figure BDA0003835453980000021
Optionally, in the method for manufacturing the MOS device, a thermal oxidation process is used to oxidize the sidewall and the upper surface of the gate structure to form the protection oxide layer.
Optionally, in the method for manufacturing a MOS device, after performing an ion implantation process on the source-drain region to form a source and a drain in the lightly doped drain region, the method for manufacturing a MOS device further includes:
and removing the protective oxide layer on the upper surface of the gate structure.
Optionally, in the method for manufacturing a MOS device, the first sidewall is a first silicon oxide layer, a first silicon nitride layer, or a stack of the first silicon oxide layer and the first silicon nitride layer; in the lamination of the first silicon oxide layer and the first silicon nitride layer, the first silicon oxide layer covers the side surface of the protection oxide layer, and the first silicon nitride layer covers the side surface of the first silicon oxide layer.
Optionally, in the method for manufacturing a MOS device, the second sidewall is a second silicon dioxide layer, a second silicon nitride layer, or a stack of the second silicon dioxide layer and the second silicon nitride layer; in the lamination of the second silicon dioxide layer and the second silicon nitride layer, the second silicon dioxide layer covers the side surface of the first side wall, and the second silicon nitride layer covers the side surface of the second silicon dioxide layer.
Optionally, in the method for manufacturing the MOS device, the thickness of the substrate is
Figure BDA0003835453980000022
On the other hand, the embodiment of the application also provides a MOS device, which comprises:
a substrate, the substrate comprising: the first substrate, the buried oxide layer and the second substrate are stacked in sequence; a shallow trench isolation structure and a well region positioned between the shallow trench isolation structures are formed in the second substrate;
a gate structure located on the second substrate surface;
the halo region is positioned in the well region of the source-drain region at the side of the gate structure, and the horizontal projection of the gate structure on the plane where the second substrate is positioned overlaps with the halo region;
the protective oxide layer covers the side wall and the upper surface of the grid structure;
the first side wall is positioned on the surface of the source drain region at the side of the protective oxide layer;
the lightly doped drain region is positioned in the halo region and is far away from the well region at the bottom of the grid structure;
the second side wall is positioned on the surface of the source-drain region at the side of the first side wall;
the source electrode and the drain electrode are respectively positioned in the lightly doped drain regions at two sides of the second side wall.
Optionally, in the MOS device, a lateral dimension of an overlapping region of the halo region and a horizontal projection of the gate structure onto a plane on which the second substrate is located is
Figure BDA0003835453980000031
The technical scheme of the application at least comprises the following advantages:
LDD injection and Halo injection are not carried out at the same time, and Halo injection is directly carried out after a grid structure is formed; and (3) oxidizing the grid structure, forming a first side wall, and then carrying out LDD injection to form a lightly doped drain region. The LDD injection and the Halo injection are separated through the protection oxide layer and the first side wall, so that the interval from the junction position of the Halo region and the well region to the junction position of the LDD region and the Halo region is larger, the gradient of an LDD/Halo junction formed by the LDD region and the Halo region can be reduced, the electric field in the LDD/Halo junction is reduced, the GIDL current is reduced, and the electric performance of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing a MOS device according to an embodiment of the present invention;
fig. 2-9 are schematic views of a semiconductor structure in various process steps for fabricating a MOS device according to an embodiment of the invention;
fig. 10 is a schematic diagram showing a comparison of an IdVg curve of a conventional MOS device and an IdVg curve of a MOS device provided by an embodiment of the present invention;
wherein reference numerals are as follows:
101-a first substrate, 102-a buried oxide layer, 103-a second substrate, 104-a shallow trench isolation structure, 105-a gate oxide layer, 106-a polysilicon layer, 11-a gate structure, 107-halo region, 108-a lightly doped drain region, 109-a source/drain, 201-a protective oxide layer, 202-a first side wall and 203-a second side wall.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The inventor researches that the transverse dimension of the overlapped area of the horizontal projection of the grid structure of the MOS device on the plane of the substrate and the halo region is smaller than that of the overlapped area due to the limitation of the process conditions
Figure BDA0003835453980000041
That is, the narrower Halo implant region in the prior device structure results in a high GIDL current readily generated at the Halo/LDD junction surface of the device, which severely affects device performance and may even lead to device failure.
Based on the above-mentioned problems, the embodiment of the present application provides a method for manufacturing a MOS device, please refer to fig. 1, and fig. 1 is a flowchart of a method for manufacturing a MOS device according to an embodiment of the present invention.
Specifically, referring to fig. 2-9, fig. 2-9 are schematic semiconductor structures in the process steps of preparing a MOS device according to an embodiment of the invention.
The preparation method of the MOS device comprises the following steps:
step S10: as shown in fig. 2, a substrate is provided, the substrate including: a first substrate 101, a buried oxide layer 102, and a second substrate 103 stacked in this order; a shallow trench isolation structure 104 and a well region between the shallow trench isolation structures 104 are formed in the second substrate 103; the second substrate 103 has a gate oxide layer 105 and a polysilicon layer 106 formed thereon, which are stacked in order. Specifically, the total thickness of the substrate may be
Figure BDA0003835453980000051
Figure BDA0003835453980000052
In this embodiment, if the device is a PMOS device, the well region is an N-well; if the device is an NMOS device, the well region is a P-well.
Step S20: as shown in fig. 3, the polysilicon layer 106 and the gate oxide layer 105 are etched to the surface of the second substrate 103 to obtain the gate structure 11, and at the same time, the source and drain regions on the gate structure 11 side are exposed.
Step S30: as shown in fig. 4, an ion implantation process is performed on the source-drain region to form a halo region 107 in the well region, where a horizontal projection of the gate structure 11 onto a plane of the second substrate 103 overlaps with the halo region 107.
In this embodiment, the lateral dimension a of the overlapping region of the halo region and the horizontal projection of the gate structure 11 onto the plane of the second substrate may be
Figure BDA0003835453980000053
Step S40: as shown in fig. 5, a protective oxide layer 201 is formed, and the protective oxide layer 201 covers the sidewalls and the upper surface of the gate structure 11. Specifically, in this embodiment, a thermal oxidation process may be used to oxidize the sidewall and the upper surface of the gate structure 11 to form the protection oxide layer 201.
Step S50: as shown in fig. 6, a first sidewall 202 is formed, and the first sidewall 202 is located on the surface of the source-drain region on the side of the protection oxide layer 201. Specifically, the first side wall 202 may be: a first silicon oxide layer, a first silicon nitride layer, or a combined stack of the first silicon oxide layer and the first silicon nitride layer. In the stack of the first silicon oxide layer and the first silicon nitride layer, the first silicon oxide layer covers the side surface of the protection oxide layer 201, and the first silicon nitride layer covers the side surface of the first silicon oxide layer.
Step S60: as shown in fig. 7, an ion implantation process is performed on the source and drain regions to form lightly doped drain regions 108 in the halo region 107. Specifically, the lightly doped drain region 108 is far away from the well region at the bottom of the gate structure 11.
The LDD implantation and Halo implantation are not performed simultaneously, specifically, after the gate structure 11 is formed, halo implantation is directly performed to obtain the Halo region 107; the Lightly Doped Drain (LDD) region 108 is formed by performing an LDD implantation after the gate structure 11 is oxidized to form the first sidewall 202. The LDD injection and the Halo injection are separated through the protective oxide layer and the first side wall, so that the interval b from the junction position of the Halo region and the well region to the junction position of the LDD region and the Halo region is larger, the gradient of the LDD/Halo junction formed by the LDD region 108 and the Halo region 107 can be reduced, the electric field in the LDD/Halo junction is reduced, the GIDL current is reduced, and the electric performance of the device is improved.
Step S70: as shown in fig. 8, a second sidewall 203 is formed, where the second sidewall 203 is located on the surface of the source-drain region on the side of the first sidewall 202. Specifically, the second side wall 203 may be: a second silicon oxide layer, a second silicon nitride layer, or a stack of the second silicon oxide layer and the second silicon nitride layer; wherein, in the lamination of the second silicon oxide layer and the second silicon nitride layer, the second silicon oxide layer covers the side surface of the first side wall 202, and the second silicon nitride layer covers the side surface of the second silicon oxide layer.
Step S80: as shown in fig. 9, an ion implantation process is performed on the source and drain regions to form a heavily doped region 109 in the lightly doped drain region 108, i.e., a source 109 is formed in one of the lightly doped drain regions 108 and a drain 109 is formed in the other of the lightly doped drain regions 108.
Further, after performing an ion implantation process on the source-drain region to form a source and a drain in the lightly doped drain region, the method for manufacturing the MOS device may further include: the protective oxide layer on the upper surface of the gate structure 11 is removed to expose at least a portion of the surface of the polysilicon layer 106, and in this embodiment, at least a portion of the surface of the polysilicon layer 106 is exposed for extracting the polysilicon gate to the surface of the semiconductor structure formed in the subsequent process.
Referring to fig. 10, fig. 10 is a schematic diagram showing a comparison of an IdVg curve of a conventional MOS device and an IdVg curve of a MOS device according to an embodiment of the present invention. In fig. 10, the abscissa represents the gate voltage Vg and the ordinate represents the current I d The voltage/current settings at the other ends of the device are as follows: the drain terminal voltage can be set to 0.05V, the substrate voltage can be set to-2.5V, the source terminal is grounded, and the gate terminal voltage is swept from-2.5V to obtain an IdVg curve of a traditional MOS device (original structure) and an IdVg curve of the MOS device (new structure) provided by the embodiment of the invention. The current I at vg= -2.5V in the defined curve d Is GIDL current (Gate Induced Drain Leakage). As can be seen from the graph, TCAD simulation shows that, under the condition of the same bias voltage, the GIDL of the MOS device (new structure) provided by the embodiment of the present invention can be reduced by about 2 orders of magnitude compared with the GIDL of the conventional MOS device (original structure) under the condition of Vth increase; where Vth represents the threshold voltage (Threshold voltage), and the closer to the right the IdVg curve represents the larger Vth value.
Based on the same inventive concept, the embodiment of the present application further provides a MOS device, as shown in fig. 9, where the MOS device includes:
a substrate, the substrate comprising: a first substrate 101, a buried oxide layer 102, and a second substrate 103 stacked in this order; a shallow trench isolation structure 104 and a well region between the shallow trench isolation structures 104 are formed in the second substrate 103;
a gate structure 11, the gate structure 11 being located on the surface of the second substrate 103, the gate structure 11 including a stacked gate oxide layer 105 and a polysilicon layer 106;
a halo region 107, where the halo region 107 is located in the well region of the source-drain region on the gate structure 11 side, and a horizontal projection of the gate structure 11 onto a plane on which the second substrate 103 is located overlaps with the halo region 107;
a protective oxide layer 201, wherein the protective oxide layer 201 covers the side wall and the upper surface of the gate structure 11;
a first side wall 202, where the first side wall 202 is located on the surface of the source drain region on the side of the protection oxide layer 201;
a lightly doped drain region 108, wherein the lightly doped drain region 108 is located in the halo region 107 and is far away from a well region at the bottom of the gate structure 11;
the second side wall 203 is located on the surface of the source-drain region on the side of the first side wall 202, and the second side wall 203 is located on the surface of the source-drain region on the side of the first side wall 202;
and a source 109 and a drain 109, which are respectively located in the lightly doped drain region 108 at two sides of the second sidewall 203.
Further, the overlapping area of the halo region 107 and the horizontal projection of the gate structure 11 onto the plane of the second substrate 103 may be of a lateral dimension
Figure BDA0003835453980000081
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (9)

1. The preparation method of the MOS device is characterized by comprising the following steps of:
providing a substrate, the substrate comprising: the first substrate, the buried oxide layer and the second substrate are stacked in sequence; a shallow trench isolation structure and a well region positioned between the shallow trench isolation structures are formed in the second substrate; a gate oxide layer and a polysilicon layer which are stacked in sequence are formed on the second substrate;
etching the polysilicon layer and the gate oxide layer to the surface of the second substrate to obtain a gate structure, and exposing a source drain region;
performing an ion implantation process on the source-drain region to form a halo region in the well region, wherein a horizontal projection of the gate structure onto a plane where the second substrate is located overlaps with the halo region;
forming a protective oxide layer, wherein the protective oxide layer covers the side wall and the upper surface of the grid structure;
forming a first side wall, wherein the first side wall is positioned on the surface of the source drain region at the side of the protective oxide layer;
performing an ion implantation process on the source-drain region to form a lightly doped drain region in the halo region, wherein the lightly doped drain region is far away from a well region at the bottom of the gate structure;
forming a second side wall, wherein the second side wall is positioned on the surface of the source-drain region at the side of the first side wall;
and performing an ion implantation process on the source-drain region to form a source electrode and a drain electrode in the lightly doped drain region respectively.
2. The method of manufacturing a MOS device according to claim 1, wherein a lateral dimension of an overlap region between a horizontal projection of the gate structure onto a plane on which the second substrate is located and the halo region is
Figure FDA0003835453970000011
3. The method for manufacturing a MOS device according to claim 1, wherein a thermal oxidation process is used to oxidize a sidewall and an upper surface of the gate structure to form the protective oxide layer.
4. The method of manufacturing a MOS device according to claim 1, wherein after performing an ion implantation process on the source and drain regions to form a source and a drain, respectively, in the lightly doped drain region, the method of manufacturing a MOS device further comprises:
and removing the protective oxide layer on the upper surface of the gate structure.
5. The method for manufacturing a MOS device according to claim 1, wherein the first sidewall is a first silicon oxide layer, a first silicon nitride layer, or a stack of the first silicon oxide layer and the first silicon nitride layer; in the lamination of the first silicon oxide layer and the first silicon nitride layer, the first silicon oxide layer covers the side surface of the protection oxide layer, and the first silicon nitride layer covers the side surface of the first silicon oxide layer.
6. The method for manufacturing a MOS device according to claim 1, wherein the second sidewall is a second silicon dioxide layer, a second silicon nitride layer, or a stack of the second silicon dioxide layer and the second silicon nitride layer; in the lamination of the second silicon dioxide layer and the second silicon nitride layer, the second silicon dioxide layer covers the side surface of the first side wall, and the second silicon nitride layer covers the side surface of the second silicon dioxide layer.
7. The method for manufacturing a MOS device according to claim 1, wherein the thickness of the substrate is
Figure FDA0003835453970000021
8. A MOS device, comprising:
a substrate, the substrate comprising: the first substrate, the buried oxide layer and the second substrate are stacked in sequence; a shallow trench isolation structure and a well region positioned between the shallow trench isolation structures are formed in the second substrate;
a gate structure located on the second substrate surface;
the halo region is positioned in the well region of the source-drain region at the side of the gate structure, and the horizontal projection of the gate structure on the plane where the second substrate is positioned overlaps with the halo region;
the protective oxide layer covers the side wall and the upper surface of the grid structure;
the first side wall is positioned on the surface of the source drain region at the side of the protective oxide layer;
the lightly doped drain region is positioned in the halo region and is far away from the well region at the bottom of the grid structure;
the second side wall is positioned on the surface of the source-drain region at the side of the first side wall;
the source electrode and the drain electrode are respectively positioned in the lightly doped drain regions at two sides of the second side wall.
9. The MOS device of claim 8, wherein a lateral dimension of an overlap region of the halo region and a horizontal projection of the gate structure onto a plane of the second substrate is
Figure FDA0003835453970000022
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CN202211086776.0A 2022-09-07 2022-09-07 MOS device and preparation method thereof Pending CN116110790A (en)

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