CN116107855A

CN116107855A - Test method, system, chip, electronic device and storage medium

Info

Publication number: CN116107855A
Application number: CN202310145799.2A
Authority: CN
Inventors: 汤志锋; 黄志鑫; 吴文鸣
Original assignee: Xiamen Ziguang Zhanrui Technology Co ltd
Current assignee: Xiamen Ziguang Zhanrui Technology Co ltd
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2023-05-12

Abstract

The invention discloses a testing method, a testing system, a chip, electronic equipment and a storage medium, wherein the testing method comprises the following steps: acquiring test data and current running state of a chip; testing the chip based on the test data and the test strategy corresponding to the running state to obtain a test result of the chip; on the basis of being capable of automatically testing the chip, the chip is further tested by combining the testing strategy corresponding to the running state of the current chip, so that the tested data can be attached to a real use scene, the testing time can be shortened, the testing efficiency can be improved, the testing labor cost can be saved, and the reliability of the testing result of the chip can be improved.

Description

Test method, system, chip, electronic device and storage medium

Technical Field

The present invention relates to the field of testing technologies, and in particular, to a testing method, a testing system, a chip, an electronic device, and a storage medium.

Background

When a chip, for example, a central processing unit (Central Processing Unit, CPU) is running, system power consumption increases if the CPU voltage is too high; the system running speed is slow if the CPU frequency is too low; the system operation is suspended if the frequency is too high and the voltage is insufficient; the CPU load is higher and the frequency is higher, but the CPU load is lower, the frequency is not higher, and the frequency is smaller, so that the power consumption is reduced. Therefore, in the chip development stage, performance data of the chip needs to be obtained through a series of tests, so as to define working parameters and specifications of the chip.

The performance test mode of the chip at present is that after a tester starts up a terminal, an adb (Android Debug Bridge ) or an adb-based PC (personal computer ) tool is used to modify the frequency and voltage of a CPU by driving a supported frequency or voltage node through CPUFReq (a driving type); and combining the last test result, modifying other frequency/voltage values for multiple times, and testing the optimal performance frequency/voltage state. The method not only needs to manually modify the frequency/voltage one by one through the adb to test the optimal frequency/voltage value, but also can observe the state of the mobile phone from time to judge the test result of a certain group of data, and has low efficiency and easy misoperation.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a testing method, a testing system, a testing chip, electronic equipment and a storage medium.

The invention solves the technical problems by the following technical scheme:

the invention provides a test method, which comprises the following steps:

acquiring test data and current running state of a chip;

and testing the chip based on the test data and the test strategy corresponding to the running state so as to obtain a test result of the chip.

Preferably, the test data includes a preset voltage and a preset frequency;

the testing the chip based on the test data and the test strategy corresponding to the running state comprises the following steps:

judging whether the chip triggers restarting according to the running state;

if yes, gradually increasing the voltage on the basis of the preset voltage by a preset first step length, and testing the chip by combining the voltage with a preset frequency;

if not, gradually reducing the voltage based on the preset voltage by the preset first step length, and testing the chip by combining with the preset frequency;

and determining a first critical voltage corresponding to the chip under the preset frequency.

Preferably, the test data includes a preset voltage and a preset frequency;

the testing of the chip based on the test data and the test strategy corresponding to the running state further comprises:

judging whether the chip triggers restarting according to the running state;

if so, gradually reducing the frequency on the basis of the preset frequency by a preset second step length, and testing the chip by combining the frequency with a preset voltage;

if not, gradually increasing the frequency based on the preset frequency by using the preset second step length, and testing the chip by combining the frequency with the preset voltage;

And determining a first critical frequency corresponding to the chip under the preset voltage.

Preferably, the testing the chip based on the test data and the test policy corresponding to the operation state includes:

judging whether the temperature of the chip is smaller than a preset temperature threshold according to the running state; or judging whether the chip is not triggered to restart at the current temperature according to the running state;

if yes, gradually increasing the frequency on the basis of the preset frequency by a preset third step length, and testing the chip by combining the frequency with a preset voltage;

if not, gradually reducing the frequency on the basis of the preset frequency by the preset third step length, and testing the chip by combining the frequency with the preset voltage;

determining a second critical frequency corresponding to the preset voltage of the chip; wherein the preset third step size is larger than the preset second step size.

determining whether the chip triggers restarting under the current load according to the running state;

if yes, gradually reducing the frequency on the basis of the preset frequency by a preset fourth step length, and testing the chip by combining the frequency with a preset voltage;

If not, gradually increasing the frequency on the basis of the preset frequency by using the preset fourth step length, and testing the chip by combining the frequency with the preset voltage;

determining a third critical frequency corresponding to the preset voltage of the chip;

and/or the number of the groups of groups,

if yes, gradually reducing the voltage on the basis of the preset voltage by a preset fifth step length, and testing the chip by combining the voltage with the preset frequency;

if not, gradually increasing the voltage on the basis of the preset voltage by using the preset fifth step length, and testing the chip by combining the voltage with the preset frequency;

and determining a second critical voltage corresponding to the chip at the preset frequency.

Preferably, the test data includes a first voltage, a second voltage and a preset frequency of the chip, wherein the first voltage is smaller than the second voltage;

taking an intermediate value of the first voltage and the second voltage as a third voltage;

testing the chip based on the combination of the third voltage and the preset frequency, and judging whether the chip triggers restarting or not;

If yes, continuing to perform dichotomy processing according to the second voltage and the third voltage, and testing until the chip is not triggered to restart;

if not, continuing to perform dichotomy processing according to the first voltage and the third voltage, and performing testing until the chip triggers restarting;

determining a third critical voltage corresponding to the chip under the preset frequency;

and/or the number of the groups of groups,

the test data comprises a first frequency, a second frequency and a preset voltage of the chip, wherein the first frequency is smaller than the second frequency;

taking the intermediate value of the first frequency and the second frequency as a third frequency;

testing the chip based on the combination of the third frequency and the preset voltage, and judging whether the chip triggers restarting or not;

if yes, continuing to perform dichotomy processing according to the first frequency and the third frequency, and testing until the chip is not triggered to restart;

if not, continuing to perform dichotomy processing according to the second frequency and the third frequency, and testing until the chip triggers restarting;

And determining a fourth critical frequency corresponding to the chip under the preset voltage.

Preferably, the test method further comprises:

generating a frequency-voltage relation table according to the test result;

and adjusting the working voltage and the working frequency of the chip based on the frequency-voltage relation table and a preset scene.

The invention also provides a test system, comprising:

the acquisition module is used for acquiring test data and current running state of the chip;

and the test module is used for testing the chip based on the test data and the test strategy corresponding to the running state so as to obtain a test result of the chip.

Preferably, the test data includes a preset voltage and a preset frequency;

the test module judges whether the chip triggers restarting according to the running state;

Preferably, the test data includes a preset voltage and a preset frequency;

Preferably, the test module judges whether the temperature of the chip is less than a preset temperature threshold according to the running state; or judging whether the chip is not triggered to restart at the current temperature according to the running state;

Preferably, the test module determines whether the chip triggers restarting under the current load according to the running state;

and/or the number of the groups of groups,

the test module takes the intermediate value of the first voltage and the second voltage as a third voltage;

and/or the number of the groups of groups,

the test module takes the intermediate value of the first frequency and the second frequency as a third frequency;

Preferably, the test system further comprises:

the adjusting module is used for generating a frequency-voltage relation table according to the test result;

The invention also provides a chip comprising:

and a processor for executing computer program instructions stored in the memory, wherein the computer program instructions, when executed by the processor, trigger the chip to execute the computer program to implement the test method as described above.

The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the test method as described above when executing the computer program.

The invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the test method as described above.

On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the application.

The invention has the positive progress effects that: on the basis of realizing automatic test of the chip, the chip is further tested by combining with a test strategy corresponding to the running state of the current chip, so that the tested data can fit the real use scene, the test time can be shortened, the test efficiency can be improved, the test labor cost can be saved, and the reliability of the test result of the chip can be improved.

Drawings

Fig. 1 is a schematic flow chart of a test method according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a second flow chart of a test method according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a third flow chart of a test method according to an embodiment of the invention.

Fig. 4 is a fourth flowchart of a testing method according to an embodiment of the present invention.

Fig. 5 is a fifth flowchart of a testing method according to an embodiment of the present invention.

Fig. 6 is a sixth flowchart of a testing method according to an embodiment of the present invention.

Fig. 7 is a seventh flowchart of a testing method according to an embodiment of the present invention.

Fig. 8 is an eighth flowchart of a testing method according to an embodiment of the present invention.

Fig. 9 is a schematic block diagram of a test system according to an embodiment of the present invention.

Fig. 10 is a schematic structural diagram of an electronic device for implementing a test method according to an embodiment of the present invention.

Detailed Description

The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.

In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present specification, and it is possible for those of ordinary skill in the art to apply the present specification to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, like reference numerals in the figures refer to like structures or operations.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

It will be appreciated that "system," "apparatus," "unit" and/or "module" as used herein is one method for distinguishing between different components, elements, parts, portions or assemblies of different levels. However, if other words can achieve the same purpose, the words can be replaced by other expressions.

As used herein, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly indicates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.

The terms "having," "can have," "including," or "can include," as used herein, are intended to refer to the existence of a corresponding function, operation, element, etc. herein and are not intended to limit the existence of other one or more functions, operations, elements, etc. Furthermore, it should be understood that the terms "comprises" or "comprising," as used herein, are intended to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

The term "a or B", "at least one of a and/or B" or "one or more of a and/or B" as used herein includes any and all combinations of words listed therewith. For example, "a or B", "at least one of a and B" or "at least one of a or B" means (1) including at least one a, (2) including at least one B, or (3) including both at least one a and at least one B.

The definitions of the first and second, etc. herein are provided herein for the purpose of illustration and distinction of descriptive objects only, without order division, and without implying any particular limitation on the number of devices herein, and without any limitation herein. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

In the definition of connected herein, it will be understood that when an element (e.g., a first element) is "connected to" or "(operatively or communicatively) coupled to" another element (e.g., a second element), the element can be directly connected or coupled to the other element, and there can be intermediate elements (e.g., third elements) between the element and the other element. In contrast, it will be understood that when an element (e.g., a first element) is "directly connected to" or "directly coupled to" another element (e.g., a second element), there are no intervening elements (e.g., a third element) between the element and the other element.

Flowcharts are used herein to describe the operations performed by systems according to embodiments herein. It should be appreciated that the preceding or following operations are not necessarily performed in order precisely. Rather, the steps may be processed in reverse order or simultaneously. Also, other operations may be added to or removed from these processes.

For ease of understanding, the terms in the examples are explained first.

Dynamic voltage frequency scaling (Dynamic Voltageand Frequency Scaling, DVFS): the low-power consumption technology is used for setting the working voltage and the clock frequency according to the actual power consumption requirement of the chip during operation, so that the power provided by the chip can be ensured to meet the requirement and not to be excessive, and the power consumption can be reduced. The DVFS technology is a technology requiring combination of software and hardware, and in the software layer, data of the DVFS is derived from a data table of the highest frequency of normal operation of the chip corresponding to each test voltage under a plurality of test voltages. Of course, the DVFS is not only specific to one chip, but also can dynamically adjust voltage and frequency for actual power consumption when multiple chips are running.

Binning test, a chip performance test means, according to the relation of the frequency (running speed) and voltage of the test chip, classify the chip of mass production; and providing DVFS table (frequency/voltage relation table), binning test flow: 1. providing a test version by a software team; after the terminal is started, a binding tester uses an adb or an adb-based PC tool to modify the CPU frequency and voltage through a frequency or voltage node supported by a CPU freq drive; 3. and 4. Combining the last test result, the binding tester needs to modify other frequency/voltage values for multiple times to test the optimal performance frequency/voltage state. 5. And outputting DVFS table (frequency/voltage relation table, as shown in table 1) for the software system to integrate and support the DVFS function (the system dynamically adjusts the CPU frequency/voltage according to the conditions of CPU scene/load and the like) so that the system works in the optimal performance/power consumption state.

CPUFReq driver, the driving action: and providing a frequency and voltage setting API interface of the CPU for the Binning Service to call.

The chip performance test mode in the prior art is to combine the last test result, modify other frequency/voltage values for many times, test out the optimal performance frequency/voltage state, and manually obtain data from the test machine after the whole test is finished. The test mode can not realize automatic test, and has lower test efficiency. Based on this, as shown in fig. 1, the present embodiment provides a testing method, which includes:

S101, acquiring test data and current running state of a chip.

It should be noted that, after the test data of the chip may receive the test instruction from the host computer or the test platform, the test data may be written into or injected into the chip to perform a test, for example, in this embodiment, the test data may be input through an adb connection method, where the test data includes, but is not limited to, a test frequency, a test voltage, a maximum frequency, a minimum frequency, a maximum voltage, a minimum voltage, a frequency adjustment step size (step size), a voltage adjustment step size (step size), one or more of each set of test durations combine the test data, and the test data that is input from the adb writing node is then analyzed by using a binding Service. The manner of acquiring the test data of the chip is not limited in this embodiment.

It should be further noted that, for the current operation state of the chip, one or more operation states including, but not limited to, the frequency, voltage, load, and temperature of the chip may be obtained through a system interface. The manner of acquiring the operation state of the chip is not limited in this embodiment.

S102, testing the chip based on the test data and the test strategy corresponding to the running state to obtain a test result of the chip.

Typically, the chip is tested for a test time, which may be a longer time period or a shorter time period. For example, the test time may be 24 hours or 48 hours, or 30 minutes or 1 hour, which is not limited in this embodiment. And the test items when the chip is tested can be continuous execution of various functions in the tested equipment, and whether various abnormal phenomena such as restarting, error reporting, overload or overhigh temperature and the like which should not occur are detected when the tested chip executes the functions. Detecting whether a chip has a preset abnormal phenomenon or not in the test process, if the chip does not have the preset abnormal phenomenon in the test time, passing the test, determining that the test is not passed once the abnormal phenomenon is detected, ending the test, and entering the next step to reduce the unnecessary pressure test process.

According to the embodiment, on the basis of being capable of automatically testing the chip, the chip is further tested by combining the testing strategy corresponding to the running state of the current chip, so that the tested data can be attached to a real use scene, the testing time can be shortened, the testing efficiency can be improved, the testing labor cost can be saved, and the reliability of the testing result of the chip can be improved.

It should be noted that, the test method provided in this embodiment may be executed in an intelligent terminal (mobile phone, tablet, smart watch), a computer terminal, a network device, a chip module or a similar computing device, which is not limited in this embodiment.

It should be further noted that the chip of the present embodiment may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components, for example, the chip to be tested may be a central processing unit CPU, a microprocessor MCU, etc. The present embodiment does not limit the specific type of chip.

As an alternative implementation manner of the present embodiment, the test data of the present embodiment includes a preset voltage and a preset frequency, and in the present embodiment, the preset voltage and the preset frequency of the present embodiment are exemplified by the preset voltage being 750mV (millivolts) and the preset frequency being 1000MHz, which are not limited thereto.

Optionally, as shown in fig. 2, step S102 includes:

s102a1, judging whether the chip triggers restarting according to the running state, if yes, executing step S102a2, and if not, executing step S102a3.

S102a2, gradually increasing the voltage on the basis of the preset voltage by a preset first step size, and combining with the preset frequency to test the chip.

It should be noted that the preset first step length may be 2mV, 5mV, or 10mV, and those skilled in the art may set the first step length according to the test requirement, which is not limited in this embodiment.

S102a3, gradually reducing the voltage on the basis of the preset voltage by a preset first step size, and combining with the preset frequency to test the chip.

S102a4, determining a first critical voltage corresponding to the chip under a preset frequency.

In an alternative example, if it is determined that the chip is not triggered to restart according to the operation state within the test duration, the set of frequency/voltage (for example, 1000MHz/750 mV) combinations is considered to be able to satisfy the current chip operation, but is not necessarily the highest available voltage of the frequency at this time, after the test duration is over, the voltage corresponding to the frequency is lowered down, for example, by 5mV in a preset first step size of "stepv 5mV", corresponding to 745mV, and then the next set of (1000 MHz/745 mV) frequency tests are performed; correspondingly, if the chip is determined to trigger restarting according to the running state within the test duration, the combination of the frequency/voltage (for example, 1000MHz/750 mV) is considered to be incapable of meeting the current chip running, namely, the voltage is considered to be insufficient, the voltage corresponding to the frequency is increased upwards, for example, the voltage is increased by 5mV by a preset first step length of 'stepv 5 mV', corresponding to 755mV, and then the next group (1000 MHz/755 mV) of frequency tests are carried out; and the method is circulated until one group is tested to be failed, so that the next group of testing is automatically carried out by combining the last group of successful voltages before the last group of successful voltages, so as to obtain the critical voltage values, namely the first critical voltage, of the success and failure of the 1000MHz testing respectively.

As an alternative implementation of the present embodiment, the test data of the present embodiment includes a preset voltage and a preset frequency.

Optionally, as shown in fig. 3, step S102 further includes:

s102b1, judging whether the chip triggers restarting according to the running state, if yes, executing step S102b2, and if not, executing step S102b3.

S102b2, gradually reducing the frequency on the basis of the preset frequency by a preset second step length, and testing the chip by combining the frequency with the preset voltage.

It should be noted that, the preset second step length may be 10MHz, 15MHz, or 20MHz, and those skilled in the art may set the second step length according to the test requirement, which is not limited in this embodiment.

S102b3, gradually increasing the frequency on the basis of the preset frequency by a preset second step length, and testing the chip by combining the frequency with the preset voltage.

S102b4, determining a first critical frequency corresponding to the chip under a preset voltage.

In an alternative example, if it is determined that the chip is not triggered to restart according to the operation state within the test duration, the set of frequency/voltage (for example, 1000MHz/750 mV) combinations is considered to be capable of meeting the current chip operation, but is not necessarily the highest available frequency of the voltage at this time, after the test duration is over, the comment corresponding to the voltage is increased upwards, for example, 15MHz is increased by a preset second step length of "stepf 15MHz", 1015MHz is correspondingly increased, and then the next set of (1015 MHz/750 mV) frequency tests are performed; correspondingly, if the chip is determined to trigger restarting according to the running state within the test duration, the group of frequency/voltage (for example, 1000MHz/750 mV) combinations cannot be considered to meet the current chip running, namely, the frequency is considered to be too high, the comment corresponding to the voltage is lowered downwards, for example, 15MHz is reduced by a preset second step length of 'stepf 15 MHz', 985MHz is corresponding, and then the next group of frequency tests (985 MHz/750 mV) are carried out; and the method is circulated until one group is tested to be failed, so that the next group of tests is automatically carried out by combining the last group of successful frequencies before the last group of successful frequencies, so as to obtain the critical frequency values, namely the first critical frequency, of each success and failure of the 750mV test.

Therefore, the embodiment can test the chip by adopting different testing strategies according to the types of the testing data and the preset step length, and the diversity of the testing method is improved.

As an alternative implementation of this embodiment, as shown in fig. 4, step S102 includes:

s102c1, judging whether the temperature of the chip is smaller than a preset temperature threshold according to the running state; or judging whether the chip is not triggered to restart at the current temperature according to the running state, if so, executing the step S102c2, and if not, executing the step S102c3.

S102c2, gradually increasing the frequency on the basis of the preset frequency by a preset third step length, and testing the chip by combining the frequency with the preset voltage.

S102c3, gradually reducing the frequency on the basis of the preset frequency by a preset third step length, and testing the chip by combining with the preset voltage.

S102c4, determining a second critical frequency corresponding to the preset voltage of the chip.

Wherein the preset third step size is larger than the preset second step size.

In order to further achieve the purpose of shortening the test time, the temperature of the chip is determined to be smaller than the preset temperature threshold through the operation state, or the frequency is increased or decreased on the basis of the preset frequency by using the preset third step length when the chip is determined to be not triggered to restart at the current temperature, namely, the fact that the chip is tested by using the preset second step length which is originally relatively conservative under the condition that the chip operates normally is avoided, and the preset third step length is used for testing, so that the test time is greatly shortened, and the test efficiency is improved. It should be noted that the test steps in this embodiment are similar to those described above, and are not described here again.

As an alternative implementation of this embodiment, as shown in fig. 5, step S102 includes:

s102d1, determining whether the chip triggers restarting under the current load according to the running state, if yes, executing step S102d2, and if not, executing step S102d3.

It should be noted that, the current load is the load level during the test, for example, a case where the Chip (CPU) is loaded by more than 90% for the definition of the high load may be regarded as the high load, and the chip test is easier to trigger the restart.

S102d2, gradually reducing the frequency on the basis of the preset frequency by a preset fourth step length, and testing the chip by combining the frequency with the preset voltage.

S102d3, gradually increasing the frequency on the basis of the preset frequency by a preset fourth step length, and testing the chip by combining the frequency with the preset voltage.

S102d4, determining a third critical frequency corresponding to the preset voltage of the chip.

It should be noted that the test steps in this embodiment are similar to those described above, and are not described here again.

As another alternative implementation of this embodiment, as shown in fig. 6, step S102 includes:

s102e1, determining whether the chip triggers restarting under the current load according to the running state, if yes, executing step S102e2, and if not, executing step S102e3.

S102e2, gradually reducing the voltage on the basis of the preset voltage by a preset fifth step length, and combining with the preset frequency to test the chip.

S102e3, gradually increasing the voltage on the basis of the preset voltage by a preset fifth step length, and combining with the preset frequency to test the chip.

S102e4, determining a second critical voltage corresponding to the chip at a preset frequency.

According to the embodiment, the chip test is set in a state which is easy to trigger restarting, and the corresponding test strategy is matched with the current running state, so that the test time can be shortened.

As an alternative implementation of this embodiment, the test data includes a first voltage, a second voltage, and a preset frequency of the chip, where the first voltage is less than the second voltage.

As shown in fig. 7, step S102 includes:

s102f1, taking the intermediate value of the first voltage and the second voltage as the third voltage.

S102f2, testing the chip based on the combination of the third voltage and the preset frequency, judging whether the chip triggers restarting, if yes, executing the step S102f3, and if not, executing the step S102f4.

S102f3, continuing to perform dichotomy processing according to the second voltage and the third voltage, and testing until the chip is not triggered to restart.

S102f4, continuing to perform dichotomy processing according to the first voltage and the third voltage, and testing until the chip triggers restarting.

S102f5, determining a third critical voltage corresponding to the chip under a preset frequency.

In one example, the first voltage may be a minimum operating voltage of the chip, the second voltage may be a maximum operating voltage of the chip, the preset frequency is the highest operating frequency, the voltage is tested from the highest operating frequency, the intermediate value between the maximum operating voltage and the minimum operating voltage is adopted, if the test fails, that is, the chip triggers restarting, the second voltage and the third voltage continue to perform the dichotomy processing, and the test is performed until the chip does not trigger restarting, if the test succeeds, that is, the chip does not trigger restarting, the first voltage and the third voltage continue to perform the dichotomy processing, and the test is performed until the chip triggers restarting, and further, the corresponding third critical voltage of the chip under the preset frequency is quickly determined, and in this embodiment, the corresponding critical voltage under the preset frequency can be quickly determined by adopting the dichotomy mode, so as to shorten the test time.

Or after the test fails, the test result increases the voltage according to the voltage step, and the next group of tests are automatically carried out; if the test is successful, the voltage is reduced according to the voltage step, and the next group of tests is automatically performed. Until two adjacent voltage values at a certain step, one fails and the other succeeds, so that the critical value of the voltage corresponding to a certain frequency is found. And simultaneously, the test conditions of the voltages of each group of the frequency are saved.

As another alternative implementation of this embodiment, the test data includes a first frequency, a second frequency, and a preset voltage of the chip, where the first frequency is less than the second frequency.

As shown in fig. 8, step S102 includes:

s102g1, the intermediate value between the first frequency and the second frequency is set as the third frequency.

S102g2, testing the chip based on the combination of the third frequency and the preset voltage, judging whether the chip triggers restarting, if yes, executing the step S102g3, and if not, executing the step S102g4.

S102g3, continuing to perform dichotomy processing according to the first frequency and the third frequency, and testing until the chip is not triggered to restart.

S102g4, continuing to perform dichotomy processing according to the second frequency and the third frequency, and testing until the chip triggers restarting.

S102g5, determining a fourth critical frequency corresponding to the chip under a preset voltage.

The embodiment can rapidly determine the corresponding critical voltage under the preset voltage by adopting a dichotomy mode, thereby shortening the test time.

As an alternative implementation manner of the present embodiment, the test method of the present embodiment further includes:

s103, generating a frequency-voltage relation table according to the test result.

Optionally, the highest available voltage value corresponding to each frequency of the terminal is tested according to the test result, and then a corresponding DVFS table, that is, a frequency-voltage relationship table, is made, so that the frequency-voltage relationship table can be integrated into software or a chip.

S104, adjusting the working voltage and the working frequency of the chip based on the frequency-voltage relation table and a preset scene.

According to the embodiment, under the condition that the chip reaches the target performance, the chip can work by utilizing the lowest safe operation voltage according to a preset scene as much as possible, so that the dynamic power consumption is reduced, the standby time of the electronic equipment is prolonged, and the lowest power consumption is ensured on the premise that the performance reaches the standard.

The present embodiment also provides a test system corresponding to the test method described above. The following will describe each. Specifically, as shown in fig. 9, the test system of the present embodiment includes:

The acquisition module 1 acquires test data and current running state of the chip.

And the test module 2 tests the chip based on the test data and the test strategy corresponding to the running state so as to obtain a test result of the chip.

As an alternative implementation of this embodiment, the test data includes a preset voltage and a preset frequency, and in this embodiment, the preset voltage and the preset frequency of this embodiment are not limited to those of this embodiment, and are exemplified by a preset voltage of 750mV (millivolts) and a preset frequency of 1000 MHz.

And the test module 2 judges whether the chip triggers restarting according to the running state.

If yes, the voltage is gradually increased on the basis of the preset voltage by a preset first step length, and the chip is tested by combining with the preset frequency.

If not, gradually reducing the voltage on the basis of the preset voltage by a preset first step length, and combining with the preset frequency to test the chip.

And determining a first critical voltage corresponding to the chip under a preset frequency.

As an alternative implementation of this embodiment, the test data includes a preset voltage and a preset frequency.

If so, gradually reducing the frequency on the basis of the preset frequency by a preset second step length, and combining with the preset voltage to test the chip.

If not, the frequency is gradually increased on the basis of the preset frequency by the preset second step length, and the chip is tested by combining with the preset voltage.

And determining a first critical frequency corresponding to the chip under a preset voltage.

As an alternative implementation manner of this embodiment, the test module 2 determines, according to the operation state, whether the temperature of the chip is less than a preset temperature threshold. Or judging whether the chip is not triggered to restart at the current temperature according to the running state.

If yes, the frequency is gradually increased on the basis of the preset frequency by a preset third step length, and the chip is tested by combining with the preset voltage.

If not, gradually reducing the frequency on the basis of the preset frequency by a preset third step length, and combining with the preset voltage to test the chip.

And determining a second critical frequency corresponding to the preset voltage of the chip.

Wherein the preset third step size is larger than the preset second step size.

As an alternative implementation manner of this embodiment, the test module 2 determines, according to the running state, whether the chip triggers a restart under the current load.

It should be noted that, the current load is the proportion of the high load test in the test process, the proportion of the high load test in the current load of the chip is set higher, and the chip test is easier to trigger restarting at this time

If yes, gradually reducing the frequency on the basis of the preset frequency by a preset fourth step length, and testing the chip by combining the frequency with the preset voltage.

If not, the frequency is gradually increased on the basis of the preset frequency by the preset fourth step length, and the chip is tested by combining with the preset voltage.

And determining a third critical frequency corresponding to the preset voltage of the chip.

As another alternative implementation of this embodiment, the test module 2 determines, according to the running state, whether the chip triggers a restart under the current load.

If yes, gradually reducing the voltage on the basis of the preset voltage by a preset fifth step length, and testing the chip by combining the voltage with the preset frequency.

If not, the voltage is gradually increased on the basis of the preset voltage by a preset fifth step length, and the chip is tested by combining with the preset frequency.

And determining a second critical voltage corresponding to the preset frequency of the chip.

The test module 2 takes the intermediate value of the first voltage and the second voltage as the third voltage.

And testing the chip based on the combination of the third voltage and the preset frequency, and judging whether the chip triggers restarting or not.

If yes, continuing to perform dichotomy processing according to the second voltage and the third voltage, and testing until the chip is not triggered to restart.

If not, continuing to perform dichotomy processing according to the first voltage and the third voltage, and testing until the chip triggers restarting.

And determining a third critical voltage corresponding to the chip under the preset frequency.

The test module 2 takes the intermediate value of the first frequency and the second frequency as the third frequency.

And testing the chip based on the combination of the third frequency and the preset voltage, and judging whether the chip triggers restarting or not.

If yes, continuing to perform dichotomy processing according to the first frequency and the third frequency, and testing until the chip is not triggered to restart.

If not, continuing to perform dichotomy processing according to the second frequency and the third frequency, and testing until the chip triggers restarting.

As an alternative implementation of the present embodiment, the test system of the present embodiment further includes:

and the adjusting module 3 generates a frequency-voltage relation table according to the test result.

It should be noted that, the test system of this embodiment may be, for example: the individual chip, chip module or electronic device may also be a chip or chip module integrated in the electronic device. With respect to each of the apparatuses and each of the modules/units included in the products described in the above embodiments, it may be a software module/unit, a hardware module/unit, or a software module/unit, and a hardware module/unit. For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least some modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the remaining (if any) part of modules/units may be implemented in hardware such as a circuit. For each device and product applied to or integrated in the chip module, each module/unit contained in the device and product may be implemented in hardware such as a circuit, and different modules/units may be located in the same component (e.g. a chip, a circuit module, etc.) of the chip module or different components, or at least part of the modules/units may be implemented in software programs running on a processor integrated in the chip module, and the rest (if any) of the modules/units may be implemented in hardware such as a circuit. For each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented by using hardware such as a circuit, different modules/units may be located in the same component (for example, a chip, a circuit module, or the like) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program, where the software program runs on a processor integrated inside the terminal, and the remaining (if any) part of the modules/units may be implemented by using hardware such as a circuit.

The present embodiment also provides a chip, the chip including: a processor for executing computer program instructions stored in the memory, wherein the computer program instructions, when executed by the processor, trigger the chip to execute the computer program to implement the method in the above embodiments.

Fig. 10 is a schematic structural diagram of an electronic device according to the present embodiment. The electronic device comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the methods of the above embodiments when executing the program. The electronic device 30 shown in fig. 10 is merely an example, and should not be construed as limiting the functionality and scope of use of embodiments of the present invention.

As shown in fig. 10, the electronic device 30 may be embodied in the form of a general purpose computing device, which may be a server device, for example. Components of electronic device 30 may include, but are not limited to: the at least one processor 31, the at least one memory 32, a bus 33 connecting the different system components, including the memory 32 and the processor 31.

The bus 33 includes a data bus, an address bus, and a control bus.

Memory 32 may include volatile memory such as Random Access Memory (RAM) 321 and/or cache memory 322, and may further include Read Only Memory (ROM) 323.

Memory 32 may also include a program/utility 325 having a set (at least one) of program modules 324, such program modules 324 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

The processor 31 executes various functional applications and data processing, such as the method of the present invention as described above, by running a computer program stored in the memory 32.

The electronic device 30 may also communicate with one or more external devices 34 (e.g., keyboard, pointing device, etc.). Such communication may be through an input/output (I/O) interface 35. Also, model-generating device 30 may also communicate with one or more networks, such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet, via network adapter 36. As shown in fig. 10, network adapter 36 communicates with the other modules of model-generating device 30 via bus 33. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in connection with the model-generating device 30, including, but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, data backup storage systems, and the like.

It should be noted that although several units/modules or sub-units/modules of an electronic device are mentioned in the above detailed description, such a division is merely exemplary and not mandatory. Indeed, the features and functionality of two or more units/modules described above may be embodied in one unit/module in accordance with embodiments of the present invention. Conversely, the features and functions of one unit/module described above may be further divided into ones that are embodied by a plurality of units/modules.

The present embodiment also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs steps in a method as in the above embodiments.

Wherein the readable storage medium may employ more specifically may include, but is not limited to: portable disk, hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.

In a possible embodiment, the invention may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps of the method as described above when the program product is run on the terminal device.

Wherein the program code for carrying out the invention may be written in any combination of one or more programming languages, the program code may execute entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device, partly on a remote device or entirely on the remote device.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims

1. A method of testing, the method comprising:

acquiring test data and current running state of a chip;

2. The test method of claim 1, wherein the test data comprises a preset voltage and a preset frequency;

judging whether the chip triggers restarting according to the running state;

3. The test method according to claim 1 or 2, wherein the test data comprises a preset voltage and a preset frequency;

judging whether the chip triggers restarting according to the running state;

4. The testing method of claim 1, wherein the testing the chip based on the test data and the test policy corresponding to the operating state comprises:

5. The testing method of claim 1, wherein the testing the chip based on the test data and the test policy corresponding to the operating state comprises:

and/or the number of the groups of groups,

6. The test method of claim 1, wherein the test data comprises a first voltage, a second voltage, and a predetermined frequency of the chip, the first voltage being less than the second voltage;

and/or the number of the groups of groups,

7. The test method of any one of claims 1-6, wherein the test method further comprises:

generating a frequency-voltage relation table according to the test result;

8. A test system, the test system comprising:

9. A chip, the chip comprising:

a processor for executing computer program instructions stored in a memory, wherein the computer program instructions, when executed by the processor, trigger the chip to execute a computer program to implement the test method of any of claims 1-7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the test method of any of claims 1-7 when the computer program is executed.

11. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the test method according to any of claims 1-7.