CN116093163A - 一种屏蔽栅沟槽mosfet - Google Patents

一种屏蔽栅沟槽mosfet Download PDF

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CN116093163A
CN116093163A CN202310322007.4A CN202310322007A CN116093163A CN 116093163 A CN116093163 A CN 116093163A CN 202310322007 A CN202310322007 A CN 202310322007A CN 116093163 A CN116093163 A CN 116093163A
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王卓
胡鲲
乔明
张波
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University of Electronic Science and Technology of China
Guangdong Electronic Information Engineering Research Institute of UESTC
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Abstract

本发明提供一种屏蔽栅沟槽MOSFET，包括从下到上依次设置N型重掺杂衬底、N型轻掺杂外延漂移层、P型扩散区、N型重掺杂扩散区、在垂直方向构建深槽、浅槽，深槽内构建屏蔽栅多晶硅与控制栅多晶硅，分别用隔离场氧与栅氧与沟槽边缘隔离，浅槽内构建控制栅多晶硅，用栅氧与沟槽边缘隔离，器件构建金属电极隔离氧，贯穿隔离氧、N型轻掺杂扩散区、P型扩散区构建梯形金属电极、金属电极与P型扩散区之间形成P型高掺杂区、器件顶部形成源极、器件底部形成漏极。本发明充分利用浅槽的抗翘曲能力大于深槽的原理，将控制器件开关的浅槽与形成电荷平衡的深槽垂直分布，相对于深槽垂直深槽分布，提高器件整体的抗翘曲能力。

Description

一种屏蔽栅沟槽MOSFET
技术领域
本发明属于半导体功率器件技术领域，具体涉及一种屏蔽栅沟槽MOSFET。
背景技术
功率半导体器件广泛应用于DC-AC变换器、DC-DC变换器、智能功率模块等领域。槽MOSFET与传统VDMOS相比，具有比导通电阻低、耐压性能好、沟道密度高的特点，成为目前市场上分立功率器件的主力产品。但是沟槽MOSFET与VDMOS类似，同样受到硅极限的限制。超结VDMOS的出现打破了硅极限，但其生产工艺复杂、成本高，因此多用于高压器件，未能取代沟槽MOSFET在中低压器件领域的市场。屏蔽栅沟槽MOSFET作为一种超结的替代结构，相对于超结MOSFET具有生产工艺简单、成本低、频率特性好的特点，成为了低压领域高端功率器件的主流，甚至在多个领域取代常规沟槽MOSFET。
屏蔽栅沟槽MOSFET的特点是具有两类多晶硅栅极，分别为控制器件开关的控制栅与提供电荷平衡的屏蔽栅。器件关断状态下，在反向偏压的作用下，由于屏蔽栅作为场板，提供了横向电场，辅助反偏压形成的纵向电场将漂移区完全耗尽，耗尽区内的电场分布近似于均匀电场，因此其击穿电压基本依赖于漂移区厚度，而漂移区浓度可以取很高的值，有效降低器件电阻。
屏蔽栅沟槽MOSFET的电流能力依赖于其沟道密度，其前身沟槽MOSFET可以使用网格状的沟槽分布来使沟道密度提升近一倍。然而，由于屏蔽栅沟槽MOSFET的沟槽相对于常规沟槽MOSFET更宽、更深，器件在生产过程中有概率出现晶圆翘曲问题。晶圆翘曲会导致晶圆加工过程中中心与边缘加工尺寸出现偏差，使器件电性波动变大，产品良率降低。严重时，会造成晶圆无法继续后续加工甚至损坏设备。因此，如果提高屏蔽栅沟槽MOSFET的抗翘曲能力，那么就可以利用网格状沟槽来提高屏蔽栅沟槽MOSFET的电流能力。
发明内容
本发明要解决的问题是：屏蔽栅沟槽MOSFET是一种垂直型沟槽器件，一种降低器件导通电阻、提高电流能力的主要方式是通过网格型沟槽来增加沟道密度。但是在工厂生产过程中，深槽产生的应力会使晶圆发生翘曲，使用网格型沟槽更是会在晶圆的两个方向都产生明显翘曲，显著提高了生产风险、降低了同一晶圆上器件性能分布不均，也是造成晶圆外周器件良品率低下的一个主要原因。因此，在使用网格型沟槽设计的前提下，如何缓解晶圆翘曲成为决定能否量产生产的主要因素。
为实现上述目的，本发明的技术方案如下：
一种屏蔽栅沟槽MOSFET，包括：N型重掺杂衬底1、位于N型重掺杂衬底1上的漂移层2、漂移层2上部的P型扩散区3、位于P型扩散区3顶部的N型重掺杂扩散区4；位于N型重掺杂扩散区4上部的金属电极隔离氧11，贯穿金属电极隔离氧11与N型重掺杂扩散区4与P型扩散区3的楔形金属电极12、位于N型重掺杂扩散区4与P型扩散区3之间的P型重掺杂区13、位于器件顶部与楔形金属电极12接触的源极电极14、位于器件底部与N型重掺杂衬底1接触的漏极电极15；
任取两相邻台面连线为剖面线AA’，沿AA’截面方向，在漂移层2内部设有深槽5，深槽5的底部靠近漂移层2与N型重掺杂衬底1的交界处，深槽5内底部及侧壁设有隔离场氧7，隔离场氧7内部为屏蔽栅多晶硅8，深槽5上部屏蔽栅多晶硅8的两侧上方为控制栅多晶硅10，控制栅多晶硅10两侧的侧壁为栅氧化层9；
BB’截面与AA’截面之间的夹角为α，α取0度到180度之间任意值，沿BB’的截面方向，在漂移层2内部设有浅槽6，浅槽6的深度深于P型扩散区3与漂移层2交界处，浅槽6内设有控制栅多晶硅10，控制栅多晶硅10两侧的浅槽侧壁设有栅氧化层9。
作为优选方式，BB’截面与AA’截面垂直。
作为优选方式，浅槽6在BB’截面的宽度小于深槽5在AA’截面的宽度，浅槽6数量大于深槽5的数量。
作为优选方式，浅槽6内的控制栅多晶硅10在BB’截面的宽度与深槽5内的控制栅多晶硅10在AA’截面的宽度相同。
作为优选方式，在深槽5之间沿垂直AA’截面方向增加多个浅槽6。
作为优选方式，在相邻深槽之间设立三种不同角度的浅槽，与深槽分别成60度、90度、120度夹角，浅槽相互拼接形成六边形网格结构。
作为优选方式，所述器件结构中各掺杂类型相应变为相反的掺杂，即P型掺杂变为N型掺杂的同时，N型掺杂变为P型掺杂。
本发明的有益效果为：本发明通过将网格型屏蔽栅沟槽MOSFET的沟道分为用于电荷平衡的深沟槽与用于控制器件的浅沟槽，降低了器件在同样沟道密度下的沟槽应力，从而降低了高沟道密度屏蔽栅沟槽MOSFET生产过程中由沟槽应力产生的晶圆翘曲，提高了生产稳定性与同一晶圆上器件性能均匀度，能够有效稳定产品良率。
附图说明
图1为本发明的立体结构示意图。
图2为图1中AA’方向的截面示意图；
图3为图1中BB’方向的截面示意图；
图4为实施例1露出沟道结构的俯视图；
图5为实施例2露出沟道结构的俯视图；
图6为实施例3露出沟道结构的俯视图；
图7为实施例4露出沟道结构的俯视图；
图8为实施例5露出沟道结构的俯视图；
1为N型重掺杂衬底，2为漂移层，3为P型扩散区，4为N型重掺杂扩散区，5为深槽，6为浅槽，7为隔离场氧，8为屏蔽栅多晶硅，9为栅氧化层，10为控制栅多晶硅，11为金属电极隔离氧，12为楔形金属电极，13为P型重掺杂区，14源极电极，15为漏极电极。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
本发明通过将网络型沟槽SGT MOS的沟槽分为提供电荷耦合能力的深沟槽与提供导电沟道的浅沟槽，从而在提高器件沟道密度的同时，降低了器件生产过程中因沟槽产生的应力，进而减少晶圆翘曲、降低生产破片率、提高成品良率。
实施例1
如图1所示，本实施例提供一种屏蔽栅沟槽MOSFET，包括：N型重掺杂衬底1、位于N型重掺杂衬底1上的漂移层2、漂移层2上部的P型扩散区3、位于P型扩散区3顶部的N型重掺杂扩散区4；位于N型重掺杂扩散区4上部的金属电极隔离氧11，贯穿金属电极隔离氧11与N型重掺杂扩散区4与P型扩散区3的楔形金属电极12、位于N型重掺杂扩散区4与P型扩散区3之间的P型重掺杂区13、位于器件顶部与楔形金属电极12接触的源极电极14、位于器件底部与N型重掺杂衬底1接触的漏极电极15；
如图2、任取两相邻台面连线为剖面线AA’，沿AA’截面方向，在漂移层2内部设有深槽5，深槽5的底部靠近漂移层2与N型重掺杂衬底1的交界处，深槽5内底部及侧壁设有隔离场氧7，隔离场氧7内部为屏蔽栅多晶硅8，深槽5上部屏蔽栅多晶硅8的两侧上方为控制栅多晶硅10，控制栅多晶硅10两侧的侧壁为栅氧化层9；
如图3所示，BB’截面与AA’截面之间的夹角为α，α取0度到180度之间任意值，本实施例中BB’截面与AA’截面垂直。沿BB’的截面方向，在漂移层2内部设有浅槽6，浅槽6的深度深于P型扩散区3与漂移层2交界处，浅槽6内设有控制栅多晶硅10，控制栅多晶硅10两侧的浅槽侧壁设有栅氧化层9。
优选的，所述器件结构中各掺杂类型相应变为相反的掺杂，即P型掺杂变为N型掺杂的同时，N型掺杂变为P型掺杂。
本例的工作原理为：
在屏蔽栅沟槽型MOSFET的生产过程中，整个晶圆的应力可大致分解为沿沟槽方向与垂直沟槽方向。假设沟槽为平行Y方向，对于X方向上的应力，由于沟槽结构，沟槽底部、沟槽拐角、台面顶部的晶圆厚度、形貌存在差异，尤其是沟槽拐角，接触晶格不同材料时会产生更大应力，同时在受到应力时更容易发生形变，X方向上的应力影响较大；对于Y方向的应力，由于沿沟槽方向上的器件结构比较均匀，整个晶圆受到应力影响与晶圆衬底相似，同时由于沟槽造成的梯形台面结构，Y方向上的应力影响较弱。综合起来，单方向沟槽的SGT在生产过程中受到的应力影响主要来自垂直沟槽方向的沟槽拐角，因此造成整体晶圆在垂直沟槽方向的形变较大。
在网格型沟槽SGT的生产过程中，沟槽相互交叉会围绕台面柱产生多个应力薄弱点，使整体晶圆向各个方向发生较大的翘曲形变。对于屏蔽栅沟槽MOSFET，其控制栅底部深度只需超过P型扩散区深度，不必与屏蔽栅一样接近外延层底部。同时，只需要一个方向的屏蔽栅阵列就可以达成器件所需的电荷平衡。因此，本发明通过将传统网格型沟槽SGT某一方向的深沟槽改为浅沟槽，从而提高了晶圆在与其垂直方向上的抗翘曲能力，在生产过程中，可以将这样结构的器件在同一晶圆上按不同方向生产，从而提高所有方向的抗翘曲能力，减轻晶圆翘曲。
实施例2
如图5所示，本发明和实施例1基本相同，差别在于：浅槽6在BB’截面的宽度小于深槽5在AA’截面的宽度，浅槽6数量大于深槽5的数量，由于缩减了浅沟槽宽度，由浅沟槽造成的应力薄弱进一步减轻，同时浅沟槽数目的增强了器件的电流能力。
实施例3
如图6所示，本发明和实施例1基本相同，差别在于：浅槽6内的控制栅多晶硅10在BB’截面的宽度与深槽5内的控制栅多晶硅10在AA’截面的宽度相同。可在与实施例1效果相同的前提下提高深沟槽内控制栅与浅沟槽内控制栅的电性均匀度。
实施例4
如图7所示，本发明和实施例1基本相同，差别在于：在深槽5之间沿垂直AA’截面方向增加多个浅槽6。以牺牲较少抗翘曲能力换来器件电流能力的大量提升。
实施例5
如图8所示，本发明和实施例1基本相同，差别在于：在相邻深槽之间设立三种不同角度的浅槽，与深槽分别成60度、90度、120度夹角，浅槽相互拼接形成六边形网格结构。减少单一方向上的应力薄弱点，同时提高了沟道密度，提升了器件的电流能力。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

1.一种屏蔽栅沟槽MOSFET，其特征在于包括：N型重掺杂衬底(1)、位于N型重掺杂衬底(1)上的漂移层(2)、漂移层(2)上部的P型扩散区(3)、位于P型扩散区(3)顶部的N型重掺杂扩散区(4)；位于N型重掺杂扩散区(4)上部的金属电极隔离氧(11)，贯穿金属电极隔离氧(11)与N型重掺杂扩散区(4)与P型扩散区(3)的楔形金属电极(12)、位于N型重掺杂扩散区(4)与P型扩散区(3)之间的P型重掺杂区(13)、位于器件顶部与楔形金属电极(12)接触的源极电极(14)、位于器件底部与N型重掺杂衬底(1)接触的漏极电极(15)；
任取两相邻台面连线为剖面线AA’，沿AA’截面方向，在漂移层(2)内部设有深槽(5)，深槽(5)的底部靠近漂移层(2)与N型重掺杂衬底(1)的交界处，深槽(5)内底部及侧壁设有隔离场氧(7)，隔离场氧(7)内部为屏蔽栅多晶硅(8)，深槽(5)上部屏蔽栅多晶硅(8)的两侧上方为控制栅多晶硅(10)，控制栅多晶硅(10)两侧的侧壁为栅氧化层(9)；
BB’截面与AA’截面之间的夹角为α，α取0度到180度之间任意值，沿BB’的截面方向，在漂移层(2)内部设有浅槽(6)，浅槽(6)的深度深于P型扩散区(3)与漂移层(2)交界处，浅槽(6)内设有控制栅多晶硅(10)，控制栅多晶硅(10)两侧的浅槽侧壁设有栅氧化层(9)。
2.根据权利要求1所述的一种屏蔽栅沟槽MOSFET，其特征在于：BB’截面与AA’截面垂直。
3.根据权利要求1所述的一种屏蔽栅沟槽MOSFET，其特征在于：浅槽(6)在BB’截面的宽度小于深槽(5)在AA’截面的宽度，浅槽(6)数量大于深槽(5)的数量。
4.根据权利要求1所述的一种屏蔽栅沟槽MOSFET，其特征在于：浅槽(6)内的控制栅多晶硅(10)在BB’截面的宽度与深槽(5)内的控制栅多晶硅(10)在AA’截面的宽度相同。
5.根据权利要求1所述的一种屏蔽栅沟槽MOSFET，其特征在于：在深槽(5)之间沿垂直AA’截面方向增加多个浅槽(6)。
6.根据权利要求1所述的一种屏蔽栅沟槽MOSFET，其特征在于：在相邻深槽之间设立三种不同角度的浅槽，与深槽分别成60度、90度、120度夹角，浅槽相互拼接形成六边形网格结构。
7.根据权利要求1至6任意一项所述的一种屏蔽栅沟槽MOSFET，其特征在于：所述器件结构中各掺杂类型相应变为相反的掺杂，即P型掺杂变为N型掺杂的同时，N型掺杂变为P型掺杂。
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CN117976723A (zh) * 2024-04-02 2024-05-03 深圳市威兆半导体股份有限公司 一种屏蔽栅沟槽型mosfet器件及其制备方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117976723A (zh) * 2024-04-02 2024-05-03 深圳市威兆半导体股份有限公司 一种屏蔽栅沟槽型mosfet器件及其制备方法

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