CN116073769B - Two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions - Google Patents
Two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions Download PDFInfo
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- CN116073769B CN116073769B CN202310277318.3A CN202310277318A CN116073769B CN 116073769 B CN116073769 B CN 116073769B CN 202310277318 A CN202310277318 A CN 202310277318A CN 116073769 B CN116073769 B CN 116073769B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
- H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions, which comprises a direct current offset eliminating circuit and a slicing threshold adjusting circuit, wherein the input end of the slicing threshold adjusting circuit is used for being connected with the differential output end of an amplifying circuit output stage of a differential amplifier, the output end of the slicing threshold adjusting circuit is connected with the differential input end of the direct current offset eliminating circuit, and the differential output end of the direct current offset eliminating circuit is connected with the input end of an amplifying circuit input stage of the differential amplifier. The invention can realize the simultaneous use of the direct current offset cancellation circuit and the slice threshold adjustment circuit, not only can eliminate the offset of the calibration differential amplifier, but also can accurately set the slice threshold adjustment according to the application requirement.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions.
Background
Differential amplifiers are widely used in receivers of optical communication systems, and mainly include limiting amplifiers (Limiting Amplifier, LA), variable Gain Amplifiers (VGAs), transimpedance amplifiers (TIA), continuous-time linear equalization amplifiers (CTLE), and the like. The direct current imbalance of the differential amplifier can cause offset of signal crossing points amplified by the differential amplifier, and when the direct current imbalance is overlarge, the output amplitude of the differential amplifier can be clamped at the maximum value and cannot work normally; in order to eliminate the dc offset of the differential amplifier, the differential amplifier needs to be designed with an additional dc offset elimination (DC Offset Cancellation, DOC) circuit to eliminate the dc offset of the differential amplifier; on the other hand, if the input signal itself input to the differential amplifier is distorted by long distance transmission, the differential amplifier needs to compensate for the distortion of the input signal by a slice adjustment (Slice Level Adjust, SLA) circuit to improve the performance of the system.
In the conventional differential amplifier, as shown in fig. 1, a dc offset cancellation circuit and a slice threshold adjustment circuit are separately implemented, wherein the dc offset cancellation circuit adjusts the dc offset voltage of the differential amplifier to zero in a form of closed-loop negative feedback; the slice threshold adjusting circuit works in an open loop mode; when the slice threshold adjusting circuit works, the direct current offset eliminating circuit is closed, and the slice threshold adjusting circuit sets a fixed offset compensation voltage for the differential amplifier by adjusting the common mode voltage of the input stage of the amplifying circuit of the differential amplifier. The disadvantage of this solution is that: the slice threshold value adjusting circuit works in an open loop mode and only adjusts the offset compensation voltage of the input stage of the amplifying circuit of the differential amplifier, the inherent offset voltage generated by the mismatch of the differential channel device and the circuit of the amplifying circuit of the differential amplifier still exists between the amplifying stage and the output stage of the amplifying circuit, and the offset voltages among different chips are different due to the process deviation in the production process of the chips, so that a fixed offset compensation voltage value is not suitable for all chips, the consistency and the precision among different chips cannot be ensured, and the effect of the slice threshold value adjusting circuit is greatly reduced or the function is not practical at all. In addition, since the dc offset cancellation circuit generally operates in a closed-loop mode and the slice threshold adjustment circuit operates in an open-loop mode, the dc offset cancellation circuit and the slice threshold adjustment circuit cannot be used at the same time, and the performance of the differential amplifier cannot be effectively improved.
Based on the above-mentioned drawbacks, it is necessary to study a two-in-one cancellation circuit integrating the functions of cancellation of dc offset and adjustment of slice threshold, which can realize simultaneous use of the dc offset cancellation circuit and the adjustment of slice threshold, so that not only the offset of the differential amplifier itself can be eliminated, but also the adjustment of slice threshold can be set accurately according to the application requirements.
Disclosure of Invention
The invention aims to provide a two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions, which can realize the simultaneous use of the direct current offset eliminating circuit and the slicing threshold adjusting circuit, can eliminate the offset of a calibration differential amplifier, and can accurately set the slicing threshold according to application requirements.
In order to achieve the above object, the solution of the present invention is:
a two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions comprises a direct current offset eliminating circuit and a slicing threshold adjusting circuit; the first differential input end and the second differential input end of the slice threshold value adjusting circuit are respectively connected with the first differential output end and the second differential output end of the output stage of the amplifying circuit of the differential amplifier, and the first differential output end and the second differential output end of the slice threshold value adjusting circuit are respectively connected with the first differential input end and the second differential input end of the direct current offset eliminating circuit; the first differential output end and the second differential output end of the direct current offset cancellation circuit are respectively connected with the first differential input end and the second differential input end of the input stage of the amplifying circuit of the differential amplifier; the slice threshold adjusting circuit comprises an isolation resistor R11, an isolation resistor R12 and a variable current source It; the first end of the isolation resistor R11 is connected with the first differential input end of the slice threshold adjusting circuit, the second end of the isolation resistor R11 and the first current supply end of the variable current source It are connected with the first differential output end of the slice threshold adjusting circuit, the first end of the isolation resistor R12 is connected with the second differential input end of the slice threshold adjusting circuit, the second end of the isolation resistor R12 and the second current supply end of the variable current source It are connected with the second differential output end of the slice threshold adjusting circuit, and the variable current source It can adjust the current of the first current supply end and the current of the second current supply end.
The variable current source It comprises a bias current source Ib, a MOS tube M11, a MOS tube M12, a MOS tube M13, a MOS tube M14, a switch K1, a switch K2, a switch K3, a switch K4 and a switch K5; the input end of the bias current source Ib is connected with a control power supply, the output end of the bias current source Ib is connected with the grid electrode and the drain electrode of the MOS tube M11, the grid electrode of the MOS tube M12, the grid electrode of the MOS tube M13 and the grid electrode of the MOS tube M14, the drain electrode of the MOS tube M12, the drain electrode of the MOS tube M13 and the drain electrode of the MOS tube M14 are jointly connected with the first end of the switch K1 and the first end of the switch K2, the second end of the switch K1 and the second end of the switch K2 are respectively connected with the first current supply end and the second current supply end of the variable current source It, the source electrode of the MOS tube M11 is grounded, the source electrode of the MOS tube M12 is grounded through the switch K3, the source electrode of the MOS tube M13 is grounded through the switch K4, and the source electrode of the MOS tube M14 is grounded through the switch K5.
The output stage of the amplifying circuit comprises an output pipe M01, an output pipe M02, a load resistor R01, a load resistor R02 and a tail current source I0, wherein the grid electrode of the output pipe M01 and the grid electrode of the output pipe M02 are respectively connected with a second differential input end and a first differential input end of the output stage, the source electrode of the output pipe M01 and the source electrode of the output pipe M02 are commonly grounded through the tail current source I0, the drain electrode of the output pipe M01 and the first end of the load resistor R01 are connected with the first differential output end of the output stage, the drain electrode of the output pipe M02 and the first end of the load resistor R02 are connected with the second differential output end of the output stage, and the second end of the load resistor R01 and the second end of the load resistor R02 are connected with a control power supply; the first differential input end and the second differential input end of the output stage of the amplifying circuit are connected with the amplifying stage of the amplifying circuit.
The direct current offset cancellation circuit comprises an error amplifier EA, an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21 and an integrating capacitor C22; the first end of the integrating resistor R21 and the first end of the integrating resistor R22 are connected with the first differential input end and the second differential input end of the direct current offset cancellation circuit, the second end of the integrating resistor R21 is connected with the non-inverting input end of the error amplifier EA and the first end of the integrating capacitor C21, the second end of the integrating resistor R22 is connected with the inverting input end of the error amplifier EA and the first end of the integrating capacitor C22, the inverting output end of the error amplifier EA and the second end of the integrating capacitor C21 are connected with the first differential output end of the direct current offset cancellation circuit, and the non-inverting output end of the error amplifier EA and the second end of the integrating capacitor C22 are connected with the second differential output end of the direct current offset cancellation circuit.
After the scheme is adopted, the slice threshold adjusting circuit and the direct current offset eliminating circuit are jointly located in a closed-loop negative feedback loop, so that the slice threshold adjusting circuit and the direct current offset eliminating circuit can work simultaneously, offset of the differential amplifier can be eliminated, and slice threshold adjustment (namely offset compensation voltage adjustment) can be accurately set according to application requirements.
Drawings
FIG. 1 is a schematic circuit diagram of a conventional differential amplifier;
FIG. 2 is an overall schematic of the circuit of the present invention;
FIG. 3 is a schematic circuit diagram of a variable current source It of the present invention;
fig. 4 is a schematic circuit diagram of an output stage of the present invention.
Description of the embodiments
In order to further explain the technical scheme of the invention, the invention is explained in detail by specific examples.
As shown in fig. 2 to 4, the present invention discloses a two-in-one cancellation circuit integrating dc offset cancellation and slice threshold adjustment functions, which includes a dc offset cancellation circuit and a slice threshold adjustment circuit; the first differential input end and the second differential input end of the slice threshold value adjusting circuit are respectively connected with the first differential output end and the second differential output end of the output stage of the amplifying circuit of the differential amplifier, and the first differential output end and the second differential output end of the slice threshold value adjusting circuit are respectively connected with the first differential input end and the second differential input end of the direct current offset eliminating circuit; the first differential output end and the second differential output end of the direct current offset cancellation circuit are used for being respectively connected with the first differential input end and the second differential input end of the input stage of the amplifying circuit of the differential amplifier. In the invention, the slice threshold adjusting circuit and the direct current offset eliminating circuit are commonly positioned in a closed-loop negative feedback loop, so that the slice threshold adjusting circuit and the direct current offset eliminating circuit can work simultaneously; meanwhile, the slice threshold adjusting circuit works in a closed-loop negative feedback loop, so that the slice threshold adjusting circuit overcomes the process deviation in the chip production, and the slice threshold adjusting circuit has good consistency in adjusting different chips.
In the embodiment of the invention, the amplifying circuit specifically comprises an input stage, an amplifying stage and an output stage which are sequentially connected; the output stage comprises an output pipe M01, an output pipe M02, a load resistor R01, a load resistor R02 and a tail current source I0, wherein the grid electrode of the output pipe M01 and the grid electrode of the output pipe M02 are respectively connected with a second differential input end and a first differential input end of the output stage, the source electrode of the output pipe M01 and the source electrode of the output pipe M02 are commonly grounded through the tail current source I0, the drain electrode of the output pipe M01 and the first end of the load resistor R01 are connected with the first differential output end of the output stage, the drain electrode of the output pipe M02 and the first end of the load resistor R02 are connected with the second differential output end of the output stage, and the second end of the load resistor R01 and the second end of the load resistor R02 are connected with a control power supply; the first differential input end and the second differential input end of the output stage of the amplifying circuit are connected with the amplifying stage of the amplifying circuit, and the first differential input end and the second differential input end of the output stage are used for being respectively connected with differential alternating current amplified signals Vipo and Vino output by the amplifying stage.
In the embodiment of the invention, the dc offset cancellation circuit includes an error amplifier EA, an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21 and an integrating capacitor C22, where a first end of the integrating resistor R21 and a first end of the integrating resistor R22 are connected to a first differential input end and a second differential input end of the dc offset cancellation circuit, a second end of the integrating resistor R21 is connected to a non-inverting input end of the error amplifier EA and a first end of the integrating capacitor C21, a second end of the integrating resistor R22 is connected to an inverting input end of the error amplifier EA and a first end of the integrating capacitor C22, an inverting output end of the error amplifier EA and a second end of the integrating capacitor C21 are connected to a first differential output end of the dc offset cancellation circuit, and a non-inverting output end of the error amplifier EA and a second end of the integrating capacitor C22 are connected to a second differential output end of the dc offset cancellation circuit.
In the embodiment of the invention, the working principle of the direct current offset cancellation circuit is as follows: the first differential output end and the second differential output end of the amplifying circuit output stage of the differential amplifier respectively output differential alternating current output signals Vop and Von, the differential alternating current output signals Vop and Von contain direct current offset voltages of the differential amplifier, the differential alternating current output signals Vop and Von are sent to a direct current offset elimination circuit through a slicing threshold value adjusting circuit, an integrator is formed by an error amplifier EA, an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21 and an integrating capacitor C22 of the direct current offset elimination circuit, the differential alternating current output signals Vop and Von are subjected to low-pass filtering, and direct current offset voltages contained in the differential alternating current output signals Vop and Von are extracted, and are sent back to the first differential input end and the second differential input end of the amplifying circuit input stage of the differential amplifier after being amplified by the error amplifier EA, so that negative feedback adjustment is achieved, and the direct current offset voltages of the first differential output end and the second differential output end of the amplifying circuit output stage of the differential amplifier are forced to become zero.
In an embodiment of the present invention, the slice threshold adjusting circuit includes an isolation resistor R11, an isolation resistor R12, and a variable current source It; the first end of the isolation resistor R11 is connected with the first differential input end of the slice threshold adjusting circuit, the second end of the isolation resistor R11 and the first current supply end of the variable current source It are connected with the first differential output end of the slice threshold adjusting circuit, the first end of the isolation resistor R12 is connected with the second differential input end of the slice threshold adjusting circuit, the second end of the isolation resistor R12 and the second current supply end of the variable current source It are connected with the second differential output end of the slice threshold adjusting circuit, and the variable current source It can adjust the current of the first current supply end and the current of the second current supply end.
In an embodiment of the present invention, the working principle of the slice threshold adjustment circuit is as follows: on the basis of normal operation of the direct current offset cancellation circuit, if there is an offset between the differential input signals Vip and Vin input by the first differential input end and the second differential input end of the amplifying circuit input stage of the differential amplifier, the offset is equivalent to a distortion voltage existing between the first differential input end and the second differential input end of the amplifying circuit input stage of the differential amplifier, at this time, the differential amplifier is expected to provide an opposite offset compensation voltage to neutralize the distortion voltage, and at this time, the current of the first current supply end and the current of the second current supply end of the variable current source It can be adjusted to neutralize the distortion voltage. Specifically, when the current of the first current supply terminal and the current of the second current supply terminal of the variable current source It are not zero, the current of the first current supply terminal of the variable current source It flowsThrough the isolation resistor R11 and the load resistor R01, the current of the second current supply end of the variable current source It flows through the isolation resistor R12 and the load resistor R02, and at the moment, the voltage V between the first differential output end and the second differential output end of the slice threshold adjusting circuit sla =V slap -V slan =I 2 *（R 12 +R 02 ）-I 1 *(R 11 +R 01 ) Wherein V is slap And V slan A first differential output terminal voltage and a second differential output terminal voltage of the slice threshold adjusting circuit respectively, I 1 Is the current value of the first current supply end of the variable current source It, I 2 Is the current value of the second current supply end of the variable current source It, R 11 The resistance value of the resistor R11, R 12 The resistance value of the resistor R12, R 01 Is the resistance value of the resistor R01, R 02 A resistance value of the resistor R02; the voltage between the first differential output end and the second differential output end of the slice threshold adjusting circuit is input to the first differential input end and the second differential input end of the amplifying circuit input stage of the differential amplifier through the DC offset canceling circuit to force the voltage V between the first differential output end and the second differential output end of the amplifying circuit output stage out =V op -V on =I 2 *R 02 -I 1 *R 01 Then equivalent to offset compensation voltage V input to the input stage of the amplifying circuit of the differential amplifier inoffset =V out /A 0 =（I 2 *R 02 -I 1 *R 01 ）/A 0 Wherein A is 0 DC gain of amplifying circuit of differential amplifier, V op And V on A first differential output terminal voltage and a second differential output terminal voltage of an amplifying circuit output stage of the differential amplifier respectively. From the foregoing, it can be seen that only I is determined 2 、I 1 、R 02 、R 01 And A 0 Can obtain the determined offset compensation voltage V inoffset In general R 02 、R 01 And A 0 Is determined according to the design requirements of the differential amplifier, then I can be changed 2 、I 1 To accurately adjust V inoffse . When the direct current offset cancellation circuit works independently, I can be calculated by 2 、I 1 Adjusted to be equal.
In the embodiment of the invention, the variable current source It includes a bias current source Ib, a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a MOS transistor M14, a switch K1, a switch K2, a switch K3, a switch K4, and a switch K5; the input end of the bias current source Ib is connected with a control power supply, the output end of the bias current source Ib is connected with the grid electrode and the drain electrode of the MOS tube M11, the grid electrode of the MOS tube M12, the grid electrode of the MOS tube M13 and the grid electrode of the MOS tube M14, the drain electrode of the MOS tube M12, the drain electrode of the MOS tube M13 and the drain electrode of the MOS tube M14 are jointly connected with the first end of the switch K1 and the first end of the switch K2, the second end of the switch K1 and the second end of the switch K2 are respectively connected with the first current supply end and the second current supply end of the variable current source It, the source electrode of the MOS tube M11 is grounded, the source electrode of the MOS tube M12 is grounded through the switch K3, the source electrode of the MOS tube M13 is grounded through the switch K4, and the source electrode of the MOS tube M14 is grounded through the switch K5. The current magnitude of the first current supply end and the current magnitude of the second current supply end of the variable current source It can be adjusted by controlling the opening and closing of the switches K3-K5, and the final current magnitude of the first current supply end and the final current magnitude of the second current supply end of the variable current source It can be selected by the switch K1 and the switch K2; when the switch K1 and the switch K2 are turned on or turned off simultaneously, the current of the first current supply end and the current of the second current supply end of the variable current source It are equal; when one of the switch K1 and the switch K2 is turned on and the other is turned off, the distortion voltage is adjusted in the positive and negative directions respectively.
The above examples and drawings are not intended to limit the form or form of the present invention, and any suitable variations or modifications thereof by those skilled in the art should be construed as not departing from the scope of the present invention.
Claims (4)
1. The utility model provides an integrated direct current offset cancellation and two unification elimination circuits of section threshold value adjustment function which characterized in that: the device comprises a direct current offset eliminating circuit and a slice threshold adjusting circuit;
the first differential input end and the second differential input end of the slice threshold value adjusting circuit are respectively connected with the first differential output end and the second differential output end of the output stage of the amplifying circuit of the differential amplifier, and the first differential output end and the second differential output end of the slice threshold value adjusting circuit are respectively connected with the first differential input end and the second differential input end of the direct current offset eliminating circuit; the first differential output end and the second differential output end of the direct current offset cancellation circuit are respectively connected with the first differential input end and the second differential input end of the input stage of the amplifying circuit of the differential amplifier;
the slice threshold adjusting circuit comprises an isolation resistor R11, an isolation resistor R12 and a variable current source It; the first end of the isolation resistor R11 is connected with the first differential input end of the slice threshold adjusting circuit, the second end of the isolation resistor R11 and the first current supply end of the variable current source It are connected with the first differential output end of the slice threshold adjusting circuit, the first end of the isolation resistor R12 is connected with the second differential input end of the slice threshold adjusting circuit, the second end of the isolation resistor R12 and the second current supply end of the variable current source It are connected with the second differential output end of the slice threshold adjusting circuit, and the variable current source It can adjust the current of the first current supply end and the current of the second current supply end.
2. The two-in-one cancellation circuit integrating direct current offset cancellation and slice threshold adjustment functions as claimed in claim 1, wherein: the variable current source It comprises a bias current source Ib, a MOS tube M11, a MOS tube M12, a MOS tube M13, a MOS tube M14, a switch K1, a switch K2, a switch K3, a switch K4 and a switch K5;
the input end of the bias current source Ib is connected with a control power supply, the output end of the bias current source Ib is connected with the grid electrode and the drain electrode of the MOS tube M11, the grid electrode of the MOS tube M12, the grid electrode of the MOS tube M13 and the grid electrode of the MOS tube M14, the drain electrode of the MOS tube M12, the drain electrode of the MOS tube M13 and the drain electrode of the MOS tube M14 are jointly connected with the first end of the switch K1 and the first end of the switch K2, the second end of the switch K1 and the second end of the switch K2 are respectively connected with the first current supply end and the second current supply end of the variable current source It, the source electrode of the MOS tube M11 is grounded, the source electrode of the MOS tube M12 is grounded through the switch K3, the source electrode of the MOS tube M13 is grounded through the switch K4, and the source electrode of the MOS tube M14 is grounded through the switch K5.
3. The two-in-one cancellation circuit integrating direct current offset cancellation and slice threshold adjustment functions according to claim 1 or 2, characterized in that: the output stage of the amplifying circuit comprises an output pipe M01, an output pipe M02, a load resistor R01, a load resistor R02 and a tail current source I0, wherein the grid electrode of the output pipe M01 and the grid electrode of the output pipe M02 are respectively connected with a second differential input end and a first differential input end of the output stage, the source electrode of the output pipe M01 and the source electrode of the output pipe M02 are commonly grounded through the tail current source I0, the drain electrode of the output pipe M01 and the first end of the load resistor R01 are connected with the first differential output end of the output stage, the drain electrode of the output pipe M02 and the first end of the load resistor R02 are connected with the second differential output end of the output stage, and the second end of the load resistor R01 and the second end of the load resistor R02 are connected with a control power supply;
the first differential input end and the second differential input end of the output stage of the amplifying circuit are connected with the amplifying stage of the amplifying circuit.
4. The two-in-one cancellation circuit integrating direct current offset cancellation and slice threshold adjustment functions as claimed in claim 1, wherein: the direct current offset cancellation circuit comprises an error amplifier EA, an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21 and an integrating capacitor C22;
the first end of the integrating resistor R21 and the first end of the integrating resistor R22 are connected with the first differential input end and the second differential input end of the direct current offset cancellation circuit, the second end of the integrating resistor R21 is connected with the non-inverting input end of the error amplifier EA and the first end of the integrating capacitor C21, the second end of the integrating resistor R22 is connected with the inverting input end of the error amplifier EA and the first end of the integrating capacitor C22, the inverting output end of the error amplifier EA and the second end of the integrating capacitor C21 are connected with the first differential output end of the direct current offset cancellation circuit, and the non-inverting output end of the error amplifier EA and the second end of the integrating capacitor C22 are connected with the second differential output end of the direct current offset cancellation circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310277318.3A CN116073769B (en) | 2023-03-21 | 2023-03-21 | Two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310277318.3A CN116073769B (en) | 2023-03-21 | 2023-03-21 | Two-in-one eliminating circuit integrating direct current offset eliminating and slicing threshold adjusting functions |
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| CN116073769B true CN116073769B (en) | 2023-08-11 |
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| EP1458090A1 (en) * | 2003-03-10 | 2004-09-15 | Alcatel | Electronic integrated circuit comprising a differential amplifier with digital compensation of the DC offset voltage |
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| CN101226413A (en) * | 2008-01-22 | 2008-07-23 | 无锡硅动力微电子股份有限公司 | Reference circuit for restraining misadjusted CMOS energy gap |
| CN108092628A (en) * | 2017-12-12 | 2018-05-29 | 上海集成电路研发中心有限公司 | A kind of operational amplifier and amplifier circuit that there is imbalance to eliminate structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI384764B (en) * | 2010-12-03 | 2013-02-01 | Ind Tech Res Inst | Processing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1458090A1 (en) * | 2003-03-10 | 2004-09-15 | Alcatel | Electronic integrated circuit comprising a differential amplifier with digital compensation of the DC offset voltage |
| CN101217263A (en) * | 2008-01-17 | 2008-07-09 | 埃派克森微电子有限公司 | A compensatory method and device for DC offset voltage of amplifier |
| CN101226413A (en) * | 2008-01-22 | 2008-07-23 | 无锡硅动力微电子股份有限公司 | Reference circuit for restraining misadjusted CMOS energy gap |
| CN108092628A (en) * | 2017-12-12 | 2018-05-29 | 上海集成电路研发中心有限公司 | A kind of operational amplifier and amplifier circuit that there is imbalance to eliminate structure |
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| CN116073769A (en) | 2023-05-05 |
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