CN116057680A - 一种芯片封装结构、电子设备及芯片封装结构的制备方法 - Google Patents

一种芯片封装结构、电子设备及芯片封装结构的制备方法 Download PDF

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Publication number
CN116057680A
CN116057680A CN202080103465.3A CN202080103465A CN116057680A CN 116057680 A CN116057680 A CN 116057680A CN 202080103465 A CN202080103465 A CN 202080103465A CN 116057680 A CN116057680 A CN 116057680A
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China
Prior art keywords
chip
substrate
data processing
packaging
package
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Pending
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CN202080103465.3A
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English (en)
Inventor
张童龙
罗立德
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN116057680A publication Critical patent/CN116057680A/zh
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

本申请实施例提供一种芯片封装结构、电子设备及芯片封装结构的制备方法,涉及芯片封装技术领域。该芯片封装结构包括:封装基底、塑封层、至少一个光引擎、至少一个数据处理芯片;封装基底为重新布线层,光引擎包括光纤连接结构,以及构成有光子集成电路的光芯片,光芯片和数据处理芯片均集成在封装基底的同一表面上,并分别与封装基底电连接,且光芯片的出光面位于背离封装基底的一侧;塑封层位于封装基底的集成有光芯片和数据处理芯片的表面上,并包裹光芯片和数据处理芯片,塑封层具有贯通至出光面的通道,光纤连接结构穿过通道与出光面连接。

Description

PCT国内申请,说明书已公开。

Claims (18)

  1. PCT国内申请,权利要求书已公开。
CN202080103465.3A 2020-08-28 2020-08-28 一种芯片封装结构、电子设备及芯片封装结构的制备方法 Pending CN116057680A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/112294 WO2022041159A1 (zh) 2020-08-28 2020-08-28 一种芯片封装结构、电子设备及芯片封装结构的制备方法

Publications (1)

Publication Number Publication Date
CN116057680A true CN116057680A (zh) 2023-05-02

Family

ID=80352499

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080103465.3A Pending CN116057680A (zh) 2020-08-28 2020-08-28 一种芯片封装结构、电子设备及芯片封装结构的制备方法

Country Status (2)

Country Link
CN (1) CN116057680A (zh)
WO (1) WO2022041159A1 (zh)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL3168874T3 (pl) * 2015-11-11 2021-07-12 Lipac Co., Ltd. Obudowa chipów półprzewodnikowych z interfejsem optycznym
US20190121041A1 (en) * 2016-03-28 2019-04-25 Intel IP Corporation Optical fiber connection on package edge
US9807882B1 (en) * 2016-08-17 2017-10-31 Qualcomm Incorporated Density-optimized module-level inductor ground structure
US10141276B2 (en) * 2016-09-09 2018-11-27 Powertech Technology Inc. Semiconductor package structure and manufacturing method thereof
US10162139B1 (en) * 2017-07-27 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package
US11004803B2 (en) * 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US11002927B2 (en) * 2019-02-21 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure

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Publication number Publication date
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