CN116053134A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN116053134A CN116053134A CN202211651576.5A CN202211651576A CN116053134A CN 116053134 A CN116053134 A CN 116053134A CN 202211651576 A CN202211651576 A CN 202211651576A CN 116053134 A CN116053134 A CN 116053134A
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present disclosure provides a method of manufacturing a semiconductor device and a semiconductor device. The preparation method of the semiconductor device comprises the following steps: a first partial process including a process step of all process temperatures greater than or equal to 900 ℃ to form a trench on a first side of a semiconductor layer, a gate structure in the trench, a well region of a second conductivity type on the first side of the semiconductor layer, a source region of a first conductivity type formed in a surface of the well region, a depth of the trench being greater than a depth of the well region; a threshold voltage adjustment process including adjusting at least a doping concentration of a portion of a region for forming an inversion layer in the well region by an ion implantation process; and in the second part of treatment process, the whole process temperature is less than or equal to 600 ℃. The preparation method can realize fine regulation and control of threshold voltage and has slight influence on other parameters of the device.
Description
Technical Field
The disclosure belongs to the technical field of semiconductors, and particularly relates to a preparation method of a semiconductor device and the semiconductor device.
Background
This section is intended to provide a background or context for the embodiments recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
The IGBT (Insulated Gate Bipolar Transistor) has the advantages of high voltage resistance, easiness in driving and controlling, strong current capacity and the like, and is known as a CPU in an electric energy conversion system. The rated current level can reach thousands of amperes, and the method is widely applied to the fields of new energy automobiles, rail transit, power grids and the like.
The regulation of the threshold voltage of an IGBT often affects other parameters of the IGBT. How to realize accurate regulation and control of threshold voltage on the premise of not affecting other parameters as much as possible is always a difficulty in the IGBT design process.
Disclosure of Invention
The present disclosure provides a method of manufacturing a semiconductor device and a semiconductor device.
The technical scheme adopted by the present disclosure is as follows: a method of fabricating a semiconductor device, comprising:
a first partial process including a process step of all process temperatures of 900 ℃ or more to form a trench on a first face of a semiconductor layer, a gate structure in the trench, a well region of a second conductivity type formed inside the first face of the semiconductor layer, and a source region of a first conductivity type formed inside a surface of the well region;
a threshold voltage adjustment process including adjusting at least a doping concentration of a portion of a region for forming an inversion layer in the well region by an ion implantation process;
and in the second part of treatment process, the whole process temperature is less than or equal to 600 ℃.
In some embodiments, the gate structure includes a gate insulation layer and a gate, and the first portion of the processing includes: and forming a gate insulating layer in the trench, and forming a gate on the gate insulating layer, wherein the gate insulating layer contains silicon element.
In some embodiments, the first portion of the process includes: an interlayer insulating layer is formed to cover the gate structure and the source region, the interlayer insulating layer including a silicon element.
In some embodiments, the threshold voltage adjustment process uses or does not use a reticle.
In some embodiments, the second portion of the processing includes forming an interconnect structure.
In some embodiments, the first portion of the process further comprises: a carrier storage layer of a first conductivity type is formed under the bottom of the well region, wherein the carrier storage layer is separated from the source region by the well region.
In some embodiments, the semiconductor device includes: an IGBT.
The technical scheme adopted by the present disclosure is as follows: a semiconductor device prepared by the aforementioned preparation method.
After all high-temperature processes are finished, the section used for forming the inversion layer in the well region is doped by implantation, and the threshold voltage of the semiconductor device is directly and accurately regulated by adjusting the energy and the dosage of ion implantation. The method does not comprise a high-temperature process in the subsequent process steps, so that the influence on other parameters of the semiconductor device is small, the independence of the threshold voltage regulation is strong, and the adjustable range of the threshold voltage is large. From the viewpoint of process implementation, the preparation method provided by the embodiment of the disclosure has the advantages of few steps, simple working procedures and strong practicability, and does not introduce a plurality of thermal budget steps, so that the load of productivity is not increased.
Drawings
Fig. 1 is a schematic view of a product structure after the end of a first part of the processing procedure in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 2 is a process effect diagram after the threshold voltage adjustment process of the method for manufacturing a semiconductor device according to the embodiment of the present disclosure is completed.
Fig. 3 is a schematic view of a product structure at a stage in the process of the second part of the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.
Wherein the reference numerals are as follows: 1. a collector region; 2. a buffer layer; 3. a base region; 4. a carrier storage layer; 5. a well region; 51. an ion implantation layer; 6. a source region; 71. a gate insulating layer; 72. a gate; 8. an interlayer insulating layer; 91. a collector electrode; 92. an emitter.
Detailed Description
The disclosure is further described below with reference to the embodiments shown in the drawings.
Embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including the following processes.
The first part of the treatment process comprises the treatment steps that the total process temperature is greater than or equal to 900 ℃ so as to form a groove on the first surface of the semiconductor layer, a grid structure is formed in the groove, a well region of a second conductivity type is formed inside the first surface of the semiconductor layer, and a source region of a first conductivity type is formed inside the surface of the well region.
A threshold voltage adjustment process including adjusting at least a doping concentration of a portion of a region for forming an inversion layer in the well region by an ion implantation process;
and in the second part of treatment process, the whole process temperature is less than or equal to 600 ℃.
After all high-temperature processes are finished, the section used for forming the inversion layer in the well region is doped by implantation, and the threshold voltage of the semiconductor device is directly and accurately regulated by adjusting the energy and the dosage of ion implantation. The method does not comprise a high-temperature process in the subsequent process steps, so that the influence on other parameters of the semiconductor device is small, the independence of the threshold voltage regulation is strong, and the adjustable range of the threshold voltage is large. From the viewpoint of process implementation, the preparation method provided by the embodiment of the disclosure has the advantages of few steps, simple working procedures and strong practicability, and does not introduce a plurality of thermal budget steps, so that the load of productivity is not increased.
Fig. 1 is a schematic view of a product structure after the end of a first part of the processing procedure in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 2 is a process effect diagram after the threshold voltage adjustment process of the method for manufacturing a semiconductor device according to the embodiment of the present disclosure is completed. Fig. 3 is a schematic view of a product structure at a stage in the process of the second part of the manufacturing method of the semiconductor device according to the embodiment of the present disclosure.
A complete fabrication process of a semiconductor device (specifically, an IGBT) in an embodiment of the present disclosure is described with reference to fig. 1 to 3.
Referring to fig. 1, during a first part of the process, a collector region 1 of a second conductivity type, a buffer layer 2 of a first conductivity type, a base region 3 of a first conductivity type, a carrier storage layer 4 of a first conductivity type, a well region 5 of a second conductivity type, a source region 6 of a first conductivity type are formed. A gate insulating layer 71 and a gate electrode 72 are formed in the trench. The depth of the trench is greater than the depth of the well region 5. An interlayer insulating layer 8 is formed to cover the source region 6, the gate electrode 72, and the gate insulating layer 71.
The first conductivity type is N-type and the second conductivity type is P-type. Or the first conductivity type is P-type and the second conductivity type is N-type.
The source region 6 is located inside the first face of the semiconductor layer and the collector region 1 is located inside the second face of the semiconductor layer. The first face and the second face of the semiconductor layer are two faces opposite to each other.
The material of the gate insulating layer 71 is, for example, an insulating material containing a silicon element such as an oxide of silicon or an oxynitride of silicon.
The material of the interlayer insulating layer 8 is, for example, an insulating material containing a silicon element such as an oxide of silicon or oxynitride of silicon.
The process temperature for forming the silicon-containing insulating material layer is typically above 900 c and typical process temperatures are above 1000 c.
Referring to fig. 2, the threshold voltage adjustment process does not use a reticle. The ion implantation layer 51 is formed by implanting boron ions under the entire first face of the semiconductor device through an ion implantation process. The newly implanted ions may be either P-type or N-type. The implantation depth is controlled in the region below the source region 6 and above the bottom of the well region 5. The region of well region 5 below source region 6, above the bottom of well region 5, and adjacent to gate 72 structure is used to form an inversion layer. The doping concentration of this section has a greater influence on the threshold voltage of the IGBT. The effect on the performance of the IGBT device is negligible for other regions of the well region 5 and for slight variations in the ion concentration in the gate 72.
Of course, the semiconductor device may be a trench gate MOSFET.
In other embodiments, photolithography, etching processes may be used to selectively adjust only the ion concentration of well region 5 below source region 6.
Referring to fig. 3, a second portion of the process includes forming an interconnect structure. Specifically, the collector 91 is formed on the surface of the collector region 1 on the side away from the buffer layer 2. The material of well region 5 between adjacent source regions 6 is selectively etched to expose the surface of source regions 6 on the side remote from the trenches. An emitter 92 is formed covering the interlayer insulating layer 8 and in electrical contact with the side surface of the source region 6.
The technical scheme adopted by the present disclosure is as follows: a semiconductor device prepared by the aforementioned preparation method.
It should be noted that, the process details in the first part of the processing procedure and the second part of the processing procedure are the execution sequence, the mask pattern, the process condition, and the like, and are not particularly limited in this disclosure. Those skilled in the art can devise the invention according to the prior art.
The various embodiments in this disclosure are described in a progressive manner, and identical and similar parts of the various embodiments are all referred to each other, and each embodiment is mainly described as different from other embodiments.
The scope of the present disclosure is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present disclosure by those skilled in the art without departing from the scope and spirit of the disclosure. Such modifications and variations are intended to be included herein within the scope of the following claims and their equivalents.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
a first partial process including a process step of all process temperatures of 900 ℃ or more to form a trench on a first face of a semiconductor layer, a gate structure in the trench, a well region of a second conductivity type formed inside the first face of the semiconductor layer, and a source region of a first conductivity type formed inside a surface of the well region;
a threshold voltage adjustment process including adjusting at least a doping concentration of a portion of a region for forming an inversion layer in the well region by an ion implantation process;
and in the second part of treatment process, the whole process temperature is less than or equal to 600 ℃.
2. The method of manufacturing of claim 1, wherein the gate structure comprises a gate insulation layer and a gate electrode, the first portion of the process comprising: and forming a gate insulating layer in the trench, and forming a gate on the gate insulating layer, wherein the gate insulating layer contains silicon element.
3. The method of claim 1, wherein the first portion of the process comprises: an interlayer insulating layer is formed to cover the gate structure and the source region, the interlayer insulating layer including a silicon element.
4. The method of claim 1, wherein the threshold voltage adjustment process is with or without a reticle.
5. The method of manufacturing of claim 1, wherein the second portion of the process includes forming an interconnect structure.
6. The method of manufacturing according to claim 1, wherein the first part of the process further comprises: a carrier storage layer of a first conductivity type is formed under the bottom of the well region, wherein the carrier storage layer is separated from the source region by the well region.
7. The method of manufacturing according to claim 1, wherein the semiconductor device comprises: an IGBT.
8. A semiconductor device produced by the production method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211651576.5A CN116053134A (en) | 2022-12-21 | 2022-12-21 | Method for manufacturing semiconductor device and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211651576.5A CN116053134A (en) | 2022-12-21 | 2022-12-21 | Method for manufacturing semiconductor device and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116053134A true CN116053134A (en) | 2023-05-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211651576.5A Pending CN116053134A (en) | 2022-12-21 | 2022-12-21 | Method for manufacturing semiconductor device and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116053134A (en) |
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2022
- 2022-12-21 CN CN202211651576.5A patent/CN116053134A/en active Pending
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