CN116052596A

CN116052596A - Display panel, driving method thereof and display device

Info

Publication number: CN116052596A
Application number: CN202310179066.0A
Authority: CN
Inventors: 张蒙蒙
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-02-23
Filing date: 2023-02-23
Publication date: 2023-05-02

Abstract

The embodiment of the application provides a display panel, a driving method thereof and a display device, wherein the display panel comprises a plurality of rows of pixel circuits, and each pixel circuit comprises a driving transistor, a data writing module and a threshold grabbing module; the control end of the threshold grabbing module in the ith row of pixel circuits is electrically connected with the control end of the threshold grabbing module in the (i+1) th row of pixel circuits, and i is more than or equal to 1; the pixel circuit includes a first bias adjustment stage and a data writing stage that are performed sequentially. A first bias adjustment stage in which the data writing module transmits a first adjustment voltage to the driving transistor; in the data writing stage, the data writing module transmits data voltage to the driving transistor, and the threshold grabbing module is started, wherein the time length between the closing time of the data writing module and the closing time of the threshold grabbing module is a first time length; in the i-th row pixel circuit and the i+1-th row pixel circuit, the first bias adjustment stage of the pixel circuit having the larger first time length is turned on earlier. The display panel can improve the problem of bright and dark lines of the display panel.

Description

Display panel, driving method thereof and display device

[ field of technology ]

The present disclosure relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

[ background Art ]

An organic light-emitting diode (OLED) display panel has advantages of low power consumption, self-luminescence, wide viewing angle, wide temperature characteristics, fast response speed, and the like, and has wide application in the market. In the display panel, a pixel circuit is used to drive a light emitting element to emit light, and a shift register circuit provided at the periphery is generally used to supply a driving signal to the pixel circuit.

In the prior art, in order to reduce the frame of the display panel, a shift register circuit is usually designed to drive two rows of pixel circuits, but this results in different brightness of the light emitting elements driven by the two rows of pixel circuits, which affects the display quality of the display panel.

[ MEANS FOR SOLVING PROBLEMS ]

In view of the foregoing, embodiments of the present application provide a display panel, a driving method thereof, and a display device to solve the foregoing problems.

In a first aspect, an embodiment of the present application provides a driving method of a display panel, where the display panel includes a plurality of rows of pixel circuits, and the pixel circuits include a driving transistor, a data writing module, and a threshold grabbing module; the driving transistor is used for generating luminous driving current, the input end of the data writing module is electrically connected with the first signal line, the output end of the data writing module is electrically connected with the first pole of the driving transistor, the input end of the threshold grabbing module is electrically connected with the second pole of the driving transistor, and the output end of the threshold grabbing module is electrically connected with the grid electrode of the driving transistor; the control end of the threshold grabbing module in the ith row of pixel circuits is electrically connected with the control end of the threshold grabbing module in the (i+1) th row of pixel circuits, and i is more than or equal to 1;

One duty cycle of the pixel circuit includes a first bias adjustment phase and a data writing phase performed after the first bias adjustment phase; the driving method comprises the following steps:

in a first bias adjustment stage, the data writing module is started, and a first signal line transmits a first adjustment voltage to the data writing module;

in the data writing stage, a data writing module and a threshold grabbing module are started, a first signal line transmits data voltage to the data writing module, and the time between the closing time of the data writing module and the closing time of the threshold grabbing module is a first time;

in the ith row of pixel circuits and the (i+1) th row of pixel circuits, the first bias adjustment stage of the first long row of pixel circuits is started earlier than the first bias adjustment stage of the first long row of pixel circuits.

In an implementation manner of the first aspect, the pixel circuit further includes a first reset module, an input end of the first reset module is electrically connected to the first reset signal line, and an output end of the first reset module is electrically connected to a gate of the driving transistor; the control end of the first reset module in the ith row of pixel circuits is electrically connected with the control end of the first reset module in the (i+1) th row of pixel circuits; one working cycle of the pixel circuit further comprises a reset phase, wherein the reset phase is performed before the data writing phase;

The driving method further includes: in the reset phase, the first reset module is turned on.

In one implementation of the first aspect, the first bias adjustment phase is performed before the reset phase.

In one implementation of the first aspect, the first bias adjustment phase at least partially overlaps the reset phase.

In one implementation manner of the first aspect, the data writing module includes a first sub-data writing module and a second sub-data writing module, the first signal line includes a first sub-signal line and a second sub-signal line, an input end of the first sub-data writing module is electrically connected with the first sub-signal line, and an output end of the first sub-data writing module is electrically connected with a first pole of the driving transistor; the input end of the second sub data writing module is electrically connected with the second sub signal line, and the output end of the second sub data writing module is electrically connected with the first electrode of the driving transistor;

in a first bias adjustment phase, the data writing module is turned on, and the first signal line transmits a first adjustment voltage to the data writing module, including: in the first bias adjustment stage, a first sub-data writing module is started, a second sub-data writing module is closed, and a first sub-signal line transmits a first adjustment voltage to the first sub-data writing module;

in the data writing stage, the data writing module and the threshold grabbing module are started, the first signal line transmits data voltage to the data writing module, and the data writing module comprises: in the data writing stage, the second sub-data writing module and the threshold grabbing module are started, the first sub-data writing module is closed, and the second sub-signal line transmits data voltage to the second sub-data writing module.

In an implementation manner of the first aspect, in the data writing stage, a duration between a time when the second sub data writing module is turned off and a time when the threshold grabbing module is turned off is a first duration;

in the ith row of pixel circuits and the (i+1) th row of pixel circuits, the first sub-data writing module of the first long row of pixel circuits is turned on earlier than the first sub-data writing module of the first short row of pixel circuits.

In an implementation manner of the first aspect, a control end of the first sub data writing module is electrically connected to the first scan line, and a control end of the second sub data writing module is electrically connected to the second scan line; the pixel circuits of different rows are respectively electrically connected with different second scanning lines, the pixel circuits of the j row and the pixel circuits of the j+1th row are electrically connected with the same first scanning line, the control end of the threshold grabbing module in the pixel circuit of the j row is electrically insulated from the control end of the threshold grabbing module in the pixel circuit of the j+1th row, j is more than or equal to 2, and j is not equal to i.

In an implementation manner of the first aspect, in a working cycle of the pixel circuit, a duration between a time when the first sub data writing module is turned off and a time when the threshold grabbing module is turned on is a second duration; in the j-th row pixel circuit and the j+1-th row pixel circuit, a second time period in the first-time-long row pixel circuit is longer than a second time period in the first-time-short row pixel circuit.

In an implementation manner of the first aspect, the pixel circuit further includes a second reset module, an input end of the second reset module is electrically connected to the second reset signal line, an output end of the second reset module is electrically connected to the first electrode of the light emitting element, and a control end of the second reset module is electrically connected to the first scan line; the signal transmitted by the first scanning line controls the switch states of the second reset module and the first sub-data writing module to be the same.

In an implementation manner of the first aspect, a control end of the threshold value grabbing module is electrically connected with the third scanning line, and a control end of the first reset module is electrically connected with the fourth scanning line; the threshold grabbing module comprises a threshold grabbing transistor, wherein a first pole of the threshold grabbing transistor is electrically connected with a second pole of the driving transistor, the second pole is electrically connected with a grid electrode of the driving transistor, and the grid electrode is electrically connected with a third scanning line; the first reset module comprises a first reset transistor, a first pole of the first reset transistor is electrically connected with the first reset signal line, a second pole of the first reset transistor is electrically connected with a grid electrode of the driving transistor, and the grid electrode of the first reset transistor is electrically connected with the fourth scanning line;

in one implementation of the first aspect, the first reset transistor and the threshold grabbing transistor each include a metal oxide active layer.

In a second aspect, embodiments of the present application provide a display panel driven using the driving method as provided in the first aspect.

In a third aspect, embodiments of the present application provide a display device including a display panel as provided in the second aspect.

In this embodiment, a control end of the threshold value grabbing module in the ith row of pixel circuits is electrically connected with a control end of the threshold value grabbing module in the ith+1th row of pixel circuits, and in the ith row of pixel circuits and the ith+1th row of pixel circuits, a time for starting a first bias adjustment stage in the first long row of pixel circuits is earlier than a time for starting a first bias adjustment stage in the first short row of pixel circuits, so that a negative bias time of a driving transistor in the first long row of pixel circuits is longer, and a degree of negative bias of the driving transistor in the first long row of pixel circuits is higher. Because the speed of the charge transmission of the driving transistor with larger negative bias voltage degree is smaller, the same grid potential of the driving transistor in the first long row of pixel circuits and the grid potential of the driving transistor in the first long row of pixel circuits become possible, thereby being beneficial to reducing the brightness difference of the light-emitting elements respectively driven by the ith row of pixel circuits and the (i+1) th row of pixel circuits, improving the bright and dark line problem of the display panel and further improving the display quality of the display panel.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;

FIG. 2 is a schematic diagram of the pixel circuit of FIG. 1;

FIG. 3 is a schematic diagram of the pixel circuit shown in FIG. 2;

FIG. 4 is a timing diagram of the pixel circuit shown in FIG. 3;

FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 3;

FIG. 6 is a timing diagram of the pixel circuit shown in FIG. 3;

FIG. 7 is a schematic diagram of yet another pixel circuit provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of the pixel circuit shown in FIG. 7;

FIG. 9 is a timing diagram of the pixel circuit shown in FIG. 8;

fig. 10 is a schematic connection diagram of three adjacent rows of pixel circuits according to an embodiment of the present disclosure;

FIG. 11 is a timing diagram of the pixel circuit shown in FIG. 10;

FIG. 12 is a schematic view of a display panel according to another embodiment of the present disclosure;

Fig. 13 is a schematic diagram of a display device according to an embodiment of the present application.

[ detailed description ] of the invention

For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and examples herein refer to values that are generally agreed upon, rather than exact, within reasonable process operating ranges or tolerances.

It should be understood that although the terms first, second, etc. may be used in embodiments of the present application to describe sub-signal lines, sub-data writing modules, scan lines, etc., these sub-signal lines, sub-data writing modules, scan lines, etc. should not be limited to these terms. These terms are only used to distinguish sub-signal lines, sub-data writing modules, scan lines, etc. from one another. For example, a first scan line may also be referred to as a second scan line, and similarly, a second scan line may also be referred to as a first scan line, without departing from the scope of embodiments of the present application.

The applicant has provided a solution to the problems existing in the prior art by intensive studies.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application, fig. 2 is a schematic diagram of the pixel circuit in fig. 1, fig. 3 is a schematic diagram of the pixel circuit in fig. 2, and fig. 4 is a timing diagram of the pixel circuit in fig. 3.

The embodiment of the application provides a driving method of a display panel 01, and the structure of the display panel 01 is shown in fig. 1, and the display panel comprises a plurality of rows of pixel circuits 10 and a plurality of light emitting elements 20, wherein the pixel circuits 10 are used for providing light emitting driving currents for the light emitting elements 20. The display panel 01 further includes a plurality of first signal lines DL1 arranged along the row direction X, the first signal lines DL1 extending along the column direction Y, and at least a portion of the pixel circuits 10 arranged along the column direction Y are electrically connected to the same first signal line DL 1.

As shown in fig. 2 and 3, the pixel circuit 10 includes a driving transistor Md, a data writing module 101, and a threshold grabbing module 102; the driving transistor Md is used for generating a light-emitting driving current, the input terminal 1011 of the data writing module 101 is electrically connected with the first signal line DL1, and the output terminal 1012 is electrically connected with the first pole of the driving transistor Md; the input 1021 of the threshold grabbing module 102 is electrically connected to the second pole of the driving transistor Md, and the output 1022 is electrically connected to the gate of the driving transistor Md. The first pole of the driving transistor Md may be a source thereof and the second pole may be a drain thereof.

The control end 1023 of the threshold value grabbing module 102 in the ith row of pixel circuits 10 is electrically connected with the control end 1023 of the threshold value grabbing module 102 in the (i+1) th row of pixel circuits 10, and i is more than or equal to 1.

As shown in connection with fig. 4, one duty cycle Z of the pixel circuit 10 includes a first bias adjustment stage E1 and a data writing stage E2 performed after the first bias adjustment stage E1.

The driving method of the display panel comprises the following steps:

step B1: in the first bias adjustment stage E1, the data writing module 101 is turned on, and the first signal line DL1 transmits the first adjustment voltage V1 to the data writing module 101.

Step B2: in the data writing phase E2, the data writing module 101 and the threshold grabbing module 102 are turned on, the first signal line DL1 transmits the data voltage Vdata to the data writing module 101, and the duration between the time when the data writing module 101 is turned off and the time when the threshold grabbing module 102 is turned off is the first duration G1.

It is understood that the first duration G1 refers to: in the same pixel circuit 10, in the data writing stage E2, the period between the time when the data writing module 101 is turned on and the time when the threshold grabbing module 102 is turned off is long.

In step B1, the first regulated voltage V1 may be transmitted to the first pole of the driving transistor Md through the turned-on data writing module 101. In step B2, since the driving transistor Md is turned on in the data writing stage E1, the data voltage Vdata can be transmitted to the gate of the driving transistor Md through the turned-on data writing module 101, the driving transistor Md, and the threshold grabbing module 102.

Alternatively, as shown in fig. 3 and 4, the control terminal 1011 of the data writing module 101 is electrically connected to the first control line SK1, the data writing module 101 includes a data writing transistor M1, a first pole of the data writing transistor M1 is electrically connected to the first signal line DL1, a second pole is electrically connected to a first pole of the driving transistor Md, and a gate is electrically connected to the first control line SK 1. The threshold grabbing module 102 includes a threshold grabbing transistor M2, where a first pole of the threshold grabbing transistor M2 is electrically connected to a second pole of the driving transistor Md, the second pole is electrically connected to a gate of the driving transistor Md, and the gate is electrically connected to the second control line SK 2.

In the first bias adjustment stage E1, the first control line SK1 transmits an active signal (e.g., a low level signal) to control the data writing transistor M1 to be turned on, and the first adjustment voltage V1 transmitted by the first signal line DL1 is transmitted to the first pole of the driving transistor Md through the turned-on data writing transistor M1.

In the data writing stage E2, the first control line SK1 transmits an active signal (e.g., a low level signal) to control the data writing transistor M1 to be turned on, the second control line SK2 transmits an active signal (e.g., a high level signal) to control the threshold grabbing transistor M2 to be turned on, and the data voltage Vdata transmitted by the first signal line DL1 is transmitted to the gate of the driving transistor Md through the turned-on data writing transistor M1, the driving transistor Md, and the threshold grabbing transistor M2.

Among the ith row of pixel circuits 10 and the (i+1) th row of pixel circuits 10, the first bias adjustment stage E1 of the one row of pixel circuits 10 having the first length of time G1 is turned on earlier than the first bias adjustment stage E1 of the one row of pixel circuits 10 having the first length of time G1 is turned on.

That is, in the i-th row pixel circuit 10 and the i+1th row pixel circuit 10, in the row pixel circuit 10 in which the first period G1 is large, the first adjustment voltage V1 biases the drive transistor Md to a greater extent; in the pixel circuits 10 of one row having the first time length G1 smaller, the first adjustment voltage V1 makes the driving transistor Md bias to a smaller extent.

For example, as shown in fig. 3 and 4, the control terminal 1023 of the threshold grabbing module 102 in the i-th row of pixel circuits 10 is electrically connected to the control terminal 1023 of the threshold grabbing module 102 in the i+1-th row of pixel circuits 10, i.e., the control terminal 1023 of the threshold grabbing module 102 in the i-th row of pixel circuits 10 is electrically connected to the same second control line SK2 (i) as the control terminal 1023 of the threshold grabbing module 102 in the i+1-th row of pixel circuits 10. The control terminal 1011 of the data writing module 101 in the ith row of pixel circuits 10 is electrically connected to the first control line SK1 (i) of the ith row, and the control terminal 1011 of the data writing module 101 in the (i+1) th row of pixel circuits 10 is electrically connected to the first control line SK1 (i+1) of the (i+1) th row, i.e., the control terminal 1011 of the data writing module 101 in the (i) th row of pixel circuits 10 and the control terminal 1011 of the data writing module 101 in the (i+1) th row of pixel circuits 10 are electrically connected to different first control lines SK1, respectively.

The first period G1 in the i-th row of pixel circuits 10 is longer than the first period G1 in the i+1-th row of pixel circuits 10, and the time at which the first bias adjustment stage E1 of the i-th row of pixel circuits 10 is turned on is earlier than the time at which the first bias adjustment stage E1 of the i+1-th row of pixel circuits 10 is turned on.

It is understood that the first control line SK1 and the second control line SK2 are typically provided with driving signals by a shift register circuit located at an edge of the display panel 01.

After the present inventors studied the display panel in the related art, it is found that, when the control end 1023 of the threshold value grabbing module 102 in the ith row of pixel circuits 10 is electrically connected with the control end 1023 of the threshold value grabbing module 102 in the (i+1) th row of pixel circuits 10 and the same second control line SK2 (i), the number of shift register circuits at the edge of the display panel can be reduced, thereby being beneficial to reducing the frame of the display panel.

However, the signal transmitted by the same second control line SK2 (i) controls the switching states of the threshold value grasping module 102 in the pixel circuit 10 of the i-th row and the threshold value grasping module 102 in the pixel circuit 10 of the i+1-th row to be the same. In the period in which the threshold value grabbing module 102 in the ith row of pixel circuits 10 and the threshold value grabbing module 102 in the i+1 th row of pixel circuits 10 are turned on, the data writing module 101 in the ith row of pixel circuits 10 and the data writing module 101 in the i+1 th row of pixel circuits 10 are turned on in a time-sharing manner, which causes the first time period G1 in the ith row of pixel circuits 10 and the i+1 th row of pixel circuits 10 to be different, and further causes the time period of threshold value compensation of one of the ith row of pixel circuits 10 and the i+1 th row of pixel circuits 10, in which the first time period G1 is large, to be larger, thereby causing the gate potential of the driving transistor Md in the pixel circuit 10 in which the threshold value compensation time period is larger to be higher.

Since the magnitude of the light emission driving current supplied from the pixel circuit 10 to the light emitting element 20 is related to the gate potential of the driving transistor Md, the difference in brightness of the light emitting element 20 driven by the pixel circuit 10 in the i-th row and the pixel circuit 10 in the i+1-th row occurs, which results in a problem of bright and dark lines of the display panel, and affects the display quality of the display panel.

Therefore, in the embodiment of the present application, the control terminal 1023 of the threshold value grabbing module 102 in the ith row of pixel circuits 10 is electrically connected to the control terminal 1023 of the threshold value grabbing module 102 in the i+1th row of pixel circuits 10, and in the ith row of pixel circuits 10 and the ith+1th row of pixel circuits 10, the time when the first bias adjustment stage E1 in the row of pixel circuits 10 with the large first duration G1 is turned on is earlier than the time when the first bias adjustment stage E1 in the row of pixel circuits 10 with the small first duration G1 is turned on, so that the negative bias duration of the driving transistor Md in the row of pixel circuits 10 with the large first duration G1 is longer, and further the degree of negative bias of the driving transistor Md in the row of pixel circuits 10 with the large first duration G1 is greater. Since the speed of the charge transfer of the driving transistor Md with a larger negative bias voltage level is smaller, it is possible that the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the larger first period G1 is the same as the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the smaller first period G1, so that the brightness difference of the light emitting elements 20 respectively driven by the pixel circuit 10 in the i-th row and the pixel circuit 10 in the i+1-th row is reduced, the bright and dark line problem of the display panel is improved, and the display quality of the display panel is improved.

With continued reference to fig. 2 and 3, in one embodiment of the present application, the pixel circuit 10 further includes a first reset module 103, wherein an input terminal 1031 of the first reset module 103 is electrically connected to the first reset signal line SL1, and an output terminal 1032 is electrically connected to the gate of the driving transistor Md. The control terminal 1033 of the first reset module 103 in the i-th row of pixel circuits 10 is electrically connected to the control terminal 1033 of the first reset module 103 in the i+1-th row of pixel circuits 10.

Optionally, the control terminal 1033 of the first reset module 103 in the ith row of pixel circuits 10 and the control terminal 1033 of the first reset module 103 in the i+1th row of pixel circuits 10 are electrically connected to the same third control line SK3 (i), and the signal transmitted by the third control line SK3 (i) controls the switching states of the first reset module 103 in the ith row of pixel circuits 10 and the first reset module 103 in the i+1th row of pixel circuits 10 to be the same.

As shown in connection with fig. 4, one duty cycle Z of the pixel circuit 10 further includes a reset phase E11, the reset phase E11 being performed before the data writing phase E2.

The driving method further includes:

step B3: in the reset phase E11, the first reset module 103 is turned on.

In step B3, the first reset voltage Vref1 on the first reset signal line SL1 may be transmitted to the gate of the driving transistor Md through the turned-on first reset module 103, so as to complete the reset of the gate of the driving transistor Md.

Alternatively, as shown in conjunction with fig. 3 and 4, the first reset module 103 includes a first reset transistor M3, a first pole of the first reset transistor M3 is electrically connected to the first reset signal line SL1, a second pole is electrically connected to a gate of the driving transistor Md, and a gate is electrically connected to the third control line SK 3.

In the reset stage E11, the third control line SK3 transmits an active signal (e.g., a high level signal) to control the first reset transistor M3 to be turned on, the first reset signal line SL1 transmits the first reset voltage Vref1, and the first reset voltage Vref1 is transmitted to the gate of the driving transistor Md through the turned-on first reset transistor M3, so as to complete the reset of the gate of the driving transistor Md.

In one embodiment of the present application, the first bias adjustment stage E1 at least partially overlaps the reset stage E11 during one duty cycle Z of the pixel circuit 10.

Alternatively, as shown in fig. 4, the first bias adjustment stage E1 is located in the reset stage E11. That is, the period in which the data writing module 101 transmits the first adjustment voltage V1 to the first pole of the driving transistor Md is within the period in which the first reset module 103 transmits the first reset voltage Vref1 to the gate of the driving transistor Md.

The embodiment of the application can reduce the duration of one working period of the pixel circuit 10, and is beneficial to realizing high-frequency display of the display panel. Meanwhile, the threshold grabbing module 102 can be in the off state in the first bias adjustment stage E1 and the reset stage E11, so that the first adjustment voltage V1 can be prevented from influencing the reset of the gate of the driving transistor Md by the first reset voltage Vref 1.

Fig. 5 is a further timing diagram of the pixel circuit shown in fig. 3, and fig. 6 is a further timing diagram of the pixel circuit shown in fig. 3.

Alternatively, as shown in fig. 5, the first offset adjustment stage E1 may also be performed before the reset stage E11.

It should be noted that, in some other embodiments, as shown in fig. 6, it is also possible to provide that, among the i-th row of pixel circuits 10 and the i+1th row of pixel circuits 10, the first bias adjustment stage E1 of the pixel circuit 10 with the first length G1 being large is performed before the reset stage E11, and the first bias adjustment stage E1 of the pixel circuit 10 with the first length G1 being small at least partially overlaps the reset stage E11.

Fig. 7 is a schematic diagram of another pixel circuit according to an embodiment of the present application, fig. 8 is a schematic diagram of the pixel circuit shown in fig. 7, and fig. 9 is a timing diagram of the pixel circuit shown in fig. 8.

In one embodiment of the present application, as shown in fig. 7 and 8, the data writing module 101 includes a first sub data writing module 101A and a second sub data writing module 101B, and the first signal line DL1 includes a first sub signal line DL11 and a second sub signal line DL12.

The input terminal 101A1 of the first sub data writing module 101A is electrically connected to the first sub signal line DL11, and the output terminal 101A2 is electrically connected to the first pole of the driving transistor Md. The input terminal 101B1 of the second sub data writing module 101B is electrically connected to the second sub signal line DL12, and the output terminal 101B2 is electrically connected to the first pole of the driving transistor Md.

In step B1, in the first bias adjustment stage E1, the data writing module 101 is turned on, and the first signal line DL1 transmits the first adjustment voltage V1 to the data writing module 101, including:

step B11: in the first bias adjustment stage E1, the first sub data writing module 101A is turned on, the second sub data writing module 101B is turned off, and the first sub signal line DL11 transmits the first adjustment voltage V1 to the first sub data writing module 101A.

In step B2, in the data writing stage E2, the data writing module 101 and the threshold grabbing module 102 are turned on, and the first signal line DL1 transmits the data voltage Vdata to the data writing module 101, including:

step B21: in the data writing stage E2, the second sub data writing module 101B and the threshold grabbing module 102 are turned on, the first sub data writing module 101A is turned off, and the second sub signal line DL12 transmits the data voltage Vdata to the second sub data writing module 101B.

In step B11, in the first bias adjustment stage E1, the first adjustment voltage V1 may be transmitted to the first pole of the driving transistor Md through the turned-on first sub-data writing module 101A. In step B21, in the data writing phase E2, the data voltage Vdata may be transmitted to the gate of the driving transistor Md through the turned-on second sub-data writing module 101B, the driving transistor Md, and the threshold grabbing module 102.

Alternatively, as shown in conjunction with fig. 8 and 9, the first sub data writing module 101A includes a first sub data writing transistor M11, a first pole of the first sub data writing transistor M11 is electrically connected to the first sub signal line DL11, a second pole is electrically connected to a first pole of the driving transistor Md, and a gate is electrically connected to the first scan line SP 1. The second sub data writing module 101B includes a second sub data writing transistor M12, a first electrode of the second sub data writing transistor M12 is electrically connected to the second sub signal line DL12, a second electrode is electrically connected to the first electrode of the driving transistor Md, and a gate electrode is electrically connected to the second scan line SP 2. The threshold grabbing module 102 includes a threshold grabbing transistor M2, where a first pole of the threshold grabbing transistor M2 is electrically connected to a second pole of the driving transistor Md, the second pole is electrically connected to a gate of the driving transistor Md, and the gate is electrically connected to the third scan line SP 3.

In the first bias adjustment stage E1, the first scan line SP1 transmits an active signal (e.g., a low level signal) to control the first sub-data writing transistor M11 to be turned on; the first sub-signal line DL11 transmits the first regulated voltage V1, and the first regulated voltage V1 is transmitted to the first pole of the driving transistor Md through the turned-on first sub-data writing transistor M11.

In the data writing stage E2, the second scan line SP2 transmits an active signal (e.g., a low level signal) to control the second sub-data writing transistor M12 to be turned on; the third scan line SP3 transmits an active signal (e.g., a high level signal) to control the threshold grabbing transistor M2 to be turned on; the second sub signal line DL12 transmits the data voltage Vdata; since the driving transistor Md is turned on in the data writing stage E2, the data voltage Vdata can be transmitted to the gate of the driving transistor Md through the turned-on second sub-data writing transistor M12, the driving transistor Md and the threshold value grabbing transistor M2.

In the data writing stage E2, the duration between the time when the second sub data writing module 101B is turned off and the time when the threshold grabbing module 102 is turned off is the first duration G1. The first period G1 here refers to: in the same pixel circuit 10, in the data writing stage E2, the second sub data writing module 101B is turned on and turned off at a time between the time when the threshold value grabbing module 102 is turned on.

In the i-th row pixel circuit 10 and the i+1th row pixel circuit 10, the first sub data writing block 101A of the row pixel circuit 10 having the first length G1 is turned on earlier than the first sub data writing block 101A of the row pixel circuit 10 having the first length G1 is turned on.

For example, as shown in fig. 8 and 9, the first period G1 in the i-th row pixel circuit 10 is longer than the first period G1 in the i+1th row pixel circuit 10, and the timing at which the first sub-data writing module 101A of the i-th row pixel circuit 10 is turned on is earlier than the timing at which the first sub-data writing module 101A of the i+1th row pixel circuit 10 is turned on.

With continued reference to fig. 7 and 8, in one embodiment of the present application, the control end 1023 of the threshold grabbing module 102 is electrically connected to the third scan line SP3, and the control end 1043 of the first reset module 104 is electrically connected to the fourth scan line SP4

The threshold grabbing module 102 includes a threshold grabbing transistor M2, where a first pole of the threshold grabbing transistor M2 is electrically connected to a second pole of the driving transistor Md, the second pole is electrically connected to a gate of the driving transistor Md, and the gate is electrically connected to the third scan line SP 3.

The first reset module 103 includes a first reset transistor M3, a first pole of the first reset transistor M3 is electrically connected to the first reset signal line SL1, a second pole is electrically connected to a gate of the driving transistor Md, and a gate is electrically connected to the fourth scan line SP 4.

Alternatively, the first reset transistor M3 and the threshold grabbing transistor M2 each include a metal oxide active layer.

Specifically, the first reset transistor M3 and the threshold grabbing transistor M2 may each include an indium gallium zinc oxide (indium gallium zinc oxide, IGZO) active layer. Since the off-state leakage current of the oxide semiconductor transistor is low, the influence of the leakage current passing through the first reset transistor M3 or the threshold value grabbing transistor M2 on the gate potential of the driving transistor Md can be reduced, which is advantageous for maintaining the stability of the gate potential of the driving transistor Md, thereby being advantageous for improving the stability of the light emission driving current generated by the pixel circuit 10.

With continued reference to fig. 7 and 8, in one embodiment of the present application, the pixel circuit 10 further includes a second reset module 104, wherein an input terminal 1041 of the second reset module 104 is electrically connected to the second reset signal line SL2, an output terminal 1042 is electrically connected to the first electrode of the light emitting element 20, and a control terminal 1043 is electrically connected to the first scan line SP 1.

The signal transmitted by the first scan line SP1 controls the second reset module 104 to have the same switching state as the first sub data writing module 101A.

Alternatively, as shown in fig. 8, the second reset module 104 includes a second reset transistor M4, a first electrode of the second reset transistor M4 is electrically connected to the second reset signal line SL2, a second electrode is electrically connected to the first electrode of the light emitting element 20, and a gate electrode is electrically connected to the first scan line SP 1. The channel type of the second reset transistor M4 is the same as that of the first sub data write transistor M11.

In addition, as shown in fig. 2, 3, 7 and 8, the pixel circuit 10 further includes a power supply voltage writing module 105 and a light emitting control module 106, wherein an input end 1051 of the power supply voltage writing module 105 is electrically connected to the power supply voltage signal line DY1, an output end 1052 is electrically connected to the first pole of the driving transistor Md, and a control end 1053 is electrically connected to the light emitting control signal line EM. The input terminal 1061 of the light-emitting control module 106 is electrically connected to the second pole of the driving transistor Md, the output terminal 1062 is electrically connected to the first pole of the light-emitting element 20, and the control terminal 1063 is electrically connected to the light-emitting control signal line EM.

Alternatively, as shown in fig. 3 and 8, the power supply voltage writing module 105 includes a power supply voltage writing transistor M5, a first pole of the power supply voltage writing transistor M5 is electrically connected to the power supply voltage signal line DY1, a second pole is electrically connected to a first pole of the driving transistor Md, and a gate is electrically connected to the light emission control signal line EM. The light emission control module 106 includes a light emission control transistor M6, a first electrode of the light emission control transistor M6 is electrically connected to a second electrode of the driving transistor Md, a second electrode is electrically connected to a first electrode of the light emitting element 20, and a gate electrode is electrically connected to the light emission control signal line EM.

The i-th row pixel circuit 10 may be connected to the same emission control signal line EM (i) as the i+1-th row pixel circuit. Of course, the i-th row pixel circuit 10 and the i+1-th row pixel circuit 10 may be connected to different emission control signal lines EM.

For the sake of clarity of explanation of the technical solution of the present application, the operation of the pixel circuit 10 shown in fig. 8 will be described below with reference to fig. 8 and 9.

The first sub data writing transistor M11, the second sub data writing transistor M12, the second reset transistor M4, the power supply voltage writing transistor M5, and the light emission control transistor M6 are P-type transistors, and the threshold value grabbing transistor M2 and the first reset transistor M3 are N-type transistors. Of course, any one of the first sub data writing transistor M11, the second sub data writing transistor M12, the second reset transistor M4, the power supply voltage writing transistor M5, and the light emission control transistor M6 may be an N-type transistor, and any one of the threshold value grabbing transistor M2 and the first reset transistor M3 may be a P-type transistor.

One duty cycle Z of the pixel circuit 10 includes a reset stage E11, a first bias adjustment stage E1, a data writing stage E2, and a light emission stage E3.

In the reset stage E11, the fourth scan line SP4 transmits a high-level on signal, and the first reset transistor M3 is turned on; the second scan line SP2 and the emission control signal line EM both transmit a high-level off signal, and the second sub-data write transistor M12, the power supply voltage write transistor M5, and the emission control transistor M6 are turned off; the third scan line SP3 transmits a low-level off signal, and the threshold-grabbing transistor M2 is turned off. Meanwhile, the first reset signal line SL1 transmits the first reset voltage Vref1, and the first reset voltage Vref1 is transmitted to the gate of the driving transistor Md through the turned-on first reset transistor M3, thereby completing the reset of the gate of the driving transistor Md.

The first bias adjustment stage E1 is located in the reset stage E11, and in the first bias adjustment stage E1, the first scan line SP1 transmits a low-level turn-on signal, and the first sub data writing transistor M11 and the second reset transistor M4 are turned on. At this time, the first sub-signal line DL11 transmits the first adjustment voltage V1, and the first adjustment voltage V1 is transmitted to the first pole of the driving transistor Md through the turned-on first sub-data writing transistor M11, so that the driving transistor Md is negatively biased.

Meanwhile, the second reset signal line SL2 transmits the second reset voltage Vref2, and the second reset voltage Vref2 is transmitted to the first electrode of the light emitting element 20 through the turned-on second reset transistor M4, thereby completing the reset of the light emitting element 20. Alternatively, the light emitting element 20 includes an organic light emitting diode, and the second reset voltage Vref2 resets an anode of the organic light emitting diode through the turned-on fifth transistor M5.

In the data writing stage E2, the first scan line SP1 and the emission control signal line EM transmit a high-level off signal, and the first sub data writing transistor M11, the second reset transistor M4, the power supply voltage writing transistor M5, and the emission control transistor M6 are turned off. The second scan line SP2 transmits a low-level turn-on signal, and the second sub data write transistor M12 is turned on; the third scanning line SP3 transmits a high-level start signal, and the threshold value grabbing transistor M2 is turned on; the fourth scan line SP4 transmits a low-level off signal, and the first reset transistor M3 is turned off. Meanwhile, the second sub-signal line DL12 transmits the data voltage Vdata, at the start point of the data writing stage E2, the gate potential of the driving transistor Md is the first reset voltage Vref1, the first electrode potential of the driving transistor Md is the data voltage Vdata, the potential difference between the first electrode and the gate of the driving transistor Md is (Vdata-Vref 1), and the potential difference between the two is greater than 0, so that the driving transistor Md is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the threshold grabbing transistor M2, so that the gate potential of the driving transistor Md is gradually increased. When the gate potential of the driving transistor Md is equal to (Vdata-vth|), the driving transistor Md is turned off. Where Vth is the threshold voltage of the driving transistor Md.

In the light emitting stage E3, the first scan line SP1 and the second scan line SP2 transmit a high-level off signal, and the first sub data writing transistor M11, the second sub data writing transistor M12, and the second reset transistor M4 are turned off; the third scan line SP3 and the fourth scan line SP4 transmit a low-level off signal, and the threshold value grabbing transistor M2 and the first reset transistor M3 are turned off; the emission control signal line EM transmits a low-level on signal, and the power supply voltage writing transistor M5 and the emission control transistor M6 are turned on. Meanwhile, the power supply voltage signal line DY1 transmits the power supply voltage VDD, that is, the first polarity potential of the driving transistor Md is the power supply voltage VDD. Since the potential of the power supply voltage VDD is greater than the potential of the data voltage Vdata, the driving transistor Md generates a light emission driving current and transmits the light emission driving current to the light emitting element 20 through the light emission control transistor M6, controlling the light emitting element 20 to emit light.

Wherein, since the gate of the threshold value grabbing transistor M2 in the i-th row pixel circuit 10 and the gate of the threshold value grabbing transistor M2 in the i+1th row pixel circuit 10 are electrically connected to the same third scanning line SP3 (i), the period in which the threshold value grabbing transistor M2 in the i-th row pixel circuit 10 is turned on is the same as the period in which the threshold value grabbing transistor M2 in the i+1th row pixel circuit 10 is turned on. Since the period in which the second sub data writing transistor M12 in the i-th row pixel circuit 10 and the second sub data writing transistor M12 in the i+1-th row pixel circuit 10 are turned on is different and both are located in the period in which the threshold value grabbing transistor M2 is turned on, the case in which the first time length G1 in the i-th row pixel circuit 10 and the i+1-th row pixel circuit 10 is different occurs.

In the i-th row pixel circuit 10 and the i+1th row pixel circuit 10, the timing at which the first bias adjustment stage E1 of the row pixel circuit 10 having the first length G1 is set to be on is earlier than the timing at which the first bias adjustment stage E1 of the row pixel circuit 10 having the first length G1 is set to be on. The negative bias time of the driving transistor Md in the one row of the pixel circuits 10 having the large first time length G1 can be made longer, and further the degree of the negative bias of the driving transistor Md in the one row of the pixel circuits 10 having the large first time length G1 can be made larger. Since the speed of the charge transfer of the driving transistor Md with a larger negative bias voltage level is smaller, it is possible that the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the larger first period G1 is the same as the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the smaller first period G1, so that the brightness difference of the light emitting elements 20 respectively driven by the pixel circuit 10 in the i-th row and the pixel circuit 10 in the i+1-th row is reduced, the bright and dark line problem of the display panel is improved, and the display quality of the display panel is improved.

It should be noted that fig. 9 only illustrates that the first period G1 in the i-th row pixel circuit 10 is longer than the first period G1 in the i+1th row pixel circuit 10, and the time when the first bias adjustment stage E1 of the i-th row pixel circuit 10 is turned on is earlier than the time when the first bias adjustment stage E1 of the i+1th row pixel circuit 10 is turned on. In some other embodiments, the first period G1 in the i+1 row pixel circuit 10 may be set to be longer than the first period G1 in the i+1 row pixel circuit 10, and the time when the first bias adjustment stage E1 of the i+1 row pixel circuit 10 is turned on is earlier than the time when the first bias adjustment stage E1 of the i row pixel circuit 10 is turned on.

Fig. 10 is a schematic connection diagram of three adjacent rows of pixel circuits according to an embodiment of the present application, and the structure of the pixel circuit 10 shown in fig. 10 is the same as that of the pixel circuit 10 shown in fig. 8.

In one embodiment of the present application, as shown in fig. 8 and 10, in the pixel circuit 10, the control terminal 101A3 of the first sub-data writing module 101A is electrically connected to the first scan line SP1, and the control terminal 101B3 of the second sub-data writing module 101B is electrically connected to the second scan line SP 2.

The pixel circuits 10 of different rows are respectively electrically connected with different second scan lines SP2, the pixel circuits 10 of the j-th row and the pixel circuits 10 of the j+1th row are electrically connected with the same first scan line SP1, the control end 1023 of the threshold value grabbing module 102 in the pixel circuit 10 of the j-th row is electrically insulated from the control end 1023 of the threshold value grabbing module 102 in the pixel circuit 10 of the j+1th row, j is greater than or equal to 2, and j is not equal to i.

That is, the control terminal 101A3 of the first sub data writing module 101A in the jth row of pixel circuits 10 and the control terminal 101A3 of the first sub data writing module 101A in the jth+1 row of pixel circuits 10 are electrically connected to the same first scan line SP1 (j), and the control terminal 1023 of the threshold value grabbing module 102 in the jth row of pixel circuits 10 and the control terminal 1023 of the threshold value grabbing module 102 in the jth+1 row of pixel circuits 10 are electrically connected to different third scan lines SP3, j+.2, and j+.i, respectively.

Alternatively, j=i+1.

For example, as shown in fig. 8 and 10, when i=1, j=2, the third scanning line SP3 and the fourth scanning line SP4 electrically connected to the 1 st row pixel circuit 10 and the 2 nd row pixel circuit 10 are the same, and are different from the third scanning line SP3 and the fourth scanning line SP4 electrically connected to the 3 rd row pixel circuit 10; the first scanning line SP1 to which the 2 nd row pixel circuit 10 and the 3 rd row pixel circuit 10 are electrically connected is the same, and is different from the first scanning line SP1 to which the 1 st row pixel circuit 10 is electrically connected; the second scan lines SP2 to which the 1 st row pixel circuit 10, the 2 nd row pixel circuit 10, and the 3 rd row pixel circuit 10 are electrically connected are different from each other.

In this embodiment of the present application, the jth row of pixel circuits 10 and the jth+1th row of pixel circuits 10 are electrically connected to the same first scan line SP1, which is favorable for further reducing the number of wires in the display panel and reducing the cost of the display panel. Moreover, since the first scan line SP1 is typically provided with a driving signal by the shift register circuit located at the edge of the display panel 01, the number of shift register circuits at the edge of the display panel can be further reduced, which is beneficial to further reducing the frame of the display panel.

FIG. 11 is a timing diagram of the pixel circuit shown in FIG. 10.

In one embodiment of the present application, as shown in fig. 8, 10 and 11, in one working cycle Z of the pixel circuit 10, a time period between a time when the first sub-data writing module 101A is turned off and a time when the threshold grabbing module 102 is turned on is a second time period G2.

In the j-th row of pixel circuits 10 and the j+1th row of pixel circuits 10, the second period of time G2 in the row of pixel circuits 10 in which the first period of time G1 is large is longer than the second period of time G2 in the row of pixel circuits 10 in which the first period of time G1 is small.

It should be noted that fig. 11 only illustrates that the first period G1 of the j+1 row of pixel circuits 10 is longer than the first period G1 of the j row of pixel circuits 10, and the second period G2 of the j+1 row of pixel circuits 10 is longer than the second period G2 of the j row of pixel circuits 10. In some other embodiments, the first period G1 in the jth row of pixel circuits 10 may also be set to be longer than the first period G1 in the jth+1th row of pixel circuits 10, and the second period G2 of the jth row of pixel circuits 10 may be set to be longer than the second period G2 of the jth+1th row of pixel circuits 10.

In this embodiment of the present application, since the first scan lines SP1 electrically connected to the jth row of pixel circuits 10 and the jth+1th row of pixel circuits 10 are the same, the opening periods of the first sub-data writing modules 101A in the jth row of pixel circuits 10 and the jth+1th row of pixel circuits 10 are the same, and the second period G2 in the row of pixel circuits 10 with the large first period G1 is set to be larger, the negative bias period of the driving transistor Md in the row of pixel circuits 10 with the large first period G1 may be longer, and thus the degree of negative bias of the driving transistor Md in the row of pixel circuits 10 with the large first period G1 may be greater. Since the speed at which the driving transistor Md with a larger degree of negative bias transfers charges is smaller, it is possible that the gate potential of the driving transistor Md in the jth row pixel circuit 10 and the jth+1th row pixel circuit 10 is the same, which is advantageous for reducing the brightness difference of the light emitting element 20 driven by the jth row pixel circuit 10 and the jth+1th row pixel circuit 10, respectively, and for further improving the display quality of the display panel.

Fig. 12 is a schematic view of another display panel according to an embodiment of the present application.

The embodiment of the application provides a display panel 01, and the structure of the display panel 01 can be shown in fig. 1 and 12. The display panel 01 is driven in the driving manner provided in the above-described embodiment.

In the display panel 01, the control terminal 1023 of the threshold value grabbing module 102 in the ith row of pixel circuits 10 is electrically connected with the control terminal 1023 of the threshold value grabbing module 102 in the (i+1) th row of pixel circuits 10, and in the ith row of pixel circuits 10 and the (i+1) th row of pixel circuits 10, the time when the first bias adjustment stage E1 in the row of pixel circuits 10 with the large first time length G1 is started is earlier than the time when the first bias adjustment stage E1 in the row of pixel circuits 10 with the small first time length G1 is started, so that the negative bias time length of the driving transistor Md in the row of pixel circuits 10 with the large first time length G1 is longer, and the degree of the negative bias of the driving transistor Md in the row of pixel circuits 10 with the large first time length G1 is further longer. Since the speed of the charge transfer of the driving transistor Md with a larger negative bias voltage level is smaller, it is possible that the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the larger first period G1 is the same as the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the smaller first period G1, so that the brightness difference of the light emitting elements 20 respectively driven by the pixel circuit 10 in the i-th row and the pixel circuit 10 in the i+1-th row is reduced, the bright and dark line problem of the display panel 01 is improved, and the display quality of the display panel 01 is improved.

The embodiment of the present application provides a display device 02, as shown in fig. 13, where the display device 02 includes the display panel 01 provided in the above embodiment. The display device 02 may be an electronic device such as a mobile phone, a computer, a television, a vehicle-mounted display, a wearable electronic device, or the like.

In the display device 02, the control terminal 1023 of the threshold value grabbing module 102 in the ith row of pixel circuits 10 is electrically connected with the control terminal 1023 of the threshold value grabbing module 102 in the (i+1) th row of pixel circuits 10, and in the ith row of pixel circuits 10 and the (i+1) th row of pixel circuits 10, the time when the first bias adjustment stage E1 in the row of pixel circuits 10 with the large first time length G1 is started is earlier than the time when the first bias adjustment stage E1 in the row of pixel circuits 10 with the small first time length G1 is started, so that the negative bias time length of the driving transistor Md in the row of pixel circuits 10 with the large first time length G1 is longer, and the degree of the negative bias of the driving transistor Md in the row of pixel circuits 10 with the large first time length G1 is further longer. Since the speed of the charge transfer of the driving transistor Md with a larger negative bias voltage level is smaller, it is possible that the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the larger first period G1 is the same as the gate potential of the driving transistor Md in the pixel circuit 10 in the row with the smaller first period G1, so that the brightness difference of the light emitting elements 20 respectively driven by the pixel circuit 10 in the i-th row and the pixel circuit 10 in the i+1-th row is reduced, the bright and dark line problem of the display device 02 is improved, and the display quality of the display device 02 is improved.

The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A driving method of a display panel, wherein the display panel includes a plurality of rows of pixel circuits, the pixel circuits comprising:

a driving transistor for generating a light emission driving current;

the input end of the data writing module is electrically connected with the first signal line, and the output end of the data writing module is electrically connected with the first pole of the driving transistor;

the input end of the threshold grabbing module is electrically connected with the second pole of the driving transistor, and the output end of the threshold grabbing module is electrically connected with the grid electrode of the driving transistor;

the control end of the threshold grabbing module in the ith row of pixel circuits is electrically connected with the control end of the threshold grabbing module in the (i+1) th row of pixel circuits, and i is more than or equal to 1;

one duty cycle of the pixel circuit includes a first bias adjustment phase and a data writing phase performed after the first bias adjustment phase;

the driving method includes:

in the first bias adjustment stage, the data writing module is started, and the first signal line transmits a first adjustment voltage to the data writing module;

In the data writing stage, the data writing module and the threshold grabbing module are started, the first signal line transmits data voltage to the data writing module, and the duration between the closing time of the data writing module and the closing time of the threshold grabbing module is a first duration;

in the ith row of pixel circuits and the (i+1) th row of pixel circuits, the first bias adjustment stage of the first long row of pixel circuits is started earlier than the first bias adjustment stage of the first short row of pixel circuits.

2. The driving method according to claim 1, wherein the pixel circuit further comprises a first reset module having an input terminal electrically connected to a first reset signal line and an output terminal electrically connected to a gate of the driving transistor; the control end of the first reset module in the ith row of pixel circuits is electrically connected with the control end of the first reset module in the (i+1) th row of pixel circuits;

one duty cycle of the pixel circuit further includes a reset phase, which is performed before the data writing phase;

the driving method further includes:

In the reset phase, the first reset module is turned on.

3. The driving method according to claim 2, wherein the first bias adjustment stage is performed before the reset stage.

4. The driving method according to claim 2, wherein the first bias adjustment phase at least partially overlaps the reset phase.

5. The driving method according to claim 1, wherein the data writing module includes a first sub data writing module and a second sub data writing module, the first signal line includes a first sub signal line and a second sub signal line, an input terminal of the first sub data writing module is electrically connected to the first sub signal line, and an output terminal is electrically connected to a first pole of the driving transistor; the input end of the second sub data writing module is electrically connected with the second sub signal line, and the output end of the second sub data writing module is electrically connected with the first electrode of the driving transistor;

the first bias adjustment stage, in which the data writing module is turned on, the first signal line transmits a first adjustment voltage to the data writing module, includes:

in the first bias adjustment stage, the first sub-data writing module is turned on, the second sub-data writing module is turned off, and the first sub-signal line transmits a first adjustment voltage to the first sub-data writing module;

The data writing module and the threshold grabbing module are turned on in the data writing stage, the first signal line transmits data voltage to the data writing module, and the data writing module comprises:

in the data writing stage, the second sub-data writing module and the threshold grabbing module are turned on, the first sub-data writing module is turned off, and the second sub-signal line transmits data voltage to the second sub-data writing module.

6. The driving method according to claim 5, wherein a time period between a time when the second sub data writing module is turned off and a time when the threshold grabbing module is turned off is a first time period in the data writing stage;

in the ith row of pixel circuits and the (i+1) th row of pixel circuits, the starting time of the first sub-data writing module of the first long row of pixel circuits is earlier than the starting time of the first sub-data writing module of the first long row of pixel circuits.

7. The driving method according to claim 5, wherein a control terminal of the first sub data writing module is electrically connected to a first scan line, and a control terminal of the second sub data writing module is electrically connected to a second scan line;

The pixel circuits of different rows are respectively electrically connected with different second scanning lines, the pixel circuits of the j row and the pixel circuits of the j+1 row are electrically connected with the same first scanning line, the control end of the threshold grabbing module in the pixel circuit of the j row is electrically insulated from the control end of the threshold grabbing module in the pixel circuit of the j+1 row, j is more than or equal to 2, and j is not equal to i.

8. The driving method according to claim 7, wherein a time period between a time when the first sub data writing module is turned off and a time when the threshold grabbing module is turned on is a second time period in one operation cycle of the pixel circuit;

in the j-th row pixel circuit and the j+1th row pixel circuit, a second time period in the first-time-long row pixel circuit is longer than a second time period in the first-time-long row pixel circuit.

9. The driving method according to claim 7, wherein the pixel circuit further comprises a second reset module having an input terminal electrically connected to a second reset signal line, an output terminal electrically connected to a first electrode of the light emitting element, and a control terminal electrically connected to the first scan line;

The signal transmitted by the first scanning line controls the switch states of the second reset module and the first sub-data writing module to be the same.

10. The driving method according to claim 2, wherein a control end of the threshold value grabbing module is electrically connected with a third scanning line, and a control end of the first reset module is electrically connected with a fourth scanning line;

the threshold grabbing module comprises a threshold grabbing transistor, wherein a first pole of the threshold grabbing transistor is electrically connected with a second pole of the driving transistor, the second pole is electrically connected with a grid electrode of the driving transistor, and the grid electrode is electrically connected with the third scanning line;

the first reset module comprises a first reset transistor, wherein a first pole of the first reset transistor is electrically connected with the first reset signal line, a second pole of the first reset transistor is electrically connected with a grid electrode of the driving transistor, and the grid electrode of the first reset transistor is electrically connected with the fourth scanning line.

11. The driving method according to claim 10, wherein the first reset transistor and the threshold-grabbing transistor each include a metal oxide active layer.

12. A display panel, characterized in that the display panel is driven using the driving method according to any one of claims 1-11.

13. A display device comprising the display panel according to claim 12.