CN116052600A - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN116052600A CN116052600A CN202310097768.4A CN202310097768A CN116052600A CN 116052600 A CN116052600 A CN 116052600A CN 202310097768 A CN202310097768 A CN 202310097768A CN 116052600 A CN116052600 A CN 116052600A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000001105 regulatory effect Effects 0.000 claims abstract description 26
- 230000003750 conditioning effect Effects 0.000 claims description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 26
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
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- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The embodiment of the application provides a display panel, a driving method thereof and a display device, wherein a pixel circuit in the display panel comprises a driving transistor and a data voltage writing module; the first phase of the pixel circuit comprises a data writing phase, a first adjusting phase and a first light-emitting phase, wherein the duration between the first adjusting phase and the first light-emitting phase is a first duration; the second stage comprises a second adjusting stage and a second light-emitting stage, and the time length between the second adjusting stage and the second light-emitting stage is a second time length; in a first regulation stage, the data voltage writing module transmits a first regulation voltage to the driving transistor; in a second regulation stage, the data voltage writing module transmits a second regulation voltage to the driving transistor; the first regulated voltage is at a different potential than the second regulated voltage and/or the first duration is at a different magnitude than the second duration. The method and the device can reduce the brightness difference between the first stage and the second stage, and improve the flicker problem of the display panel, especially the flicker problem during low gray scale display.
Description
[ field of technology ]
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.
[ background Art ]
An organic light-emitting diode (OLED) display panel has advantages of low power consumption, self-luminescence, wide viewing angle, wide temperature characteristics, fast response speed, and the like, and has wide application in the market. Among them, the pixel circuit for controlling the light emission of the light emitting device is a core technical content of the OLED display panel, and has important research significance.
In the conventional pixel circuit, due to the operation characteristics of the driving transistor, the light-emitting brightness of the display panel in the first stage and the light-emitting brightness in the second stage have a large difference, which affects the display effect. The first phase is a phase including a data writing phase and a light emitting phase, and the second phase is a phase which is performed after the first phase and does not include a data voltage writing phase but includes a light emitting phase. Especially, in the low gray scale and low frequency display state of the display panel, the difference of the light-emitting brightness of the display panel in the first stage and the second stage is very obvious, and the display effect of the display panel is seriously affected.
[ MEANS FOR SOLVING PROBLEMS ]
In view of the foregoing, embodiments of the present application provide a display panel, a driving method thereof, and a display device to solve the foregoing problems.
In a first aspect, embodiments of the present application provide a display panel, the display panel including a plurality of pixel circuits, the pixel circuits including:
a driving transistor for generating a light emission driving current;
the input end of the data voltage writing module is electrically connected with the first signal line, and the output end of the data voltage writing module is electrically connected with the first pole of the driving transistor;
one duty cycle of the pixel circuit includes a first phase and a second phase performed after the first phase; the first phase comprises a data writing phase, a first adjusting phase and a first light-emitting phase which are sequentially carried out, wherein the duration between the first adjusting phase and the first light-emitting phase is a first duration; the second stage comprises a second adjusting stage and a second light-emitting stage which are sequentially carried out, and the duration between the second adjusting stage and the second light-emitting stage is a second duration;
in a first regulation phase, the data voltage writing module transmits a first regulation voltage to a first pole of the driving transistor; in a second regulation phase, the data voltage writing module transmits a second regulation voltage to the first pole of the driving transistor;
wherein the first regulating voltage and the second regulating voltage are different in potential and/or the first duration and the second duration are different in magnitude.
In a second aspect, embodiments of the present application provide a driving method of a display panel, for driving the display panel provided in the first aspect, the driving method including:
in a first regulation phase, the data voltage writing module transmits a first regulation voltage to a first pole of the driving transistor; in a second regulation phase, the data voltage writing module transmits a second regulation voltage to the first pole of the driving transistor;
wherein the first regulation voltage is different in magnitude from the second regulation voltage, and/or the first duration is different in magnitude from the second duration.
In a third aspect, embodiments of the present application provide a display device including a display panel as provided in the first aspect.
In the embodiment of the application, in the first adjustment stage of the first stage, the first adjustment voltage can correct the bias state of the driving transistor, so as to reduce the bias state difference of the driving transistor in the first stage and the second stage. In addition, in the second adjusting stage of the second stage, the second adjusting voltage can further correct the bias state of the driving transistor, so that the bias state difference of the driving transistor in the first stage and the second stage is further reduced, the gradient speed difference of the current received by the light emitting element in the first stage and the second stage is reduced, and the brightness difference of the display panel in the first stage and the second stage is reduced.
In addition, when the display panel performs lower gray scale display, the first adjusting voltage and the second adjusting voltage mainly serve to reset the electric potential of the first pole of the driving transistor, so that the electric potentials of the first adjusting voltage and the second adjusting voltage are different, and/or the first time length is different from the second time length, according to the electric potential difference of the first pole of the driving transistor at the starting moment of the first adjusting stage and the electric potential difference of the first pole of the driving transistor at the starting moment of the second adjusting stage, the electric potentials of the first adjusting voltage and the second adjusting voltage and the electric potentials of the first time length and the electric potential of the second time length are flexibly set, so that the first pole electric potential of the driving transistor is the same at the starting moment of the first light-emitting stage and the starting moment of the second light-emitting stage, the quantity difference of the luminous charges generated by the pixel circuit after passing through the first pole of the driving transistor in the first light-emitting stage and the second light-emitting stage is reduced, the brightness difference of the first stage and the second stage of the display panel in lower gray scale display is facilitated to be reduced, the flicker effect of the display panel is facilitated to be improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the pixel circuit of FIG. 1;
FIG. 3 is a schematic diagram of the pixel circuit shown in FIG. 2;
FIG. 4 is a timing diagram of the pixel circuit shown in FIG. 3;
FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 3;
FIG. 6 is a timing diagram of the pixel circuit shown in FIG. 3;
FIG. 7 is a timing diagram of the pixel circuit shown in FIG. 3;
FIG. 8 is a schematic diagram of another display panel according to an embodiment of the disclosure;
FIG. 9 is a schematic diagram of the pixel circuit of FIG. 8;
FIG. 10 is a schematic diagram of the pixel circuit shown in FIG. 9;
FIG. 11 is a timing diagram of the pixel circuit shown in FIG. 10;
FIG. 12 is a timing diagram of the pixel circuit of FIG. 10;
FIG. 13 is a timing diagram of the pixel circuit of FIG. 10;
FIG. 14 is a schematic view showing brightness of a display panel according to the related art;
FIG. 15 is a timing diagram of the pixel circuit of FIG. 10;
FIG. 16 is a timing diagram of the pixel circuit of FIG. 10;
fig. 17 is a schematic diagram of a display device according to an embodiment of the present application.
[ detailed description ] of the invention
For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and examples herein refer to values that are generally agreed upon, rather than exact, within reasonable process operating ranges or tolerances.
It should be understood that although the terms first, second, etc. may be used in embodiments of the present application to describe the conditioning phase, conditioning voltage, duration, etc., these conditioning phases, conditioning voltages, durations, etc. should not be limited to these terms. These terms are only used to distinguish the regulation phase, regulation voltage, duration, etc. from each other. For example, a first conditioning phase may also be referred to as a second conditioning phase, and similarly, a second conditioning phase may also be referred to as a first conditioning phase, without departing from the scope of embodiments of the present application.
The applicant has provided a solution to the problems existing in the prior art by intensive studies.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application, fig. 2 is a schematic diagram of the pixel circuit in fig. 1, fig. 3 is a schematic diagram of the pixel circuit in fig. 2, fig. 4 is a timing chart of the pixel circuit in fig. 3, fig. 5 is a timing chart of the pixel circuit in fig. 3, and fig. 6 is a timing chart of the pixel circuit in fig. 3.
The embodiment of the application provides a display panel 01, as shown in fig. 1, the display panel 01 includes a plurality of pixel circuits 10, a light emitting device 20, and a plurality of first signal lines DL1 arranged along a first direction X, the first signal lines DL1 extend along a second direction Y, and at least part of the pixel circuits 10 arranged along the first direction Y are electrically connected to the same first signal lines DL 1. The pixel circuit 10 is electrically connected to the light emitting element 20 for supplying the light emitting element 20 with a light emission driving current.
As shown in fig. 2 to 4, the pixel circuit 10 includes a driving transistor Md for generating a light emission driving current and a data voltage writing module 101; the input terminal 1011 of the data voltage writing module 101 is electrically connected to the first signal line DL1, and the output terminal 1012 is electrically connected to the first pole of the driving transistor Md. The first pole of the driving transistor Md may be a source thereof.
One duty cycle Z of the pixel circuit 10 includes a first phase T1 and a second phase T2 performed after the first phase; the first phase T1 includes a data writing phase E1, a first adjusting phase E2, and a first light emitting phase E3, which are sequentially performed, i.e., the first adjusting phase E2 is performed after the data writing phase E1, and the first light emitting phase E3 is performed after the first adjusting phase E2. The duration between the first adjustment stage E2 and the first lighting stage E3 is a first duration G1, where the duration between the first adjustment stage E2 and the first lighting stage E3 refers to a duration between a time when the first adjustment stage E2 ends and a time when the first lighting stage E3 is turned on.
The second phase T2 comprises a second conditioning phase E4 and a second lighting phase E5, which are carried out in succession, i.e. the second lighting phase E5 is carried out after the second conditioning phase E4. The duration between the second adjustment stage E4 and the second light-emitting stage E5 is a second duration G2, where the duration between the second adjustment stage E4 and the second light-emitting stage E5 refers to a duration between a time when the second adjustment stage E4 ends and a time when the second light-emitting stage E5 is turned on.
In the data writing phase E1, the data voltage writing module 101 transmits the data voltage Vdata to the first pole of the driving transistor Md.
In the first regulation stage E2, the data voltage writing module 101 transmits the first regulation voltage V1 to the first pole of the driving transistor Md.
In the second regulation stage E4, the data voltage writing module 101 transmits the second regulation voltage V2 to the first pole of the driving transistor Md.
Alternatively, as shown in fig. 3, the data voltage writing module 101 includes a first transistor M1, a first electrode of the first transistor M1 is electrically connected to the first signal line DL1, a second electrode of the first transistor M is electrically connected to the first electrode of the driving transistor Md, and a gate electrode of the first transistor M1 is electrically connected to the first scan line SP 1. The first pole of the first transistor M1 may be its source and the second pole may be its drain.
Referring to fig. 4, in the data writing stage E1, the first scan line SP1 transmits an active signal (e.g., a low level signal) to control the first transistor M1 to be turned on, the first signal line DL1 transmits the data voltage Vdata, and the data voltage Vdata is transmitted to the first pole of the driving transistor Md through the turned-on first transistor M1.
In the first adjustment stage E2, the first scan line SP1 transmits an active signal (e.g., a low level signal) to control the first transistor M1 to be turned on, the first signal line DL1 transmits a first adjustment voltage V1, and the first adjustment voltage V1 is transmitted to the first pole of the driving transistor Md through the turned-on first transistor M1.
In the second adjustment stage E4, the first scan line SP1 transmits an active signal (e.g., a low level signal) to control the first transistor M1 to be turned on, the first signal line DL1 transmits the second adjustment voltage V2, and the second adjustment voltage V2 is transmitted to the first pole of the driving transistor Md through the turned-on first transistor M1.
Wherein the first regulating voltage V1 and the second regulating voltage V2 are different in potential and/or the first duration G1 and the second duration G2 are different in magnitude.
That is, in the display panel 01 provided in the embodiment of the present application, as shown in fig. 4, the first adjustment voltage V1 and the second adjustment voltage V2 may be set to have different potentials, and the first duration G1 and the second duration G2 have the same magnitude; as shown in fig. 5, the first adjusting voltage V1 and the second adjusting voltage V2 may be set to have the same potential, and the first time period G1 and the second time period G2 may be different in size; as shown in fig. 6, the first regulated voltage V1 and the second regulated voltage V2 may be set to be different in potential, and the first time period G1 and the second time period G2 may be different in magnitude.
In the related art, in the first stage T1 of the pixel circuit 10, in order to generate the light emission driving current that meets the requirements of the driving transistor Md, it is necessary to reset the gate of the driving transistor Md and then write the data voltage Vdata to the gate of the driving transistor Md. To ensure that the driving transistor Md can generate the light-emitting driving current in accordance with the requirement in the first light-emitting stage E3 of the first stage T1 and transmit the light-emitting driving current to the light-emitting device 20. In the second phase T2 of the pixel circuit 10, the gate of the driving transistor Md is not reset and the data voltage Vdata is written, and the gate of the driving transistor Md maintains a potential substantially equivalent to that in the previous light emitting phase and is transmitted to the light emitting element 20 after the light emitting driving current is generated.
The present inventors have studied to find that there is a current ramp-up process at the initial stage of light emission of the light emitting element 20, and the current ramp-up speed is related to the bias state of the driving transistor Md. Since the pixel circuit 10 does not perform the gate reset and the writing of the data voltage Vdata to the driving transistor Md in the second stage T2 as performed in the first stage T1, the bias state of the driving transistor Md is greatly different between the initial stage of the second light-emitting stage E5 of the second stage T2 and the initial stage of the first light-emitting stage E3 of the first stage T1, so that the speed difference of the current ramp received by the light-emitting element 20 is greatly increased in the first stage T1 and the second stage T2, and the brightness difference of the display panel 01 in the first stage T1 and the second stage T2 is greatly increased, which results in a flicker problem and affects the normal display of the display panel 01.
In the embodiment of the present application, in the first adjustment stage E2 of the first stage T1, the first signal line DL1 may transmit the first adjustment voltage V1 to the first pole of the driving transistor Md through the turned-on data voltage writing module 101, so that the bias state of the driving transistor Md may be corrected, and the bias state difference of the driving transistor Md in the first stage T1 and the second stage T2 may be reduced. In addition, in the second adjustment stage E4 of the second stage T2, the first signal line DL1 may transmit the second adjustment voltage V2 to the first pole of the driving transistor Md through the turned-on data voltage writing module 101, so that the bias state of the driving transistor Md may be further corrected, and the bias state difference of the driving transistor Md in the first stage T1 and the second stage T2 may be further reduced, thereby being beneficial to reducing the ramp speed difference of the current received by the light emitting element 20 in the first stage T1 and the second stage T2, and further being beneficial to reducing the brightness difference of the display panel 01 in the first stage T1 and the second stage T2, and improving the display effect of the display panel 01.
It should be noted that the potentials of the first adjusting voltage V1 and the second adjusting voltage V2 may be flexibly configured according to the bias condition of the driving transistor Md, so long as the bias state difference of the driving transistor Md in the first stage T1 and the second stage T2 can be reduced.
Further, the present inventors have also found through research that, when the display panel 01 performs a lower gray scale display, especially when the display brightness is below 0.5nit, the effect of the first adjustment voltage V1 and the second adjustment voltage V2 to correct the bias state of the driving transistor Md is reduced, which mainly serves to reset the first pole of the driving transistor Md. If the first polarity potential of the driving transistor Md cannot be set to be the same at the start time of the first light-emitting period E3 and the start time of the second light-emitting period E5, the pixel circuit 10 is caused to generate different amounts of light-emitting charges through the first polarity of the driving transistor Md in the first light-emitting period E3 and the second light-emitting period E5, so that the charges supplied to the light-emitting element 20 by the pixel circuit 10 in the first light-emitting period E3 and the second light-emitting period E5 are caused to be different, and the brightness of the first period T1 and the second period T2 is caused to be different when the display panel 01 is displayed in a low gray scale, so that a flicker problem which can be observed by a user, particularly when the display panel 01 is displayed in a low frequency, is caused to be very obvious.
Furthermore, the present inventors have found that since the pixel circuit 10 does not perform the gate reset and the write data voltage Vdata to the driving transistor Md as performed in the first phase T1 in the second phase T2, the first electrode potential of the driving transistor Md is generally different between the start timing of the first adjustment phase E2 and the start timing of the second adjustment phase E4, and thus the first electrode potential of the driving transistor Md is made to be different between the first adjustment voltage V1 and the second adjustment voltage V2, so that the first electrode potential of the driving transistor Md is the same between the start timing of the first light-emitting phase E3 and the start timing of the second light-emitting phase E5 becomes a solution.
In addition, since the transistor is in an off state, a leakage current phenomenon occurs. After the first adjustment phase E2, the first polarity potential of the driving transistor Md is generally changed due to the leakage current. After the second adjustment stage E4, the potential of the first electrode of the driving transistor Md also changes due to the leakage current. It is also a solution to set the magnitudes of the first and second durations G1, G2 to be different so that the potential of the first pole of the drive transistor Md at the start of the first light-emitting phase E3 is the same as at the start of the second light-emitting phase E5.
In this embodiment of the present application, the first adjustment voltage V1 and the second adjustment voltage V2 are set to have different potentials, and/or the first duration G1 and the second duration G2 are different in size, so that the difference between the number of the first poles of the driving transistor Md after the first poles of the driving transistor Md pass through the first poles of the driving transistor Md in the first adjustment stage E2 and the second adjustment stage E4 in the first adjustment stage E4 can be reduced, the difference between the first adjustment voltage V1 and the second adjustment voltage V2, and the first duration G1 and the second duration G2 can be flexibly set, so that the first pole potential of the driving transistor Md is possible at the first time of the first lighting stage E3 and the second time of the second lighting stage E5, which is beneficial to reducing the difference between the number of the light-emitting charges generated by the pixel circuit 10 after the first poles of the driving transistor Md in the first lighting stage E3 and the second lighting stage E5, thereby being beneficial to reducing the difference between the first stage T1 and the second stage T2 in the low gray scale display of the display panel 01, and further beneficial to improving the flicker effect of the display panel 01 in the low gray scale display.
Fig. 7 is a timing diagram of the pixel circuit shown in fig. 3.
In one embodiment of the present application, in one duty cycle Z of the pixel circuit 10, the first phase T1 includes n1 first conditioning phases E2, the second phase T2 includes n2 second conditioning phases E4, n1.gtoreq.1, n2.gtoreq.1.
The first period G1 is a period between the first adjustment stage E2 and the first lighting stage E3, which are last performed in time sequence in the n1 first adjustment stages E2.
The second period G2 is a period between the second adjustment phase E4 and the second light-emitting phase E5, which is last performed in time sequence in the n2 second adjustment phases E4.
For example, as shown in fig. 7, the first phase T1 includes 1 first adjustment phase E2, and the first period G1 is a period between the first adjustment phase E2 and the first lighting phase E3.
The second stage T2 includes 2 second adjustment stages E4, and the 2 second adjustment stages E4 may be a first sub-adjustment stage E41 and a second sub-adjustment stage E42, the second sub-adjustment stage E42 being performed after the first sub-adjustment stage E41, and the second light-emitting stage E5 being performed after the second sub-adjustment stage E42, the second period of time G2 being a period of time between the second sub-adjustment stage E42 and the second light-emitting stage E4.
According to the embodiment of the application, the first electrode of the driving transistor Md can be regulated in potential at the starting moment of the first light-emitting stage E3 by the first time length G1, and the second electrode of the driving transistor Md can be regulated in potential at the starting moment of the second light-emitting stage E5 by the second time length G2, so that the potential of the first electrode of the driving transistor Md tends to be consistent at the starting moment of the first light-emitting stage E3 and the starting moment of the second light-emitting stage E5 by setting the different sizes of the first time length G1 and the second time length G2, and the brightness difference between the first stage T1 and the second stage T2 is reduced when the display panel 01 is displayed in a low gray scale, and the display quality is improved.
Fig. 8 is a schematic diagram of another display panel according to an embodiment of the present application, fig. 9 is a schematic diagram of the pixel circuit in fig. 8, fig. 10 is a schematic diagram of the pixel circuit in fig. 9, fig. 11 is a timing chart of the pixel circuit in fig. 10, fig. 12 is another timing chart of the pixel circuit in fig. 10, and fig. 13 is another timing chart of the pixel circuit in fig. 10.
In one embodiment of the present application, as shown in fig. 8-10, the first signal line DL1 includes a first sub-signal line DL11 and a second sub-signal line DL12, the input terminal 1011 of the data voltage writing module 101 includes a first sub-input terminal 10111 and a second sub-output terminal 10112, the first sub-input terminal 10111 is electrically connected to the first sub-signal line DL11, and the second sub-input terminal 10112 is electrically connected to the second sub-signal line DL 12. The data voltage writing module 101 includes a first transistor M1 and a second transistor M2, wherein a first pole of the first transistor M1 is electrically connected to the first sub-signal line DL11, a second pole is electrically connected to a first pole of the driving transistor Md, and a gate is electrically connected to the first scan line SP 1. The first electrode of the second transistor M2 is electrically connected to the second sub-signal line DL12, the second electrode is electrically connected to the first electrode of the driving transistor Md, and the gate electrode is electrically connected to the second scan line SP 2.
In conjunction with fig. 11, in the data writing stage E1, the first scan line SP1 transmits an active signal (e.g., a low level signal) to control the first transistor M1 to be turned on, and the second scan line SP2 transmits an active signal (e.g., a high level signal) to control the second transistor M2 to be turned off, and the first sub-signal line DL11 transmits the data voltage Vdata, which is transmitted to the first pole of the driving transistor Md through the turned-on first transistor M1.
In the first adjustment stage E2 and the second adjustment stage E4, the first scan line SP1 transmits an active signal (e.g., a high level signal) to control the first transistor M1 to be turned off, and the second scan line SP2 transmits an active signal (e.g., a low level signal) to control the second transistor M2 to be turned on, and the second sub-signal line DL12 transmits the first adjustment voltage V1 in the first adjustment stage E2 and the second adjustment voltage V2 in the second adjustment stage E4. That is, in the first regulation stage E2, the first regulation voltage V1 on the second sub-signal line DL12 is transmitted to the first pole of the driving transistor Md through the turned-on second transistor M2; in the second regulation stage E4, the second regulation voltage V2 on the second sub-signal line DL12 is transmitted to the first pole of the driving transistor Md through the turned-on second transistor M2.
As shown in fig. 12 and 13, when the first phase T1 includes more than one first adjustment phase E2, the first period G1 is: in the first phase T1, the second scan line SP2 transmits an active signal (e.g., a low level signal) to control a duration between an end time of last turning on of the second transistor M2 and a time of turning on of the first light emitting phase E3. When the second phase T2 includes more than one second conditioning phase E4, the second duration G2 is: in the second stage T2, the second scan line SP2 transmits an active signal (e.g., a low level signal) to control a duration between an end time of last turning on of the second transistor M2 and a time of turning on of the second light emitting stage E5.
In this embodiment, the first sub-signal line DL11 and the first transistor M1 are set to transmit the data voltage Vdata to the driving transistor Md, and the second sub-signal line DL12 and the second transistor M2 are set to transmit the first adjusting voltage V1 and the second adjusting voltage V2 to the driving transistor Md, which is beneficial to reducing the driving difficulty of the pixel circuit 10 and reducing the design difficulty of the peripheral driving circuit.
With continued reference to fig. 2, 3, 9 and 10, in one embodiment of the present application, the pixel circuit 10 further includes a threshold voltage grabbing module 102, an input end 1021 of the threshold voltage grabbing module 102 is electrically connected to the second pole of the driving transistor Md, an output end 1022 of the threshold voltage grabbing module is electrically connected to the gate of the driving transistor Md, and the second pole of the driving transistor Md may be the drain thereof.
In the data writing phase E1, the threshold voltage grabbing module 102 is turned on. In the first and second regulation phases E2 and E4, the threshold voltage grabbing module 102 is turned off.
Alternatively, as shown in fig. 3 and 4, or in fig. 10 and 11, the threshold voltage grabbing module 102 includes a third transistor M3, the first pole of the third transistor M3 is electrically connected to the second pole of the driving transistor Md, the second pole is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the third scan line SP 3.
In the data writing stage E1, the third scan line SP3 transmits an active signal (e.g., a high signal) to control the third transistor M3 to turn on, so as to ensure that the data voltage Vdata can be transmitted to the gate of the driving transistor Md. In the first adjusting stage E2 and the second adjusting stage E4, the third scan line SP3 transmits an active signal (e.g., a low level signal) to control the third transistor M3 to be turned off, so as to avoid the first adjusting voltage V1 and the second adjusting voltage V2 from affecting the gate potential of the driving transistor Md.
Optionally, the third transistor M3 includes a metal oxide active layer.
In particular, the third transistor M3 may include an indium gallium zinc oxide (indium gallium zinc oxide, IGZO) active layer. Since the off-state leakage current of the oxide semiconductor transistor is low, the third transistor M3 is beneficial to reducing the leakage current of the light-emitting driving current flowing to the gate of the driving transistor Md, and to maintaining the stability of the potential of the gate of the driving transistor Md, thereby improving the stability of the light-emitting driving current generated by the pixel circuit 10.
In one embodiment of the present application, please continue to refer to fig. 2, 3, 9 and 10, the pixel circuit 10 further includes a first reset module 103, an input terminal 1031 of the first reset module 103 is electrically connected to the first reset line SL1, and an output terminal 1032 is electrically connected to the gate of the driving transistor Md. The first reset module 103 is configured to reset the gate of the driving transistor Md.
As shown in fig. 4 to 7 and 11 to 13, the first phase T1 further includes a reset phase E0, and the reset phase E0 is performed before the data writing phase E1.
In the reset phase E0, the first reset module 103 is turned on, and the first reset line SL1 transmits the first reset voltage Vref1.
In the data writing phase E1, the first adjusting phase E2 and the second adjusting phase E4, the first reset module 103 is turned off.
Alternatively, as shown in fig. 3 and 4, or in fig. 10 and 11, the first reset module 103 includes a fourth transistor M4, a first electrode of the fourth transistor M4 is electrically connected to the first reset line SL1, a second electrode is electrically connected to a gate of the driving transistor Md, and a gate is electrically connected to the fourth scan line SP 4.
In the reset stage E0, the fourth scan line SP4 transmits an active signal (e.g., a high level signal) to control the fourth transistor M4 to be turned on, and the first reset voltage Vref1 on the first reset line SL1 is transmitted to the gate of the driving transistor Md through the turned-on fourth transistor M4, so as to complete the reset of the gate of the driving transistor Md.
In the data writing stage E1, the first adjusting stage E2 and the second adjusting stage E4, the fourth scan line SP4 transmits an effective signal (e.g. a low level signal) to control the fourth transistor M4 to be turned off, so as to avoid the first reset voltage Vref1 from affecting the gate potential of the driving transistor Md.
Optionally, the fourth transistor M4 includes a metal oxide active layer.
Specifically, the fourth transistor M4 may include an indium gallium zinc oxide (indium gallium zinc oxide, IGZO) active layer. Since the off-state leakage current of the oxide semiconductor transistor is low, the leakage current of the gate of the driving transistor Md through the fourth transistor M4 is small, which is beneficial to reducing the influence of the leakage current on the stability of the gate potential of the driving transistor Md, thereby being beneficial to improving the stability of the light-emitting driving current generated by the pixel circuit 10.
In an embodiment of the present application, please continue to refer to fig. 2, 3, 9 and 10, the pixel circuit 10 further includes a power voltage writing module 104 and a light emitting control module 105, wherein the input terminal 1041 of the power voltage writing module 104 is electrically connected to the power voltage signal line DY1, and the output terminal 1042 is electrically connected to the first pole of the driving transistor Md. The input terminal 1051 of the light emission control module 105 is electrically connected to the second pole of the driving transistor Md, and the output terminal 1052 is electrically connected to the first pole of the light emitting element 20.
Alternatively, as shown in fig. 3 and 10, the power supply voltage writing module 104 includes a fifth transistor M5, a first pole of the fifth transistor M5 is electrically connected to the power supply voltage signal line DY1, a second pole is electrically connected to a first pole of the driving transistor Md, and a gate is electrically connected to the light emission control signal line EM. The light emission control module 105 includes a sixth transistor M6, a first electrode of the sixth transistor M6 is electrically connected to a second electrode of the driving transistor Md, a second electrode is electrically connected to a first electrode of the light emitting element 20, and a gate electrode is electrically connected to the light emission control signal line EM.
In addition, as shown in fig. 3 and 10, the pixel circuit 10 further includes a second reset module 106, the input terminal 1061 of the second reset module 106 is electrically connected to the second reset line SL2, the output terminal 1062 is electrically connected to the first electrode of the light emitting element 20, and the second reset module 106 is configured to transmit the second reset voltage Vref2 on the second reset line SL2 to the first electrode of the light emitting element 20. The second reset module 106 may include a seventh transistor M7, a first electrode of the seventh transistor M7 being electrically connected to the second reset line SL2, a second electrode being electrically connected to the first electrode of the light emitting element 20, and a gate electrode being electrically connected to the second scan line SP 2.
For the sake of clarity of explanation of the technical solution of the present application, the operation of the pixel circuit 10 shown in fig. 10 is described below with reference to fig. 10 and 11.
The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are P-type transistors, and the third transistor M3 and the fourth transistor M4 are N-type transistors. Of course, any one of the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be an N-type transistor, and any one of the third transistor M3 and the fourth transistor M4 may be a P-type transistor.
In the reset phase E0 of the first phase T1, the fourth scan line SP4 transmits a high-level turn-on signal, and the fourth transistor M4 is turned on; the first scan line SP1, the second scan line SP2 and the emission control signal line EM all transmit a high-level off signal, and the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned off; the third scan line SP3 transmits a low-level off signal, and the third transistor M3 is turned off. Meanwhile, the first reset line SL1 transmits the first reset voltage Vref1, and the first reset voltage Vref1 is transmitted to the gate of the driving transistor Md through the turned-on fourth transistor M4, thereby completing the reset of the gate of the driving transistor Md.
In the data writing stage E1 of the first stage T1, the first scan line SP1 transmits a low-level turn-on signal, and the first transistor M1 is turned on; the third scan line SP3 transmits a high-level start signal, and the third transistor M3 is turned on; the second scan line SP2 and the emission control signal line EM each transmit a high-level off signal, and the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are each turned off; the fourth scan line SP4 transmits a low-level off signal, and the fourth transistor M4 is turned off. Meanwhile, the first sub-signal line DL11 transmits the data voltage Vdata, at the start point of the data writing stage E1, the gate potential of the driving transistor Md is the first reset voltage Vref1, the first electrode potential of the driving transistor Md is the data voltage Vdata, the potential difference between the first electrode and the gate of the driving transistor Md is (Vdata-Vref 1), and the potential difference between the two is greater than 0, so that the driving transistor Md is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the turned-on third transistor M3, such that the gate potential of the driving transistor Md is gradually increased. When the gate potential of the driving transistor Md is equal to (Vdata-vth|), the driving transistor Md is turned off. Where Vth is the threshold voltage of the driving transistor Md.
In the first adjustment stage E2 of the first stage T1, the second scan line SP2 transmits a low-level turn-on signal, and the second transistor M2 and the seventh transistor M7 are turned on; the first scan line SP1 and the emission control signal line EM both transmit a high-level off signal, and the first transistor M1, the fifth transistor M5, and the sixth transistor M6 are all turned off; the third scan line SP3 and the fourth scan line SP4 each transmit a low-level off signal, and the third transistor M3 and the fourth transistor M4 are each turned off. At this time, the second sub-signal line DL12 transmits the first adjustment voltage V1, and the first adjustment voltage V1 is transmitted to the first pole of the driving transistor Md through the turned-on second transistor M2, thereby adjusting the bias state of the driving transistor Md.
Meanwhile, the second reset line SL2 transmits the second reset voltage Vref2, and the second reset voltage Vref2 is transmitted to the first electrode of the light emitting element 20 through the turned-on seventh transistor M7, thereby completing the reset of the light emitting element 20. Alternatively, the light emitting element 20 includes an organic light emitting diode, and the second reset voltage Vref2 resets an anode of the organic light emitting diode through the turned-on sixth transistor M6.
In the first light emitting stage E3 of the first stage T1, the first scan line SP1 and the second scan line SP2 both transmit a high-level off signal, and the first transistor M1, the second transistor M2 and the seventh transistor M7 are all turned off; the third scan line SP3 and the fourth scan line SP4 each transmit a low-level off signal, and the third transistor M3 and the fourth transistor M4 are each turned off; the emission control signal line EM transmits a low-level on signal, and the fifth transistor M5 and the sixth transistor M6 are turned on, and at the same time, the power supply voltage signal line DY1 transmits the power supply voltage VDD, that is, the first polarity potential of the driving transistor Md is the power supply voltage VDD. Since the potential of the power supply voltage VDD is greater than the potential of the data voltage Vdata, the driving transistor Md generates a light emission driving current and transmits the light emission driving current to the light emitting element 20 through the sixth transistor M6, controlling the light emitting element 20 to emit light.
In a second adjustment stage E4 of the second stage T2, the second scan line SP2 transmits a low-level turn-on signal, and the second transistor M2 and the seventh transistor M7 are turned on; the first scan line SP1 and the emission control signal line EM both transmit a high-level off signal, and the first transistor M1, the fifth transistor M5, and the sixth transistor M6 are all turned off; the third scan line SP3 and the fourth scan line SP4 each transmit a low-level off signal, and the third transistor M3 and the fourth transistor M4 are each turned off. At this time, the second sub-signal line DL12 transmits the second adjustment voltage V2, and the second adjustment voltage V2 is transmitted to the first pole of the driving transistor Md through the turned-on second transistor M2, thereby further adjusting the bias state of the driving transistor Md. Meanwhile, the second reset voltage Vref2 transmitted by the second reset line SL2 may reset the light emitting element 20.
It should be noted that, in the second adjustment stage E4, although the second reset voltage Vref2 can be transmitted to the first electrode of the light emitting element 20 through the turned-on seventh transistor M7, the adjustment of the bias state of the driving transistor Md is not affected. The light emitting element 20 is reset once by the second reset voltage Vref2 before the first stage T1 and the second stage T2 start to emit light, which is beneficial to further reducing the difference of the light emitting brightness of the light emitting element 20 in the first stage T1 and the second stage T2.
The second light-emitting stage E5 of the second stage T2 is the same as the first light-emitting stage E3 of the first stage T1, and will not be described herein.
When the display panel 01 performs lower gray scale display, especially when the display brightness is below 0.5nit, the first voltage V1 and the second voltage V2 mainly play a role in resetting the first pole of the driving transistor Md during the first adjustment stage E2 of the first stage T1 and the second adjustment stage E4 of the second stage T2, so that the first pole potential of the driving transistor Md is the same at the starting time of the first light-emitting stage E3 and the starting time of the second light-emitting stage E5, thereby reducing the difference of the quantity of the light-emitting charges generated by the pixel circuit 10 after passing through the first pole of the driving transistor Md during the first light-emitting stage E3 and the second light-emitting stage E5, and further improving the flicker problem during lower gray scale display of the display panel 01.
Fig. 14 is a schematic view of brightness of a display panel in the related art.
In one embodiment of the present application, please continue to refer to fig. 11, the potential of the first regulated voltage V1 is greater than the potential of the second regulated voltage V2.
As can be seen from the operation of the pixel circuit 10, in the first stage T1, the signal transmitted by the third scan line SP3 is switched from high level to low level, so that the first electrode potential of the driving transistor Md is pulled down in a coupling manner, and in the second stage T2, the third scan line SP3 always transmits the high level signal, and no signal jump occurs, which results in that the potential of the first electrode of the driving transistor Md at the beginning of the first adjustment stage E2 is lower than the potential thereof at the beginning of the second adjustment stage E4, so that the luminance W1 of the display panel 01 in the first lighting stage E3 is lower than the luminance W2 thereof in the second lighting stage E5 when the display luminance of the display panel 01 is lower than 0.5nit, as shown in fig. 14.
In this embodiment, if the potential of the first adjustment voltage V1 is greater than the potential of the second adjustment voltage V2, the problem that the potential of the first pole of the driving transistor Md is lower at the start time of the first adjustment stage E2 caused by the jump of the signal transmitted by the third scan line can be compensated, which is favorable for improving the potential of the first pole of the driving transistor Md at the end time of the first adjustment stage E2, so as to be favorable for reducing the difference between the potential of the first pole of the driving transistor Md at the start time of the first light-emitting stage E3 and the potential at the start time of the second light-emitting stage E5, and further favorable for reducing the number difference of the light-emitting charges generated by the pixel circuit 10 in the first light-emitting stage E3 and the second light-emitting stage E5 after passing through the first pole of the driving transistor Md, reducing the brightness difference of the first stage T1 and the second stage T2 of the display panel 01 when the display panel 01 displays in low gray scale, and improving the flicker problem of the display panel 01.
It should be noted that, in some other embodiments, if the potential of the first pole of the driving transistor Md at the start of the first adjusting phase E2 is higher than the potential thereof at the start of the second adjusting phase E4, the potential of the first adjusting voltage V1 may be set to be smaller than the potential of the second adjusting voltage V2.
Fig. 15 is a timing diagram of the pixel circuit shown in fig. 10.
In one embodiment of the present application, as shown in fig. 12, 13 and 15, the first time period G1 is smaller than the second time period G2. I.e. the drain current time of the first pole potential of the driving transistor Md after the end of the first regulation phase E2 is smaller than the drain current time thereof after the end of the second regulation phase E4.
As can be seen from the operation of the pixel circuit 10, in the first stage T1, the signal transmitted by the third scan line SP3 is switched from high level to low level, so that the first electrode potential of the driving transistor Md is pulled down in a coupling manner, and in the second stage T2, the third scan line SP3 always transmits the high level signal, and no signal jump occurs, which results in that the potential of the first electrode of the driving transistor Md at the beginning of the first adjustment stage E2 is lower than the potential thereof at the beginning of the second adjustment stage E4, so that the luminance W1 of the display panel 01 in the first lighting stage E3 is lower than the luminance W2 thereof in the second lighting stage E5 when the display luminance of the display panel 01 is lower than 0.5nit, as shown in fig. 14.
In this embodiment of the present invention, if the first duration G1 is set to be less than the second duration G2, the leakage current time of the first pole potential of the driving transistor Md after the end of the first adjustment phase E2 is shorter, so that the problem that the potential of the first pole of the driving transistor Md at the starting time of the first adjustment phase E2 is lower due to the jump of the signal transmitted by the third scan line can be compensated, which is favorable for improving the potential of the first pole of the driving transistor Md at the starting time of the first light-emitting phase E3, thereby being favorable for reducing the difference between the potential of the first pole of the driving transistor Md at the starting time of the first light-emitting phase E3 and the potential at the starting time of the second light-emitting phase E5, and further being favorable for reducing the brightness difference between the first phase T1 and the second phase T2 when the display panel 01 is displayed in low gray scale, and improving the display effect.
It should be noted that, in some other embodiments, if the potential of the first pole of the driving transistor Md at the start of the first adjusting phase E2 is higher than the potential thereof at the start of the second adjusting phase E4, the first period G1 may be set to be longer than the second period G2.
Fig. 16 is a timing diagram of the pixel circuit shown in fig. 10.
In one embodiment of the present application, as shown in fig. 16, the potential of the first regulated voltage V1 may also be set to be greater than the potential of the second regulated voltage V2, and the first period of time G1 is less than the second period of time G2.
The embodiment of the application is beneficial to improving the setting flexibility of the first adjusting voltage V1, the second adjusting voltage V2, the first duration G1 and the second duration G2, and is beneficial to improving the preparation difficulty of the display panel 01 under the condition that the potential of the first electrode of the driving transistor Md at the starting moment of the first light-emitting stage E3 and the potential at the starting moment of the second light-emitting stage E5 tend to be consistent.
It should be noted that, in some other embodiments, if the potential of the first pole of the driving transistor Md at the start of the first adjustment phase E2 is higher than the potential thereof at the start of the second adjustment phase E4, the potential of the first adjustment voltage V1 may be set to be smaller than the potential of the second adjustment voltage V2, and the first period G1 is longer than the second period G2.
The embodiment of the application also provides a driving method of the display panel 01, which is used for driving the display panel 01 provided by the embodiment. The structure of the display panel 01 can be understood with reference to the operation of the pixel circuit 10 in the display panel 01 described above, as shown in fig. 1.
The driving method comprises the following steps:
step B1: in the first regulation stage E2, the data voltage writing module 101 transmits the first regulation voltage V1 to the first pole of the driving transistor Md.
Step B2: in the second regulation stage E4, the data voltage writing module 101 transmits the second regulation voltage V2 to the first pole of the driving transistor Md.
Wherein the first regulating voltage V1 and the second regulating voltage V2 are different in potential and/or the first duration G1 and the second duration G2 are different in magnitude.
In the embodiment of the present application, in the first adjustment stage E2 of the first stage T1, the first adjustment voltage V1 may correct the bias state of the driving transistor Md, so as to reduce the bias state difference of the driving transistor Md in the first stage T1 and the second stage T2. In the second adjusting stage E4 of the second stage T2, the second adjusting voltage V2 may further correct the bias state of the driving transistor Md, so as to further reduce the bias state difference of the driving transistor Md in the first stage T1 and the second stage T2, thereby being beneficial to reducing the ramp speed difference of the current received by the light emitting element 20 in the first stage T1 and the second stage T2, and further being beneficial to reducing the brightness difference of the display panel in the first stage T1 and the second stage T2.
In addition, considering that when the display panel 01 performs lower gray scale display, the main effect of the first adjusting voltage V1 and the second adjusting voltage V2 is to reset the electric potential of the first pole of the driving transistor Md, then the electric potentials of the first adjusting voltage V1 and the second adjusting voltage V2 are set to be different, and/or the electric potentials of the first pole of the driving transistor Md at the starting time of the first adjusting stage E2 and the electric potential difference at the starting time of the second adjusting stage E4 are different, the electric potentials of the first adjusting voltage V1 and the second adjusting voltage V2 and the electric potentials of the first pole of the driving transistor Md and the electric potential of the first pole of the second adjusting voltage V2 are flexibly set, so that the electric potentials of the first pole of the driving transistor Md at the starting time of the first light-emitting stage E3 and the starting time of the second light-emitting stage E5 are the same, which is beneficial to reducing the quantity of the light-emitting charges generated by the pixel circuit 10 at the first light-emitting stage E3 and the second light-emitting stage E5 after passing through the first pole of the driving transistor d is beneficial to reducing the amount of the first pole of the first light-emitting stage E3 and improving the first gray scale display effect of the first gray scale display panel, thereby being beneficial to improving the gray scale display 01, and further improving the difference display effect, and the gray scale display is beneficial to the low gray scale display, and the display panel is 1.
In one embodiment of the present application, the first regulated voltage V1 is different from the second regulated voltage V2 in potential, comprising:
the potential of the first regulated voltage V1 is greater than the potential of the second regulated voltage V2.
As can be seen from the above analysis, in the first phase T1, the signal transmitted by the third scan line SP3 is shifted from high level to low level, so that the first pole potential of the driving transistor Md is coupled to be pulled down, while in the second phase T2, the third scan line SP3 always transmits the high level signal, and no signal jump occurs, which results in the potential of the first pole of the driving transistor Md at the beginning of the first adjustment phase E2 being lower than the potential thereof at the beginning of the second adjustment phase E4.
In this embodiment, the potential of the first adjustment voltage V1 is set to be greater than the potential of the second adjustment voltage V2, so that the problem that the potential of the first pole of the driving transistor Md is lower at the starting time of the first adjustment stage E2 caused by the jump of the signal transmitted by the third scanning line can be compensated, which is favorable for improving the potential of the first pole of the driving transistor Md at the ending time of the first adjustment stage E2, thereby being favorable for reducing the difference between the potential of the first pole of the driving transistor Md at the starting time of the first light-emitting stage E3 and the potential at the starting time of the second light-emitting stage E5, and further being favorable for reducing the brightness difference between the first stage T1 and the second stage T2 when the display panel 01 is displayed in a low gray scale, improving the flicker problem of the display panel 01, and improving the display effect.
In one embodiment of the present application, the first time period G1 and the second time period G2 are different in size, including:
the first period G1 is smaller than the second period G2.
As can be seen from the above analysis, in the first phase T1, the signal transmitted by the third scan line SP3 is shifted from high level to low level, so that the first pole potential of the driving transistor Md is coupled to be pulled down, while in the second phase T2, the third scan line SP3 always transmits the high level signal, and no signal jump occurs, which results in the potential of the first pole of the driving transistor Md at the beginning of the first adjustment phase E2 being lower than the potential thereof at the beginning of the second adjustment phase E4.
In this embodiment of the present invention, if the first duration G1 is set to be less than the second duration G2, the leakage current time of the first pole potential of the driving transistor Md after the end of the first adjustment phase E2 is shorter, so that the problem that the potential of the first pole of the driving transistor Md at the starting time of the first adjustment phase E2 is lower due to the jump of the signal transmitted by the third scan line can be compensated, which is favorable for improving the potential of the first pole of the driving transistor Md at the starting time of the first light-emitting phase E3, thereby being favorable for reducing the difference between the potential of the first pole of the driving transistor Md at the starting time of the first light-emitting phase E3 and the potential at the starting time of the second light-emitting phase E5, and further being favorable for reducing the brightness difference between the first phase T1 and the second phase T2 when the display panel 01 is displayed in low gray scale, and improving the display effect.
Fig. 17 is a schematic diagram of a display device according to an embodiment of the present application.
The embodiment of the present application provides a display device 02, as shown in fig. 17, where the display device 02 includes the display panel 01 provided in the above embodiment. The display device 02 provided in the embodiments of the present application may be an electronic device such as a mobile phone, a computer, a television, or a wearable electronic device. The present application is not particularly limited.
In the display device 02, in the first adjustment stage E2 of the first stage T1, the first adjustment voltage V1 can correct the bias state of the driving transistor Md, reducing the bias state difference of the driving transistor Md in the first stage T1 and the second stage T2. In the second adjusting stage E4 of the second stage T2, the second adjusting voltage V2 may further correct the bias state of the driving transistor Md, so as to further reduce the bias state difference of the driving transistor Md in the first stage T1 and the second stage T2, thereby being beneficial to reducing the ramp speed difference of the current received by the light emitting element 20 in the first stage T1 and the second stage T2, and further being beneficial to reducing the brightness difference of the display panel in the first stage T1 and the second stage T2.
In addition, considering that when the display panel 01 performs lower gray scale display, the main effect of the first adjusting voltage V1 and the second adjusting voltage V2 is to reset the electric potential of the first pole of the driving transistor Md, then the electric potentials of the first adjusting voltage V1 and the second adjusting voltage V2 are set to be different, and/or the electric potentials of the first pole of the driving transistor Md at the starting time of the first adjusting stage E2 and the electric potential difference at the starting time of the second adjusting stage E4 are different, the electric potentials of the first adjusting voltage V1 and the second adjusting voltage V2 and the electric potentials of the first pole of the driving transistor Md and the electric potential of the first pole of the second adjusting voltage V2 are flexibly set, so that the electric potentials of the first pole of the driving transistor Md at the starting time of the first light-emitting stage E3 and the starting time of the second light-emitting stage E5 are the same, which is beneficial to reducing the quantity of the light-emitting charges generated by the pixel circuit 10 at the first light-emitting stage E3 and the second light-emitting stage E5 after passing through the first pole of the driving transistor d is beneficial to reducing the amount of the first pole of the first light-emitting stage E3 and improving the first gray scale display effect of the first gray scale display panel, thereby being beneficial to improving the gray scale display 01, and further improving the difference display effect, and the gray scale display is beneficial to the low gray scale display, and the display panel is 1.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (16)
1. A display panel, the display panel comprising a plurality of pixel circuits, the pixel circuits comprising:
a driving transistor for generating a light emission driving current;
the input end of the data voltage writing module is electrically connected with the first signal line, and the output end of the data voltage writing module is electrically connected with the first pole of the driving transistor;
one duty cycle of the pixel circuit includes a first phase and a second phase performed after the first phase; the first phase comprises a data writing phase, a first adjusting phase and a first light-emitting phase which are sequentially carried out, and the duration between the first adjusting phase and the first light-emitting phase is a first duration; the second stage comprises a second adjusting stage and a second light-emitting stage which are sequentially carried out, and the time length between the second adjusting stage and the second light-emitting stage is a second time length;
in the first regulation phase, the data voltage writing module transmits a first regulation voltage to a first pole of the driving transistor; in the second regulation phase, the data voltage writing module transmits a second regulation voltage to the first pole of the driving transistor;
Wherein the first regulated voltage is different from the second regulated voltage in potential and/or the first duration is different from the second duration in magnitude.
2. The display panel according to claim 1, wherein a potential of the first adjustment voltage is greater than a potential of the second adjustment voltage.
3. The display panel of claim 1, wherein the first time period is less than the second time period.
4. The display panel according to claim 1, wherein the first stage comprises n1 of the first adjustment stages, the second stage comprises n2 of the second adjustment stages, n1 is greater than or equal to 1, n2 is greater than or equal to 1;
the first duration is the duration between the first adjusting phase and the first lighting phase, which are finally performed according to time sequence in the n1 first adjusting phases;
the second duration is a duration between the second adjustment phase and the second light-emitting phase, which are last performed according to time sequence in the n2 second adjustment phases.
5. The display panel according to claim 1, wherein the data voltage writing module includes a first transistor having a first pole electrically connected to the first signal line and a second pole electrically connected to the first pole of the driving transistor;
In the data writing stage, the first transistor is turned on, and the first signal line transmits a data voltage; in the first regulation stage, the first transistor is turned on, and the first signal line transmits a first regulation voltage; in the second regulation phase, the first transistor is turned on and the first signal line transmits a second regulation voltage.
6. The display panel of claim 1, wherein the first signal line includes a first sub signal line and a second sub signal line, and the data voltage writing module includes a first transistor and a second transistor; the first electrode of the first transistor is electrically connected with the first sub-signal line, the second electrode of the first transistor is electrically connected with the first electrode of the driving transistor, and the first electrode of the second transistor is electrically connected with the second sub-signal line, and the second electrode of the second transistor is electrically connected with the first electrode of the driving transistor;
in the data writing stage, the first transistor is turned on, the second transistor is turned off, and the first sub-signal line transmits a data voltage;
in the first regulation stage and the second regulation stage, the first transistor is turned off, the second transistor is turned on, and the second sub-signal line transmits the first regulation voltage in the first regulation stage and the second regulation voltage in the second regulation stage.
7. The display panel of claim 1, wherein the pixel circuit further comprises a threshold voltage grasping module having an input electrically connected to the second pole of the drive transistor and an output electrically connected to the gate of the drive transistor;
in the data writing stage, the threshold voltage grabbing module is started; the threshold voltage grabbing module is turned off during the first and second regulation phases.
8. The display panel of claim 7, wherein the threshold voltage grabbing module comprises a third transistor, a first pole of the third transistor being electrically connected to a second pole of the driving transistor, the second pole being electrically connected to a gate of the driving transistor.
9. The display panel of claim 8, wherein the third transistor comprises a metal oxide active layer.
10. The display panel of claim 7, wherein the pixel circuit further comprises a first reset module having an input electrically connected to a first reset line and an output electrically connected to a gate of the drive transistor;
The first phase further includes a reset phase, which is performed before the data writing phase;
in the reset stage, the first reset module is turned on, and the first reset line transmits a first reset voltage;
the first reset module is turned off during the data writing phase, the first conditioning phase and the second conditioning phase.
11. The display panel of claim 10, wherein the first reset module comprises a fourth transistor having a first pole electrically connected to the first reset line and a second pole electrically connected to the gate of the drive transistor.
12. The display panel of claim 11, wherein the fourth transistor comprises a metal oxide active layer.
13. A driving method of a display panel, characterized by being used for driving the display panel according to any one of claims 1-12; the driving method includes:
in the first regulation phase, the data voltage writing module transmits a first regulation voltage to a first pole of the driving transistor;
in the second regulation phase, the data voltage writing module transmits a second regulation voltage to the first pole of the driving transistor;
Wherein the first regulated voltage is different in magnitude from the second regulated voltage, and/or the first duration is different in magnitude from the second duration.
14. The driving method according to claim 13, wherein the first regulation voltage is different in magnitude from the second regulation voltage, comprising:
the potential of the first regulating voltage is greater than the potential of the second regulating voltage.
15. The driving method according to claim 13, wherein the first time period is different in size from the second time period, comprising:
the first time period is less than the second time period.
16. A display device comprising a display panel according to any one of claims 1-12.
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