KR20090104721A - Display apparatus - Google Patents

Abstract

PURPOSE: A display device is provided to suppress brightness change due to the characteristic deviation of a driving transistor or electro-optic device. CONSTITUTION: A driving transistor(121) generates a driving current. An electro-optic device is connected to an output terminal of the driving transistor. A vertical scan unit generates a vertical scan pulse for scanning a pixel circuit vertically. A plurality of vertical scan lines are connected to the vertical scan unit. A horizontal scan unit supplies the image signal to the pixel circuit by synchronizing with the vertical scan. A plurality of horizontal scan lines are connected to the horizontal scan unit. A record scan unit(104) generates a record scan pulse for recording the information by the signal amplitude in the storage capacity(120). A plurality of record scan lines are connected to the record scan unit. The image signal is supplied from the horizontal scan unit to an input terminal of a first sampling transistor(125). A control input terminal of a second sampling transistor is connected to the vertical scan line.

Description

Display device {DISPLAY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device including a plurality of pixel circuits or pixels including an electro-optical element functioning as a display element or a light emitting element. More specifically, the current driving in which the luminance varies with the magnitude of the drive signal The present invention relates to a display device including a display element formed by an electro-optical element of a type and a plurality of pixel circuits each including an active element for performing display driving on a pixel basis.

BACKGROUND ART As a display element of a pixel, there is a display device using an electro-optical element whose luminance is changed by a voltage applied or a flowing current. For example, a liquid crystal display element is a representative example of an electro-optical element whose luminance changes due to an applied voltage, and an organic electroluminescence (hereinafter referred to as organic) is an electro-optical element whose luminance changes due to a flowing current. An abbreviation is EL). An organic EL display device using the latter organic EL element is a so-called self-luminous display device using an electro-optical element that is a self-luminous element as a display element of a pixel.

The organic EL element is formed by providing an organic thin film (organic layer) formed by stacking an organic hole transport layer or an organic light emitting layer between a lower electrode and an upper electrode, and utilizes a phenomenon of emitting light when an electric field is applied to the organic thin film, and flows through the organic EL element. The color tone is obtained by controlling the current value.

In an organic EL display device using a current-driven element such as an organic EL element as an electro-optical element, a drive signal (voltage signal) in response to an input image signal received in a storage capacitor is converted from a drive transistor to a current signal, The driving current is supplied to the organic EL element.

For example, in order for the luminescence brightness of an organic EL element to be unchanged, it is important to make the drive current consistent with the input image signal constant.

However, the threshold voltage and the mobility of the active element (drive transistor) for driving the electro-optical element are disturbed by the process variation. In addition, the characteristics of electro-optical elements such as organic EL elements fluctuate over time. If there is such a characteristic variation of the active element for driving or the characteristic variation of the electro-optical element, even the constant current driving method will affect the light emission luminance.

For this reason, in order to uniformly control the luminescence brightness over the entire screen of the display device, various structures for correcting the luminance fluctuations caused by the characteristic fluctuations of the driving active element or the electro-optical element described above in each pixel circuit are various. It is considered.

For example, Japanese Patent Laid-Open No. 2006-215213 (hereinafter referred to as Patent Document 1) discloses a pixel circuit for an organic EL element employing the above-described structure. This pixel circuit has a threshold correction function for keeping the drive current constant even when there is a deviation or change over time in the threshold voltage of the drive transistor, or a constant drive current even when there is a deviation or change over time in the mobility of the drive transistor. A mobility correction function for carrying out this function and a bootstrap function for keeping the driving current constant even when there is a change over time in the current-voltage characteristics of the organic EL element are provided.

On the other hand, when cost reduction is taken into consideration, it is conceivable to reduce the number of scanning lines drawn from various scanning circuits provided in the periphery of the pixel array portion without reducing the number of pixels. In this case, a plurality of pixels are assigned to one horizontal scan line or a plurality of rows are assigned to one vertical scan line, so that the scan signal output from the scanning circuit is shared by the plurality of pixels.

By reducing the number of scan lines wired in the pixel array unit, the cost can be reduced by the circuit cost for driving each scan line. At this time, it is conceivable to employ a structure in which the number of the extraction wirings is reduced without reducing the number of pixels proposed in the liquid crystal display device. For example, when attention is paid to the horizontal scanning side, it is conceivable to adopt a structure in which the cost can be reduced by sharing the signal line with a plurality of pixels. Such a structure is disclosed, for example, in Japanese Patent Laid-Open No. 2006-215322 (hereinafter referred to as Patent Document 2).

The structure described in Patent Literature 2 is a system in which signal lines are shared by adjacent pixels, and two video signals are input to one pixel to rewrite the video signal.

However, the structure described in Patent Literature 2 cannot be employed in a structure that performs mobility correction by performing signal recording while flowing a current. When the video signal voltage is input to the gate of the driving transistor two or more times, the mobility correction is performed on the first video signal, and the mobility correction operation is normally performed on the video signal input to the gate of the driving transistor after the second time. This can't be done.

In addition, in the structure described in Patent Literature 1, wiring for supplying a potential for correction, a switching transistor for correction, and a switching pulse for driving the switching transistor are required. The configuration of the 5TR drive that uses is adopted. Therefore, the configuration of the pixel circuit is complicated, such as a large number of vertical scan lines. Since there are many components of the pixel circuit, it becomes an obstacle of high precision of a display apparatus. As a result, due to the configuration of the 5TR drive, it is difficult to apply to display devices used in small electronic devices such as mobile devices.

Therefore, it is necessary to provide a display device that can share a video signal line or a video signal in a plurality of pixels (that is, a plurality of columns) without increasing the number of control lines or control signals, paying attention to the horizontal scanning system.

In addition, it is necessary to provide a display device that enables high precision of the display device by simplifying the pixel circuit. Further, the pixel circuit can be simplified while suppressing the luminance variation caused by the characteristic variation of the driving transistor or the electro-optical element. There is a need to provide a display device that can.

According to an exemplary embodiment of the present invention, a display device including a pixel array unit in which a plurality of pixel circuits are arranged in a matrix form in order to share an image signal line, which is an example of a horizontal scanning line, in a plurality of pixels (ie, a plurality of columns) is provided. In the pixel circuit, the electro-optical element generates a drive current based on the information stored in the storage capacitor by the drive transistor, and causes the drive current to flow through the electro-optical element to emit light. The pixel array unit includes a driving transistor for generating a driving current, an electro-optical element connected to an output terminal of the driving transistor, a storage capacitor for storing information according to the signal amplitude of the image signal, and a slave connection for recording information according to the signal amplitude in the storage capacitor. A first sampling transistor and a second sampling transistor. The pixel array unit may further include a vertical scanning unit for generating a vertical scanning pulse for vertically scanning the pixel circuit, and a pixel circuit (particularly, the first sampling transistor and the second sampling) in synchronization with the vertical scanning by the vertical scanning unit. A horizontal scanning unit for providing an image signal to a transistor), and a plurality of horizontal scanning lines connected to the horizontal scanning unit. The vertical scanning unit includes a write scanning unit for vertically scanning at least the pixel circuit to generate a write scanning pulse for recording information according to the signal amplitude in the storage capacitor, and the vertical scanning line includes a plurality of write scanning lines connected to the write scanning unit. . Each of the horizontal scanning lines is wired so that a video signal for signal writing from the horizontal scanning unit is commonly provided to the input terminal of the first sampling transistor included in the plurality of columns. The control input terminal of the second sampling transistor belonging to each of the groups each including a plurality of columns to which the video signal is commonly supplied is used for vertical scanning of different rows of groups other than the group to which the second sampling transistor belongs. A pulse is connected to the vertical scan line so that a pulse is supplied to the control input terminal of the second sampling transistor in the vertical scan portion.

That is, in order to share a video signal line or a video signal which is a scanning line of a horizontal scanning system in a plurality of columns, the sampling transistor is formed in a double gate configuration including a transistor connected in two stages. The video signal lines of a plurality of columns of the shared object are commonly connected to the signal input terminal of the sampling transistor of the double gate configuration on the video signal line side.

On the other hand, the second sampling transistor belongs to its own row so that the video signal is supplied to the control input terminal of the driving transistor in synchronism with the normal vertical scanning for each row by the combination of the first and second sampling transistors. It is connected to the same or different vertical scan lines of different rows of the other groups except the shared group. In this regard, "heterogeneous" does not mean that all of the vertical scanning lines connected to the control input terminal of the second sampling transistor in the tank are heterogeneous, and that the control input terminal of each second sampling transistor in the tank is different. Means that it is connected with at least two types of vertical scanning lines.

In the display device, the sampling transistor has a double gate structure, and the signal input terminal of the sampling transistor of the debate structure is commonly connected to the common video signal line so that one video signal line is commonly used by a plurality of column pixel circuits. On the other hand, as the vertical scanning line for controlling the second sampling transistor, as the existing vertical scanning line, the same or different vertical scanning lines of different rows of different groups except for the shared group to which the own row belongs are allocated.

Therefore, the cost can be reduced by sharing the video signal supplied to the pixel circuit via the video signal line or the video signal line in a plurality of columns without increasing the number of control lines or control signals.

<Overview of display device>

1 shows a general configuration of an active matrix display device which is one embodiment of a display device according to the present invention. In the present embodiment, the display device is applied to an active matrix organic electroluminescence (EL) display device (hereinafter, abbreviated as "organic EL display device"). In the organic EL display device, the organic EL element is used as a display element, an electro-optical element or a light emitting element of each pixel, and a polysilicon thin film transistor (TFT) is used as an active element of each pixel. In addition, the organic EL element is formed on a semiconductor substrate on which a thin film transistor is formed. Such an organic EL display device described above is utilized as a display portion in some other electronic device or portable music player utilizing a recording medium such as a semiconductor memory, a mini disc (MD) or a cassette tape.

As shown in FIG. 1, the organic EL display device 1 has an aspect ratio in which a pixel circuit (also referred to as a pixel) P having an organic EL element (not shown) as a plurality of display elements has a display aspect ratio X: The drive signal which is an example of the display panel part 100 arrange | positioned so that the effective image area | region of Y (for example, 9:16), and the panel control part which generate | occur | produces various pulse signals which drive-control this display panel part 100 are shown. The generation unit 200 and the video signal processing unit 300 are provided. The drive signal generator 200 and the video signal processor 300 are embedded in a single chip integrated circuit (IC).

For example, when the organic EL display device is formed of a panel type display device, the pixel array unit 102 and the pixel array unit 102 in which elements constituting pixel circuits such as TFTs and electro-optical elements are arranged in a matrix form; ), The control unit 109 having a scanning unit (horizontal driving unit or vertical driving unit) as a main unit, arranged around the scanning line for driving each pixel circuit P, and various kinds of operations for operating the control unit 109. It is common to include a driving signal generator 200 or an image signal processor 300 for generating a signal to form the whole apparatus.

The display panel unit 100 includes a pixel array unit 102 in which pixel circuits P are arranged in a matrix of n rows by m columns, and a vertical driving unit that is an example of a vertical scanning unit that scans the pixel circuits P in a vertical direction. The 103, the horizontal driver 106, which is an example of the horizontal scanning unit for scanning the pixel circuit P in the horizontal direction, and the terminal portion or the pad portion 108 for external connection are formed in an integrated form. The horizontal driver 106 is also called a horizontal selector or data line driver. That is, peripheral drive circuits such as the vertical drive unit 103 and the horizontal drive unit 106 are formed on the substrate 101 on which the pixel array unit 102 is formed.

In the vertical drive unit 103, for example, a write scan unit (Write Scan WS) 104 or a drive scan unit (Drive Scan (DS) which functions as a power scanner having a power supply capability). Have 105. The vertical drive unit 103 and the horizontal drive unit 106 constitute a control unit 109 for controlling the recording of the signal potential into the storage capacitance, the threshold correction operation, the mobility correction operation, and the bootstrap operation.

Various pulse signals are supplied to the terminal portion 108 from the drive signal generator 200 disposed outside the organic EL display device 1. Similarly, the video signal Vsig is supplied from the video signal processor 300. In the case of the color display correspondence, the video signals Vsig_R, G, and B of three different colors (R (red), G (green), and B (blue) in this example) are supplied.

As an example, as pulse signals for vertical driving, necessary pulse signals such as shift start pulses SPDS and SPWS, vertical scan clocks CKDS and CKWS, which are examples of recording start pulses in the vertical direction, are supplied. As a pulse signal for horizontal driving, necessary pulse signals such as a horizontal start pulse SPH and a horizontal scan clock CKH, which are examples of recording start pulses in the horizontal direction, are supplied.

In the pixel array unit 102, each scanning line (vertical scanning line: write scanning line 104WS and power supply line 105DSL) on the vertical scanning side and an image signal line (data line) 106HS which is a scanning line (horizontal scanning line) on the horizontal scanning side Is formed. An organic EL element (not shown) and a thin film transistor (TFT) driving the same are formed at the intersection portion of each scan line in the vertical scan and the horizontal scan. The pixel circuit P is constituted by a combination of an organic EL element and a thin film transistor.

Specifically, for each pixel circuit P arranged in a matrix form, n scan rows 104WS_1 to 104WS_n and a drive scan unit (for n rows driven by the write drive pulse WS by the write scan unit 104). N rows of power supply lines 105DSL_1 to 105DSL_n driven by the power supply driving pulse DSL are wired for each pixel row.

The write scan unit 104 and the drive scan unit 105 each pixel circuit through the write scan line 104WS and the power supply line 105DSL based on the pulse signal of the vertical drive system supplied from the drive signal generator 200. Select (P) sequentially. The horizontal driver 106 applies a predetermined potential in the video signal Vsig to the selected pixel circuit P through the video signal line 106HS based on the pulse signal of the horizontal drive system supplied from the drive signal generator 200. Sampled and recorded in storage capacity.

In the organic EL display device 1 of the present embodiment, linear sequential driving, surface sequential driving, or other driving can be performed. For example, the recording scanning unit of the vertical driving unit 103 can be used. The 104 and the driving scanning unit 105 scan the pixel array unit 102 in units of rows, and in parallel with this, the horizontal driving unit 106 simultaneously outputs an image signal for one horizontal line. Record at 102.

The horizontal driver 106 includes, for example, a driver circuit that turns on a switch (not shown) provided on all the video signal lines 106HS in a row, and includes pixels input from the video signal processor 300. In order to simultaneously record the signals to all the pixel circuits P for one line of the row selected by the vertical driver 103, all the switches provided on the video signal lines 106HS of all the columns are turned on at the same time, and the driver The video signal Vsig (an example of a horizontal scanning signal) is supplied to the horizontal scanning line (image signal line 106HS) via the circuit.

Each portion of the vertical driver 103 is constituted by a combination of logic gates (including latches) and a driver circuit, and the pixel gates select each pixel circuit P of the pixel array unit 102 by a logic gate. The vertical scan signal is supplied to the vertical scan line via the driver circuit. In addition, although the structure which arrange | positions the vertical drive part 103 only to one side of the pixel array part 102 is shown in FIG. 1, the structure which sandwiches the pixel array part 102 and arrange | positions the vertical drive part 103 to both left and right sides is shown. May be adopted. Similarly, although FIG. 1 shows the structure which arrange | positions the horizontal drive part 106 only to one side of the pixel array part 102, the structure which arrange | positions the pixel drive part 102 and arranges the horizontal drive part 106 on both sides of upper and lower sides. May be adopted.

These vertical driving units 103 (write scanning unit 104 and driving scanning unit 105), horizontal driving unit 106, vertical scanning lines (writing scanning line 104WS and power supply line 105DSL), and horizontal scanning lines (image signal lines ( As can be seen from the connection mode of 106HS), scanning lines are required to supply the scanning signals to the pixel circuits P of the pixel array unit 102, and in a simple structure, the number of the pixel circuits P increases. When the number of scanning lines is reduced, the number of scanning lines increases accordingly, and the driver circuit for driving the scanning lines also increases. In Fig. 1, the scan lines are arranged for each row or column for convenience, but the structure of the present embodiment described later adopts a structure in which the number of scan lines (particularly the video signal lines 106HS) is reduced while maintaining the number of pixels. .

<Pixel Circuit of Comparative Example: First Example>

As shown in FIG. 2, the pixel circuit P of the first comparative example is basically characterized in that a drive transistor is composed of a p-type thin film field effect transistor TFT. In addition to the dove transistor, a configuration of 3Tr driving using two transistors for scanning is adopted.

Specifically, the pixel circuit P of the first comparative example includes the p-type driving transistor 121, the p-type light emission control transistor 122 to which the driving pulse of the active L is supplied, and the active-H driving pulse. N-type transistor 125 to be supplied, an organic EL element 127 which is an example of an electro-optical element (light emitting element) that emits light as a current flows, and a storage capacitor (also referred to as a pixel capacitance) 120. In addition, as the simplest circuit, a configuration of 2Tr driving in which the light emission control transistor 122 is removed may be adopted. In this case, the organic EL display device 1 adopts a configuration in which the driving scan unit 105 is removed.

The driving transistor 121 is configured to supply the driving current corresponding to the potential supplied to the gate terminal serving as the control input terminal to the organic EL element 127. In general, the organic EL element 127 is represented by a symbol of a diode because of its rectifying property. In addition, the parasitic capacitance Cel exists in the organic EL element 127. In the figure, the parasitic capacitance Cel is shown in parallel with the organic EL element 127.

The sampling transistor 125 is a switching transistor provided on the gate terminal (control input terminal) side of the driving transistor 121, and the light emission control transistor 122 is also a switching transistor. In general, the sampling transistor 125 may be replaced with a p-type to which a driving pulse of the active (L) is supplied. The emission control transistor 122 may be replaced with an n-type supplied with an active-H driving pulse.

The pixel circuit P is disposed at the intersection of each of the scanning lines 104WS and 105DS on the vertical scanning side and the video signal line 106HS which is the scanning line on the horizontal scanning side. The write scan line 104WS from the write scan unit 104 is connected to the gate end of the sampling transistor 125, and the drive scan line 105DS from the drive scan unit 105 is connected to the gate end of the light emission control transistor 122. Is connected to.

The sampling transistor 125 is connected to the video signal line 106HS as the source terminal S as the signal input terminal, and to the gate terminal G of the driving transistor 121 as the drain terminal D as the signal output terminal. The storage capacitor 120 is provided between the connection point and the second power source potential Vc2 (for example, may be the same as the electrostatic source voltage or the first power source potential Vc1). As shown in parentheses, the sampling transistor 125 reverses the source terminal S and the drain terminal D, connects the drain terminal D to the video signal line 106HS as a signal input terminal, and connects the source terminal ( S may be connected to the gate terminal G of the driving transistor 121 as a signal output terminal.

The driving transistor 121, the light emission control transistor 122, and the organic EL element 127 are disposed between the first power source potential Vc1 (for example, the electrostatic source voltage) and the ground potential GND, which is an example of the reference potential. Are connected in series in this order. Specifically, in the driving transistor 121, the source terminal S is connected to the first power supply potential Vc1, and the drain terminal D is connected to the source terminal S of the light emission control transistor 122. . The drain terminal D of the light emission control transistor 122 is connected to the anode terminal A of the organic EL element 127, and the cathode terminal K of the organic EL element 127 is the cathode common wiring common to all pixels. It is connected to 127K. As an example, the cathode common wiring 127K becomes the ground potential GND, and in this case, the cathode potential Vcath also becomes the ground potential GND.

In either the 3Tr drive shown in FIG. 2 or the 2Tr drive not shown, since the organic EL element 127 is a current light emitting element, the color tone is obtained by controlling the amount of current flowing through the organic EL element 127. To this end, the current value flowing through the organic EL element 127 is changed by changing the voltage applied to the gate terminal of the driving transistor 121 and changing the gate-source voltage Vgs stored in the storage capacitor 120. Control At this time, the potential (video signal line potential) of the video signal Vsig supplied from the video signal line 106HS is set as the signal potential. In addition, the signal amplitude which shows gray scale is set to (DELTA) Vin.

N-type is supplied by supplying the active-H write drive pulse WS from the write scan unit 104 to put the write scan line 104WS in the selected state, and applying a signal potential from the horizontal drive unit 106 to the video signal line 106HS. The transistor 125 is turned on, the signal potential becomes the potential of the gate terminal of the driving transistor 121, and information corresponding to the signal amplitude ΔVin is written in the storage capacitor 120. The current flowing through the driving transistor 121 and the organic EL element 127 becomes a value corresponding to the gate-source voltage Vgs of the driving transistor 121 stored in the storage capacitor 120, and the organic EL element ( 127 continues to emit light at a luminance corresponding to the current value. The operation of selecting the write scan line 104WS and transmitting the video signal Vsig given to the video signal line 106HS into the pixel circuit P is called "write" or "sampling". Once the signal is recorded, the organic EL element 127 continues to emit light at a constant luminance until it is next rewritten.

In the pixel circuit P of the first comparative example, the current value flowing through the EL organic EL element 127 is controlled by changing the applied voltage supplied to the gate terminal of the driving transistor 121 in response to the signal amplitude DELTA Vin. At this time, the source terminal of the p-type driving transistor 121 is connected to the first power source potential Vc1, and the driving transistor 121 is always operating in the saturation region.

<Pixel Circuit of Comparative Example: Second Example>

Next, the pixel circuit P of the second embodiment shown in FIG. 3 will be described. Referring to Fig. 3, the pixel circuit P of the second comparative example is characterized in that the drive transistor is basically composed of an n-type thin film field effect transistor (the same applies to the embodiment of the present invention described later). If each transistor can be configured by n type instead of p type, it is possible to use a conventional amorphous silicon (a-Si) process in producing a transistor. As a result, the transistor substrate can be reduced in cost, and the development of the pixel circuit P having such a configuration is expected.

The pixel circuit P of the second comparative example is basically the same as the present embodiment described later in that the drive transistor is composed of an n-type thin film field effect transistor, but the organic EL element 127 and the driving transistor 121 A drive signal constant circuit is not provided to prevent the influence on the drive current Ids due to characteristic variations (deviation or change over time).

Specifically, the pixel circuit P of the second comparative example simply replaces the p-type driving transistor 121 in the pixel circuit P of the first comparative example with the n-type driving transistor 121, and The light emission control transistor 122 and the organic EL element 127 are disposed on the source end side. The light emission control transistor 122 is also replaced with an n type. Of course, as the simplest circuit, a configuration of 2Tr driving in which the light emission control transistor 122 is removed may be adopted.

In the pixel circuit P of the second comparative example, regardless of whether or not a light emission control transistor is provided, when driving the organic EL element 127, the drain end side of the driving transistor 121 is the first power source potential Vc1. The source terminal is connected to the anode end side of the organic EL element 127 to form a source follower circuit as a whole.

<Relationship of Iel-Vel Characteristics of Electro-optical Device>

In general, as shown in FIG. 4A, the driving transistor 121 is driven in a saturation region where the driving current Ids is constant regardless of the voltage between the drain and the source. Therefore, the current flowing between the drain terminal and the source of the transistor operating in the saturation region is Ids, the mobility is μ, the channel width (gate width) W, the channel length (gate length) L, the gate capacitance (gate per unit area). When the oxide film capacitance is set to Cox and the threshold voltage of the transistor is Vth, the driving transistor 121 is a constant current source having the value indicated by the following equation (1). In addition, "＾" represents power. As is apparent from equation (1), in the saturation region, the drain current Ids of the transistor is controlled by the gate-source voltage Vgs and operates as a constant current source.

By the way, generally, the I-V characteristic of the current-driven light emitting element including the organic EL element changes as time passes. In the current-voltage (Iel-Vel) characteristics of the current-driven light emitting element represented by the organic EL element shown in Fig. 4B, the curve shown by the solid line shows the characteristic at the initial state, and the curve shown by the broken line is shown. The characteristic after a change with time is shown.

For example, when the luminous current Iel flows through the organic EL element 127 which is one example of the luminous means, the first power source potential Vel is determined uniformly. By the way, as shown in FIG. 4B, during the light emission period, the light emission current Iel determined by the drive current Ids of the drive transistor 121 flows to the anode end of the organic EL element 127, whereby the organic EL The anode-cathode voltage (Vel) of the device 127 rises by a minute.

In the pixel circuit P of the first comparative example shown in FIG. 2, the influence of the rise of the voltage between the anode and the cathode of the organic EL element 127 is shown on the drain end side of the driving transistor 121, but driving is performed. Since the transistor 121 is a constant current driving operating in the saturation region, the constant current Ids continues to flow through the organic EL element 127, and its luminescence brightness is maintained over time even if the Iel-Vel characteristic of the organic EL element 127 changes. Nothing changes.

Referring to FIG. 3, the pixel circuit P of the second comparative example includes a driving transistor 121, a light emission control transistor 122, a storage capacitor 120, and a sampling transistor 125. In the configuration of the pixel circuit P in the connected state shown in Fig. 1, a drive signal constant circuit for correcting a change in the current-voltage characteristic of the organic EL element 127, which is an example of an electro-optic element, to keep the drive current constant Is to be configured. That is, when driving the pixel circuit P with the image signal Vsig, the source terminal of the p-type driving transistor 121 is connected to the first power source potential Vc1 and is designed to always operate in the saturation region. Therefore, it functions as a constant current source for supplying a current having a value defined by the above expression (1).

In the pixel circuit P of the first comparative example, the voltage at the drain terminal of the driving transistor 121 changes while the Iel-Vel characteristic of the organic EL element 127 changes with time (FIG. 4B). Since the gate-source voltage Vgs is kept constant in principle by the bootstrap function of the storage capacitor 120, the transistor 121 operates as a constant current source, and as a result, A certain amount of current flows through the organic EL element 127, and the organic EL element 127 can emit light at a constant luminance, and the emission luminance does not change.

Also in the pixel circuit P of the second comparative example, the potential (source potential Vs) of the source terminal of the driving transistor 121 is determined at the operating point of the driving transistor 121 and the organic EL element 127, and driving is performed. Since the transistor 121 is driven in the saturation region, the drive current Ids of the current value defined in the above formula (1) flows with respect to the gate-source voltage Vgs corresponding to the source voltage of the operating point.

By the way, in a simple circuit in which the p-type driving transistor 121 of the pixel circuit P of the first comparative example is changed to n-type (pixel circuit P of the second comparative example), the source terminal is the organic EL element 127. Is connected to the As a result, the anode-cathode voltage Vel for the same emission current Iel is changed from Vel1 to Vel2 by the Iel-Vel characteristic of the organic EL element 127 that changes over time as shown in FIG. 4B. Since the operating point of the driving transistor 121 changes, the source potential Vs of the driving transistor 121 changes even when the same gate potential Vg is applied. As a result, the gate-source voltage Vgs of the driving transistor 121 changes. As apparent from Equation (1), when the gate-source voltage Vgs fluctuates, for example, the drive current Ids fluctuates even if the gate potential Vg is constant. The fluctuation in the drive current Ids due to this cause is caused by the variation in the luminance of the light emission for each pixel circuit P or the variation over time.

On the other hand, although the details will be described later, even when the n-type driving transistor 121 is used, a boot that causes the potential Vg of the gate terminal to cooperate with the variation of the potential Vs of the source terminal of the driving transistor 121. By adapting to the circuit configuration and the driving timing to realize the strap function, the anode potential variation (i.e., the source potential variation of the driving transistor 121) of the organic EL element 127 due to the time-dependent variation of the characteristics of the organic EL element 127 is obtained. Even if it is, the gate potential Vg can be varied to cancel the variation. Thereby, the uniformity (uniformity) of screen brightness can be ensured. The bootstrap function makes it possible to improve the ability to correct fluctuations over time of the current-driven light-emitting element typified by the organic EL element. Of course, this bootstrap function is a process of rising until the light emission current Iel starts to flow in the organic EL element 127 at the start of light emission, and thereby the voltage between the anode and the cathode becomes stable. Also functions when the source potential Vs of the driving transistor 121 fluctuates with the fluctuation of the anode-cathode voltage Vel.

<Relationship between Vgs-Ids Characteristics of Driving Transistors>

In the first and second comparative examples, the characteristics of the driving transistor 121 are not particularly problematic. However, if the characteristics of the driving transistor 121 differ from pixel to pixel, the influence of the driving current flows through the driving transistor 121. Affects (Ids) As an example, as can be seen from equation (1), when the mobility (μ) or the threshold voltage (Vth) is disturbed by the pixel or changes over time, the gate-source voltage (Vgs) is the same. Even if the driving current Ids flows through the driving transistor 121, a deviation or a change with time occurs, and the light emission luminance of the organic EL element 127 also changes for each pixel.

For example, due to variations in the manufacturing process of the driving transistor 121, there are variations in characteristics such as the threshold voltage Vth and the mobility μ for each pixel circuit P. FIG. Even when the driving transistor 121 is driven in the saturation region, even when the driving transistor 121 is supplied with the same gate potential, the drain current (driving current Ids) varies for each pixel circuit P. This is caused by deviation of the light emission luminance.

As described above, the drain current Ids when the driving transistor 121 is operating in the saturation region is represented by the above formula (1). When attention is paid to the threshold voltage deviation of the driving transistor 121, as apparent from Equation (1), when the threshold voltage Vth fluctuates, the drain current Ids even when the gate-source voltage Vgs is constant. Fluctuates. In addition, when paying attention to the variation in mobility of the driving transistor 121, as apparent from Equation (1) above, if the mobility μ varies, the drain current is constant even when the gate-source voltage Vgs is constant. (Ids) fluctuates.

As described above, when the difference in the threshold voltage Vth or the mobility μ causes a large difference in the Vgs-Ids characteristic, even when the same signal amplitude ΔVin is applied, the driving current Ids fluctuates and the emission luminance is increased. It becomes different and uniformity of screen brightness cannot be obtained. On the other hand, by setting the drive timing (detailed later) which realizes a threshold correction function and a mobility correction function, the influence of these fluctuations can be suppressed and the uniformity of screen brightness can be ensured.

In the threshold correction operation and mobility correction operation employed in the present embodiment, when the write gain is assumed to be an abnormal value of 1, the gate-source voltage Vgs at the time of light emission is displayed as "ΔVin + Vth-ΔV". By doing so, the drain-source current Ids does not depend on the variation or variation in the threshold voltage Vth, and does not depend on the variation or variation in the mobility μ. As a result, even if the threshold voltage Vth and the mobility mu fluctuate with the manufacturing process or with time, the driving current Ids does not fluctuate, and the light emission luminance of the organic EL element 127 does not fluctuate. At the time of mobility correction, the negative feedback is performed so that the mobility correction parameter ΔV1 increases for the large mobility μ1, while the mobility correction parameter ΔV2 also decreases for the small mobility μ2. I walk. In this sense, the mobility correction parameter ΔV is also referred to as negative feedback amount ΔV.

<Pixel Circuit of Comparative Example: Third Example>

The pixel circuit P of the third comparative example is shown in FIG. In the pixel circuit P of the second comparative example shown in Fig. 3, a circuit for preventing the drive current variation due to the aging change of the organic EL element 127, i.e., a bootstrap circuit, is mounted. The pixel circuit P of the third comparative example shown in FIG. 5 based on the pixel circuit P of the present embodiment adopts a driving method which prevents the drive current fluctuation caused by the characteristic variation (threshold voltage variation or mobility variation). to be.

The pixel circuit P of the third comparative example uses the n-type driving transistor 121 similarly to the pixel circuit P of the second comparative example. In addition, a circuit for suppressing fluctuations in driving currents (Ids) of the organic EL element due to changes in the organic EL element over time, that is, driving by correcting a change in the current-voltage characteristic of the organic EL element as an example of an electro-optical element It is characterized in that it comprises a drive signal constant circuit for keeping the current Ids constant. Further, the present invention is characterized in that it has a function of keeping the driving current constant even when there is a change over time in the current-voltage characteristic of the organic EL element.

That is, in addition to the driving transistor 121, a 2TR driving configuration using one switching transistor (sampling transistor 125) for scanning is adopted, and a power supply driving pulse DSL and a write driving controlling each switching transistor are employed. By setting the on / off timing (switching timing) of the pulse WS, the variation over time of the organic EL element 127 and the characteristic variation of the driving transistor 121 (for example, a deviation or fluctuation such as a threshold voltage or mobility) It is characterized in that the influence on the driving current (Ids) by () is prevented. Since it is the structure of 2TR drive, and there are few elements and a wiring number, high precision is attained.

A large difference in configuration with respect to the second comparative example shown in FIG. 3 is a circuit which modifies the connection mode of the storage capacitor 120 and prevents the drive current fluctuation caused by the change of the organic EL element 127 over time, and drives. One aspect of the signal scheduling circuit is to configure a bootstrap circuit. As a method of suppressing the influence on the drive current Ids caused by the characteristic variation of the driving transistor 121 (for example, deviation or variation in threshold voltage, mobility, etc.), the driving timing of each transistor 121, 125 is determined. Cope by devising

Specifically, the pixel circuit P of the third comparative example is the n-type to which the storage capacitor 120, the n-type drive transistor 121, and the write drive pulse WS of the active H (high) are supplied. The transistor 125 has an organic EL element 127, which is an example of an electro-optical element (light emitting element) that emits light as a current flows.

The storage capacitor 120 is connected between the gate terminal (node ND122) and the source terminal of the driving transistor 121, and the source terminal of the driving transistor 121 is directly connected to the anode terminal of the organic EL element 127. It is. The storage capacity 120 also functions as a bootstrap capacity. The cathode end of the organic EL element 127 is connected to the cathode common wiring 127K common to all pixels, similarly to the first comparative example or the second comparative example, and has a cathode potential Vcath (for example, a ground potential GND). ) Is given.

The drain terminal of the drive transistor 121 is connected to a power supply line 105DSL from the drive scanning section 105 which functions as a power scanner. The power supply line 105DSL is characterized in that the power supply line 105DSL itself has a power supply capability to the drive transistor 121.

Specifically, the driving scan unit 105 applies the first potential Vcc on the high voltage side and the second potential Vss on the low voltage side corresponding to the power supply voltage to the drain terminal of the driving transistor 121, respectively. It is provided with the power supply voltage switching circuit which switches and supplies.

The second potential Vss is a potential sufficiently lower than the offset potential Vofs (also referred to as a reference potential) of the video signal Vsig in the video signal line 106HS. Specifically, the power supply so that the voltage Vgs (the difference between the gate potential Vg and the source potential Vs) of the driving transistor 121 becomes larger than the threshold voltage Vth of the driving transistor 121. The second potential Vss on the low potential side of the supply line 105DSL is set. The offset potential Vofs is also used for the initialization operation prior to the threshold correction operation and also for preliminary charging of the video signal line 106HS.

The sampling transistor 125 has a gate terminal connected to the write scanning line 104WS from the write scanning unit 104, a drain terminal connected to the video signal line 106HS, and a source terminal connected to the gate terminal of the driving transistor 121. (Node ND122). The active-H write drive pulse WS is supplied to the gate end thereof from the write scan unit 104.

The sampling transistor 125 can also be set as the connection mode which inverted the source terminal and the drain terminal. As the sampling transistor 125, either a depression type or an enhancement type can be used.

<Operation of the Pixel Circuit: Third Comparative Example>

FIG. 6 is a timing chart illustrating a basic example of driving timing of the third comparative example with respect to the pixel circuit P of the third comparative example shown in FIG. 5, and is shown in the case of linear sequential driving. In FIG. 6, the potential change of the recording scan line 104WS, the potential change of the power supply line 105DSL, and the potential change of the video signal line 106HS are shown in common with the time axis. In parallel with these potential changes, the gate potential Vg and the source potential Vs of the driving transistor 121 are also shown for one row (the first row in the drawing).

The driving timing shown in FIG. 6 is a case of the linear sequential driving, and the write drive pulse WS, the power supply drive pulse DSL, and the video signal Vsig each have one row for one set. The timing (especially phase relationship) of the signals is independently controlled in units of rows, and when the rows are changed, they are shifted by 1H (H is a horizontal scanning period).

In the following description, in order to facilitate explanation and understanding, the recording gain is recorded as 1 (outlier), and the information of the signal amplitude? Vin is recorded in the storage capacitor 120 unless otherwise specified. The description will be briefly described by sampling or sampling. When the recording gain is less than 1, the storage capacitor 120 stores not only the magnitude of the signal amplitude? Vin but the gain-multiplied information corresponding to the magnitude of the signal amplitude? Vin.

In this regard, the ratio of the size of the information recorded in the storage capacitor 120 corresponding to the signal amplitude DELTA Vin is referred to as recording gain. Here, specifically, the recording gain is the total capacitance C1 including the parasitic capacitance arranged in parallel with the storage capacitor 120 in an electrical circuit, and the storage capacity 120 in an electrical circuit. In the capacitor series circuit of the dedicated amount C2 disposed in series with the capacitor, it relates to the amount of charge distributed to the capacitor C1 when the signal amplitude? Vin is supplied to the capacitor series circuit. In the expression, when g = C1 / (C1 + C2), recording gain (Ginput) = C2 / (C1 + C2) = 1-C1 / (C1 + C2) = 1-g. In the following description, the description in which "g" appears is taken into account the recording gain.

In addition, in order to facilitate explanation or understanding, unless otherwise indicated, it is assumed and described simply that the bootstrap gain is 1 (outlier). In this regard, when the storage capacitor 120 is provided between the gate and the source of the driving transistor 121, the rate of increase of the gate potential Vg with respect to the rise of the source potential Vs is obtained by bootstrap gain (bootstrap). Operating capability) (Gbst). Here, the bootstrap gain Gbst is specifically the capacitance value Cs of the storage capacitor 120 and the capacitance value Cgs of the parasitic capacitance C121gs formed between the gate and the source of the driving transistor 121. , The capacitance value Cgd of the parasitic capacitance C121gd formed between the gate and the drain, and the capacitance value Cws of the parasitic capacitance C125gs formed between the gate and the source of the sampling transistor 125. In this case, the bootstrap gain (Gbst) = (Cs + Cgs) / (Cs + Cgs + Cgd + Cws).

In the driving timing of the third comparative example, the period in which the video signal Vsig is in the offset potential Vofs which is an invalid period is set as the first half of one horizontal period, and the signal potential that is the effective period ( The period in Vin) (= Vofs + ΔVin) is the second half of the horizontal period. Further, the threshold correction operation is repeated over a plurality of times (three times in the drawing) for each horizontal period in which the valid period and the invalid period of the video signal Vsig are combined. The timings of the switching timings t13V and t15V of the valid period and the invalid period of each video signal Vsig and the active and inactive switching timings t13W and t15W of the write drive pulse WS are the timings. Each time is distinguished by indicating with a reference of "_" absent.

First, in the light emission period B of the organic EL element 127, the power supply line 105DSL is at the first potential Vcc and the sampling transistor 125 is turned off. At this time, since the driving transistor 121 is set to operate in the saturation region, the driving current Ids flowing through the organic EL element 127 is in response to the gate-source voltage Vgs of the driving transistor 121. , Takes the value shown in equation (1).

Next, in the non-luminescing period, first, in the discharge period C, the power supply line 105DSL is switched to the second potential Vss. At this time, when the second potential Vss is smaller than the sum of the threshold voltage VthEL and the cathode potential Vcath of the organic EL element 127, that is, "Vss <VthEL + Vcath", the organic EL element 127 Is extinguished, and the power supply line 105DSL becomes the source side of the driving transistor 121. At this time, the anode of the organic EL element 127 is charged to the second potential Vss.

In the initialization period D, the sampling transistor 125 is turned on when the video signal line 106HS becomes the offset potential Vofs, and the gate potential of the driving transistor 121 is set to the offset potential Vofs. At this time, the gate-source voltage Vgs of the driving transistor 121 takes the value of "Vofs-Vss". If the "Vofs-Vss" is not larger than the threshold voltage Vth of the driving transistor 121, the threshold correction operation cannot be performed. Therefore, it is necessary to set "Vofs-Vss> Vth".

After that, when the first threshold correction period E is entered, the power supply line 105DSL is switched again to the first potential Vcc. By setting the power supply line 105DSL (that is, the power supply voltage to the driving transistor 121) to the first potential Vcc, the anode of the organic EL element 127 becomes the source of the driving transistor 121 and is driven from the driving transistor 121. The drive current Ids flows. Since the equivalent circuit of the organic EL element 127 is represented by a diode and a capacitance, as long as the anode potential with respect to the cathode potential Vcath of the organic EL element 127 is Vel, " Vel ≦ Vcath + VthEL " In other words, as long as the leakage current of the organic EL element 127 is much smaller than the current flowing through the driving transistor 121, the driving current Ids of the driving transistor 121 is the storage capacitor 120 and the organic EL element 127. It is used to fill the parasitic capacity (Cel) of. At this time, the anode potential Vel of the organic EL element 127 rises with time.

After a predetermined time elapses, the sampling transistor 125 is turned off. At this time, if the gate-source voltage Vgs of the driving transistor 121 is larger than the threshold voltage Vth (that is, the threshold correction is not completed), the driving current Ids of the driving transistor 121 is a storage capacitor. The gate 120 continues to flow to receive power 120, and the gate-source voltage Vgs of the driving transistor 121 rises. At this time, since the reverse bias is applied to the organic EL element 127, the organic EL element 127 does not emit light.

When the second threshold correction period G is entered, the sampling transistor 125 is turned on again when the video signal line 106HS becomes the offset potential Vofs, and the gate potential of the driving transistor 121 is changed to the offset potential Vofs. Then, the threshold correction operation is started again. By repeating this operation, the gate-source voltage Vgs of the driving transistor 121 finally takes the value of the threshold voltage Vth. At this time, " Vel = Vofs-Vth ≦ Vcath + VthEL ".

In addition, in the operation example of the third comparative example, one horizontal period is stored in order to ensure that the storage capacitor 120 has a voltage corresponding to the threshold voltage Vth of the driving transistor 121 reliably by repeatedly executing the threshold correction operation. Although the threshold correction operation is repeated a plurality of times as a processing cycle, this repeating operation is not essential, but it is also possible to execute only one threshold correction operation with one horizontal period as the processing cycle.

After the end of the threshold correction operation (in this example, after the third threshold correction period I), the sampling transistor 125 is turned off to enter the write and mobility correction preparation period J. When the video signal line 106HS becomes the signal potential Vin (= Vofs + ΔVin), the sampling transistor 125 is turned on again to enter the sampling period & mobility correction period K. The signal amplitude ΔVin is a value corresponding to the gray scale. The gate potential of the sampling transistor 125 is the signal potential Vin (= Vofs + ΔVin) since the sampling transistor 125 is turned on, but the drain terminal of the driving transistor 121 is the first potential Vcc and is driven. Since the current Ids flows, the source potential Vs rises with time. In the figure, this increase is indicated by ΔV.

At this time, if the source voltage Vs does not exceed the sum of the threshold voltage VthEL and the cathode potential Vcath of the organic EL element 127, in other words, the leakage current of the organic EL element 127 is the driving transistor 121. If the current is much smaller than the current flowing through the?), The drive current Ids of the drive transistor 121 is used to charge the storage capacitor 120 and the parasitic capacitance Cel of the organic EL element 127.

At this point in time, since the threshold correction operation of the drive transistor 121 is completed, the current flowing through the drive transistor 121 reflects the mobility μ. Specifically, when the mobility μ is large, the amount of current at this time is large, and the rise of the source voltage is also rapid. Conversely, if the mobility µ is small, the amount of current is small, and the rise of the source potential is slowed down. As a result, the gate-source voltage Vgs of the driving transistor 121 decreases to reflect the mobility μ, and the gate-source voltage Vgs that completely corrects the mobility μ after a predetermined time elapses. do.

After this, the light emitting period L is entered, the sampling transistor 125 is turned off, the writing is finished, and the organic EL element 127 is made to emit light. Because of the bootstrap effect by the storage capacitor 120, the gate-source voltage Vgs of the driving transistor 121 is constant, so that the driving transistor 121 generates a constant current (driving current Ids). The anode potential Vel of the organic EL element 127 flows up to the element 127 and rises up to a voltage Vx through which a current called driving current Ids flows in the organic EL element 127. Emits light.

Also in the pixel circuit P of the third comparative example, the organic EL element 127 changes its I-V characteristic when the light emission time becomes long. Therefore, the potential of the node ND121 (that is, the source potential Vs of the driving transistor 121) also changes. However, since the gate-source voltage Vgs of the driving transistor 121 is kept constant due to the bootstrap effect by the storage capacitor 120, the current flowing through the organic EL element 127 does not change. Therefore, even if the I-V characteristic of the organic EL element 127 is deteriorated, a constant current (driving current Ids) always flows through the organic EL element 127, and the luminance of the organic EL element 127 does not change.

Here, the relationship between the drive current Ids and the gate voltage Vgs is expressed by Equation (2-1) by substituting " ΔVin-ΔV + Vth " Can be displayed together. In this regard, when the recording gain is taken into consideration, it can be expressed as in Expression (2-2) by substituting "(1-g) ΔVin-ΔV + Vth" for Vgs in the formula (1). In formula (2-1) or formula (2-2) (collectively referred to as formula (2)), k = (1/2) (W / L) Cox.

Ids = kμ (Vgs-Vth) ^ 2 = kμ (ΔVin-ΔV) ^ 2. (2-1)

Ids = k mu (Vgs-Vth) ^ 2 = k mu ((1-g) ΔVin-ΔV) ^ 2... (2-2)

From this equation (2), it is found that the term of the threshold voltage Vth is canceled, and the driving current Ids supplied to the organic EL element 127 does not depend on the threshold voltage Vth of the driving transistor 121. Can be. Basically, the driving current Ids is determined by the signal amplitude DELTA Vin (in detail, the sampling voltage = Vgs corresponding to the signal amplitude DELTA Vin) and stored in the storage capacitor 120. In other words, the organic EL element 127 emits light with luminance corresponding to the signal amplitude DELTA Vin.

At that time, the information stored in the storage capacitor 120 is corrected by the rise ΔV of the source potential Vs. The rise ΔV acts to obviate the effect of the mobility μ located precisely in the counting portion of equation (2). Although the correction amount ΔV for the mobility μ of the driving transistor 121 is applied to the signal written in the storage capacitor 120, the direction is actually a negative direction, and in this sense, the increase amount ΔV Is also referred to as mobility correction parameter? V and negative feedback amount? V.

The driving current Ids flowing through the organic EL element 127 cancels out variations in the threshold voltage Vth and mobility μ of the driving transistor 121 and substantially depends only on the signal amplitude ΔVin. Done. Since the driving current Ids does not depend on the threshold voltage Vth or the mobility μ, even if the threshold voltage Vth or the mobility μ is disturbed by the manufacturing process or there is a change over time, the drain The driving current Ids between the sources does not change, and the light emission luminance of the organic EL element 127 does not change either.

In addition, by connecting the storage capacitor 120 between the gate and the source of the driving transistor 121, even when the n-type driving transistor 121 is used, the potential Vs of the source terminal of the driving transistor 121 is reduced. A circuit configuration and driving timing for realizing a bootstrap function for allowing the potential Vg of the gate terminal to be linked to the variation, and the anode potential of the organic EL element 127 due to the time-dependent variation of the characteristics of the organic EL element 127. Even if there is a fluctuation (that is, a fluctuation in the source potential of the driving transistor 121), the gate potential Vg can be changed to cancel the fluctuation.

Thereby, the influence of the time-dependent change of the characteristic of the organic EL element 127 is alleviated, and the uniformity of screen brightness can be ensured. The bootstrap function by the storage capacitor 120 between the gate and the source of the driving transistor 121 can improve the capability of correcting fluctuations over time of the current-driven light-emitting element typified by the organic EL element. Of course, the bootstrap function is in the process of rising until the light emission current Iel starts to flow through the organic EL element 127 at the start of light emission, and thereby the voltage between the anode and the cathode becomes stable. It also functions when the source potential Vs of the driving transistor 121 fluctuates with the fluctuation of the voltage between the anode and the cathode.

Thus, according to the driving timing by the pixel circuit P of the 3rd comparative example (actually the same as the pixel circuit P of this Example mentioned later) and the control part 109 which drives it, the drive transistor 121 and organic Even when there is a characteristic variation (deviation or temporal variation) of the EL element 127, by correcting the variation, the effect does not appear on the display screen and high quality image display without luminance change is possible.

By the way, in order to operate the threshold correction function, the signal recording function, the mobility correction function, and the bootstrap function, it is necessary to control the switching of signals to various transistors. For example, in order to control the pixel circuit P of the third comparative example shown in FIG. 5 in the same manner as the driving timing shown in FIG. 6, the sampling transistor 125 is turned on or off or the driving transistor 121 is controlled. Switching control of the power supply to the first potential Vcc and the second potential Vss, or switching control of the image signal Vsig to the offset potential Vofs and the signal potential Vin (= Vofs + ΔVin) There is. Scan lines are required to supply these signals to the pixel circuits P of the pixel array unit 102. When the number of pixel circuits P increases, the number of scan lines also increases accordingly. In view of this, there is a demand for a structure in which the number of scanning lines is reduced while maintaining the number of pixels.

Considering the cost reduction based on the pixel circuit P of the third comparative example described above, the control unit 109 (write scanning unit 104) provided in the periphery of the pixel array unit 102 without reducing the number of pixels. ), It is conceivable to first reduce the number of scanning lines drawn out from the driving scanning unit 105 and the horizontal driving unit 106. By reducing the scanning line, the cost can be reduced by the circuit cost for driving the scanning line.

Comparative Example: Fourth Example

FIG. 7A illustrates a reference circuit for the pixel circuit P of the present embodiment constituting the organic EL display device 1 shown in FIG. 1. FIG. 7B is a timing chart illustrating driving timing when the structure of the reference circuit is applied to the pixel circuit P of the third comparative example (called a fourth comparative example). In FIG. 7A, three pixels (one row and three columns) are shown. This fourth comparative example is one embodiment in consideration of cost reduction. In that regard, part of FIG. 7A and FIG. 7B refer to FIG. 3 and FIG. 5 of Patent Literature 2, and reference numerals and the like are also used as they are.

When the number of scanning lines is reduced and the cost is reduced, attention is paid to the horizontal driver 106 side, and it is conceivable to share the video signal line 106HS in a plurality of pixels. In that case, it is conceivable to employ a structure in which the cost reduction is achieved by sharing the signal line with a plurality of pixels in the liquid crystal display device. For example, it is conceivable to employ the structure described in Patent Document 2.

However, the structure described in Patent Literature 2 is a method of sharing a signal line in adjacent pixels and inputting two video signals to one pixel to rewrite the video signal, which is effective for a method of not performing signal recording while flowing a current. Although it is a means, it cannot simply employ | adopt the structure for the 3rd comparative example which performs mobility correction by performing signal recording while making an electric current drive a current drive type electro-optical element.

This is because, as shown in FIG. 7B, when the video signal Vsig is input to the gate of the driving transistor 121 two or more times, mobility correction is performed on the first video signal Vsig, and after the second time. This is because the mobility correction operation cannot be normally performed on the video signal Vsig input to the gate of the driving transistor 121. For this reason, in the pixel circuit P of the third comparative example, it is difficult to share the video signal line 106HS, and it can be said that there is a problem in terms of cost reduction.

Then, in this embodiment, in the application to the current-driven electro-optical element, when the video signal line 106HS is shared by a plurality of pixels by paying attention to the horizontal driver 106 side, signal writing is performed while flowing current. The structure which makes it possible to perform mobility correction is also adopted. The advantages will be described below.

<Improvement method: First embodiment>

8A to 8C show a horizontal scanning system, adopting a structure for performing mobility correction by writing a signal while flowing current when driving the organic EL element 127, which is an example of a current-driven electro-optical element. It is a figure explaining the first embodiment of the organic EL display device in which the video signal line 106HS is shared by a plurality of pixels. 8A shows a pixel circuit P corresponding to 16 pixels (4 rows and 4 columns) of the organic EL display device 1 of the first embodiment, each scanning unit (write scanning unit 104, and driving scanning unit 105). And a connection relationship between the scanning lines (the recording scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS) between the horizontal drive unit 106. FIG.

FIG. 8B shows details of the connection relationship between the pixel circuit P for the three pixels (one row and three columns) of FIG. 8A and each scan line (the write scan line 104WS, the power supply line 105DSL, and the video signal line 106HS). It is a figure shown. 8C is a timing chart for explaining the driving timing of the first embodiment, and is shown in the case of linear sequential driving. When describing the line number or column attribute (for example, distinguishing between a color variety and an odd number) in the description text, "_" may be referred to by referencing the line number or column attribute. The same applies to other embodiments described later.

In addition to the other embodiments described later, in the present embodiment, when the video signal line 106HS or the video signal Vsig, which is a scanning line of a horizontal scanning system, is shared by a plurality of pixels, first, a sampling transistor is used as one sampling transistor (first first). Is changed to a two-stage cascaded configuration of the sampling transistor 125 of the second transistor and the other sampling transistor (the second sampling transistor 625). In short, the sampling transistor has a double gate structure.

When both sampling transistors 125 and 625 are cascaded, the video signal Vsig (offset potential Vofs or signal potential Vin) from the video signal line 106HS becomes the gate of the driving transistor 121. The sampling transistors 125 and 625 fulfill the AND (logical) function because they are supplied to. Therefore, in the threshold correction preparation pulse or the threshold correction pulse that is the combination of the two sampling transistors 125 and 625, the sampling transistors 125 and 625 of the R, G, and B pixels in the tank are turned on, and the signal write pulse or In the mobility correction pulse, the second sampling transistors 625 in each of the R, G, and B columns shared in response to the color signal potentials Vin_R, Vin_G, and Vin_B may be sequentially turned on.

The second sampling transistor 625 is connected to the write scanning line 104WS of its own row by controlling the control input terminal (gate) of the first sampling transistor 125 of each column to be tone-like and to be controlled by the write drive pulse WS. ), The control input terminal (gate) is connected to the same or different vertical scanning lines of different rows of each other group (another row) for each group that commons the video signal lines 106HS. A characteristic is that the second write drive pulse WS and the other power supply drive pulse DSL are controlled as the sampling control signal SC. Since the write scanning unit 104 and the driving scanning unit 105 are used for the control of the sampling transistor 625, the scanning unit for controlling the second sampling transistor 625 is controlled by the write scanning unit 104 and the driving scanning unit ( Apart from 105), there is no need to prepare separately.

Here, in the entire sampling period & mobility correction period Q_all, when any one of the sampling transistors 625 is turned on for display processing (signal recording or mobility correction in this example), the video signal Vsig or the image Since the other color sampling transistor 125 which uses the signal line 106HS is also turned on, other color sampling is prohibited in order to prohibit the display processing operation (in this example, signal recording and mobility correction) in other colors. The other write drive pulse WS or the other power supply drive pulse DSL is set so that the transistor 625 is turned off.

In addition, the other write driving pulse WS and the other power supply driving pulse DSL, which are also used to control the sampling transistor 625, are to be in a transition state of the same power in each row, that is, in the other row. The state of the basic on / off operation of the transistor based on the write drive pulse WS or power supply drive pulse DSL is adjusted to the maximum. The write drive pulse WS or the power supply drive pulse DSL is used for the sampling control signal SC for controlling the sampling transistor 625 so as to prevent the operation from being unbalanced by the rows. This makes it possible to apply a general structure in which the scan pulse for controlling the vertical scan line of each row creates a reference pulse and sequentially shifts it by 1H in the shift register.

In particular, as a difference from the other embodiments described later, in the first embodiment, the power supply line 105DSL of another row has different gates of the second sampling transistor 625 for each group in which the video signal line 106HS is common. And control by using a different power supply driving pulse DSL. In other words, the control input terminal (gate) of the second sampling transistor 625 is controlled only by the other power supply driving pulse DSL, regardless of the number of columns to be shared by the video signal line 106HS (video signal Vsig). It is characteristic in that it does. Thereby, for each group in which the video signal line 106HS is shared, the other sampling transistor (second sampling transistor 625) is replaced by using a power supply driving pulse DSL of another row except for the row to which the group belongs. By controlling, the number of scanning lines (video signal lines 106HS) drawn out from the horizontal drive section 106 is reduced.

8A to 8C show an example in which three rows of video signal lines 106HS are shared. As a typical three-column example, the color display at the time of color display, that is, the subpixel (subpixel) of R (red), G (green), and B (blue) as a typical example is considerable. 8A and 8B show the case where the video signal Vsig or the video signal line 106HS is shared in three columns for the subpixels R, G, and B for color display, which is a typical example.

In order to share the video signal Vsig in three pixels adjacent to each other in the horizontal direction (pixel circuits P for three columns), first, the sampling transistor is first sampled transistor 125 and second sampled transistor 625. The two-stage cascade connection configuration is used, and the sampling transistor has a double gate structure.

As shown in FIG. 8A, for the first sampling transistor 125, the write drive pulse WS from the write scan unit 104 is connected to the write scan line 104WS in its own row in tone form. To control. The second sampling transistor 625 has different rows of power supply lines 105DSL connected to gates in R, G, and B pixels. Specifically, the R pixel (pixel circuit P_R) is connected to the N-3th power supply line 105DSL_N-3, and the G pixel (pixel circuit P_G) is the N-2nd power supply line 105DSL_N-2. In the B pixel (pixel circuit P_B), the power supply line 105DSL_N-1 on the N-1st line is connected to each other.

8A and 8B, the gates of the second sampling transistors 625 in the R, G, and B columns of which the image signals Vsig are shared are connected to different power supply lines 105DSL of the ostrich (the other row). Because of the connection, the power supply line 105DSL for controlling the sampling transistor 625 is insufficient at the end of the vertical scan of the pixel array unit 102 (the uppermost one in this example), but as many dummy rows are provided. Do it.

8C shows a timing chart of the first embodiment. In addition to the other embodiments described below, the power supply driving pulse DSL, the recording driving pulse WS, and the video signal Vsig are divided into three columns in common with the video signal Vsig and the video signal line 106HS. The timing (particularly the phase relationship) of each signal is defined by using one pair. In the following description, attention will be given to three columns of R, G, and B.

First, since the AND function is performed on the sampling transistor 125 and the sampling transistor 625, the control signal synthesized by the sampling transistors 125 and 625 in the R-th column of the N-th row is the write drive pulse WS_N. And the control signal synthesized by the sampling transistors 125 and 625 in the G-column of the Nth row are the logical product of the write drive pulse WS_N and the power drive pulse DSL_N-2. The control signal synthesized by the sampling transistors 125 and 625 in column B of the N-th row is a logical product of the write drive pulse WS_N and the power drive pulse DSL_N-1.

Regarding the video signal Vsig of each of the R, G, and B columns, the period in which the video signal Vsig is in the offset potential Vofs, which is an invalid period, is taken as the first half of the horizontal period, and the signal potential Vin which is the effective period. The period in which (= Vofs + ΔVin) is the latter half of one horizontal period, and the period of the signal potential Vin is switched to each signal potential (Vin_R, Vin_G, Vin_B) corresponding to the grayscales for R, G, and B. Adopt the technique. In accordance with this, the write drive pulse WS is switched to become active (H) at the signal potentials Vin_R, Vin_G, and Vin_B. In addition, since the on / off control by the second sampling transistor 625 works, the write drive pulse WS may be active H in the entire sampling period & mobility correction period Q_all. This point also applies to other embodiments.

In this regard, since the signal recording is performed in order (for example, in the order of R → G → B) in the period of the signal potential Vin, the signal recording for three columns of the synthesized video signal Vsig is performed. In order to perform the above, it is necessary to switch the video signal Vsig (in detail, the signal potential Vin = Vofs + ΔVin) to Vsig_R for R pixels, Vsig_G for G pixels, and Vsig_B for B pixels to perform signal recording. There is. For this purpose, the signal potential Vin (= Vofs + ΔVin) is switched to the signal potential Vin_R for the R pixel, the signal potential Vin for the G pixel, and the signal potential Vin_B for the B pixel. For this countermeasure, for example, the horizontal drive unit 106 may include a storage unit (for example, a line memory) so that the Vin_R, Vin_G, and Vin_B are switched immediately.

The ratio of the respective periods of the offset potential Vofs and the total signal potential Vin may be set at approximately 50% as in the case of the timing chart of the third comparative example, for example, depending on the gradation for R, G, and B. The period of the signal potential Vin may be widened by taking the point of switching to the signal potentials Vin_R, Vin_G, and Vin_B (in other words, the points in which the signal recording periods of R, G, and B become narrower). Since the period of the offset potential Vofs is narrowed and the threshold correction period per 1H is narrowed by that, the number of threshold corrections may be increased in consideration of this point. These are examples and other timings can be applied.

In addition, in the entire sampling period & mobility correction period Q_all, the prohibition of sampling and mobility correction of other pixels is added, and the sampling of G pixels and B pixels is performed in the sampling period & mobility correction period Q_R of the R pixel. The power supply driving pulses DSL_N-2 and DSL_N-1 in the N-2nd and N-1st rows, which are also used as the sampling control signals SC_G and SC_B for controlling the transistor 625, are set as the second potential Vss. Next time, it is returned to the first potential Vcc when necessary. Likewise, in the sampling period & mobility correction period (Q_G) of the G pixel, the N-3th row and the N-1 which are also used as the sampling control signals SC_R, SC_B for controlling the sampling transistors 625 of the G pixel and the B pixel. The power supply driving pulses DSL_N-3 and DSL_1 in the row are set to the second potential Vss, and then returned to the first potential Vcc when necessary. In addition, during the sampling period & mobility correction period Q_B of the B pixel, the N-3th row and the N-2nd row which are also used as sampling control signals SC_R and SC_G for controlling the sampling transistors 625 of the R pixel and the G pixel. The power supply driving pulses DSL_N-3 and DSL_2 are set to the second potential Vss, and then returned to the first potential Vcc when necessary. The sampling period & mobility correction period Q_R, Q_G, Q_B for each color is determined in the active period of the logical product of the write drive pulse WS in the own row and the power drive pulse DSL in the other row.

In addition, the other power supply driving pulse DSL, which is also used to control the sampling transistor 625, causes the transition state of the same power in each row, that is, the driving transistor based on the power supply driving pulse DSL in the other row. The state of the on / off operation of the basic power line of 121 is adjusted to the maximum. In order to prevent unbalance of operation by rows by using another power supply driving pulse DSL for the sampling control signal SC for controlling the sampling transistor 625. Thereby, the general structure which the power supply drive pulse DSL for controlling the power supply line 105DSL of each row produces | generates a reference pulse, and shifts it sequentially by 1H by a shift register can be applied.

Here, as understood from the timing chart shown in Fig. 8C, in the first embodiment, the threshold value correction between the pixels of each of the R, G, and B columns sharing the video signal Vsig or the video signal line 106HS is used. The frequency is the same. In this regard, the threshold correction preparation period between pixels in each of the R, G, and B columns sharing the video signal Vsig or the video signal line 106HS varies, but the threshold correction preparation is performed by the driving transistor 121. There is no problem because it is an operation of setting the source voltage of to be the second potential Vss.

Further, in the structure of the first embodiment, the power supply driving pulse DSL of another row (in this example, N-3 rows, N-2 rows, and N-1 rows) is set to the second potential Vss. (In other words, the power supply to the driving transistor 121 is turned off) to determine the timing of sampling or mobility correction of the signal potential, so that the power supply driving pulse DSL of its own row is also corrected for the sampling period & mobility. There is a period which becomes the second potential Vss after the period. However, even when the power supply line 105DSL in its own row becomes the second potential Vss (that is, even when the power supply is turned off) after the signal writing is completed, the storage capacitor 120 is connected between the gate and the source of the driving transistor 121. And the bootstrap function and the gate-source voltage Vgs is constant, the organic EL element again when the power supply line 105DSL returns to the first potential Vcc (that is, when the power is turned on). 127 can emit light normally again, and the light emission luminance does not change.

In this regard, the light emission period of the organic EL element 127 is basically a timing in which the write drive pulse WS after the sampling period & mobility correction period Q is made inactive (of the sampling transistor 125). Off timing) and switching to the second potential Vss of the power supply line 105DSL which is the power supply line (power off). In this example, since the threshold preparation period is entered after the write drive pulse WS after the sampling period & mobility correction period Q is inactive, before switching the power supply line 105DSL to the second potential Vss, In the sampling period & mobility correction period Q_all, the signal recording and mobility correction for each pixel of R, G, and B are switched in order, so that the power drive pulses DSL_N-3, DSL_N-2, DSL_N- 3) is once switched to the second potential Vss. For this reason, the sampling period & mobility correction period Q_R of each row, and the time point at which the sampling transistor 125 is turned off later become the light emission start timing, after which the power supply driving pulse DSL for initialization before entering the threshold correction operation. ) Is the end timing of light emission, and the one whose power supply driving pulse DSL excludes the period of the second potential Vss becomes the total light emission period.

As understood from the relationship in the sampling period & mobility correction period Q of the combined control signal by the two sampling transistors 125 and 625 in the timing chart shown in Fig. 8C, in the second half of the 1H period, R The light emission start timings of the pixels G, B are sequentially shifted. However, since the difference is within at least 1H period and is small, the difference in the light emission period of each color may not be considered a problem. When this misalignment becomes a problem, it is good to cope by correcting the signal potentials Vin_R, Vin_G, Vin_B for each color, for example.

In the structure of the first embodiment, since the gate of the second sampling transistor 625 is connected to the other power supply line 105DSL and controlled by the other power supply driving pulse DSL, the second sampling transistor ( It is not necessary to prepare a scanning portion for controlling the 625 separately from the recording scanning portion 104 and the driving scanning portion 105, and there is an advantage that the cost can be reliably realized. Without increasing the number of control signals output from the vertical driver 103 (scanner or driver), and without having an extra control circuit or control line externally, to the sampling transistor 125 (in fact, also to the sampling transistor 625). The number of video signal lines 106HS, which are scanning lines for supplying the video signal Vsig, can be reduced (1/3 roll in this example), and the cost can be reduced.

Further, in the previous example, the gate of the second sampling transistor 625 is connected to the power supply line 105DSL before three rows to one row differently by color, but this is only one example. The gate of the sampling transistor 625 may be connected to the power supply line 105DSL of any row as long as it is the power supply line 105DSL of another row except for the shared line. However, the further the distance away from the common part, the longer the wiring length and the disadvantage of increasing the crossing with the write scanning line 104WS. For example, timing misalignment due to large wiring resistance, cross short due to crossover, or the like may occur. There is also a difficulty in that the number of dummy rows provided at the end portion of the vertical scan of the pixel array unit 102 increases. Therefore, it is preferable that the gate of the second sampling transistor 625 be connected to the power supply line 105DSL in the vicinity of the shared portion.

In the previous example, the video signal line 106HS has been described as an example in which three columns for the subpixels R, G, and B for color display are shared, but this is only one example, and the video signal to be shared is an example. (Vsig) may be plural rows, and not adjacent three rows.

In addition, in the previous example, for the sake of easy understanding, it has been described as an example of sharing the video signal Vsig in three columns for adjacent R, G, and B, but this is only one example, and the number of objects to be shared is arbitrary ( k), and the sampling transistor may have a double gate structure, and the video signal Vsig and the video signal line 106HS may be shared in k columns. In this case, the second sampling transistor 625 is connected to the power supply line 105DSL of each other row except for the row to be shared, and the power supply driving pulse DSL of each other row is applied to the sampling control signal ( SC) can be used. However, similarly to the case of three-column sharing, there is a disadvantage in that the distance from the shared portion increases, the length of the wiring increases, the crossover with the write scanning line 104WS increases, and the dummy row increases.

<Improvement method: Second embodiment>

9A and 9B show a second embodiment of an organic EL display device in which the video signal line 106HS of a horizontal scanning system is shared by a plurality of pixels while adopting a structure in which mobility is corrected by writing a signal while passing a current. It is a figure explaining. Here, Fig. 9A shows a pixel circuit P for three pixels (one row and three columns) of the organic EL display device 1 of the second embodiment, each scan line (write scan line 104WS, power supply line 105DSL, and image). It is a figure which shows the detail of the connection relationship of the signal line 106HS. 9B is a timing chart for explaining the driving timing of the second embodiment, and is shown in the case of linear sequential driving. For ease of understanding, as in the first embodiment, an example of sharing the video signal Vsig or the video signal line 106HS in three columns for the subpixels R, G, and B for color display is shown. Is shown.

In the second embodiment, the specific structure in the pixel circuit P has a double gate structure in which the sampling transistor is a slave connection between the first sampling transistor 125 and the second sampling transistor 625, similarly to the first embodiment. Adopt. The difference from the first embodiment is that the control input terminal (gate) of the second sampling transistor 625 is not controlled only by the other power supply driving pulse DSL, but by the other writing driving pulse WS and the other row. It is characterized in that it is controlled by a combination of the power source driving pulses DSL.

That is, with respect to the gate of the sampling transistor 625, one of the shared columns is connected to the write scan line 104WS of the other row except for the shared portion, and the write drive pulse WS of the other row is used as the sampling control signal SC. In addition to the control box, the other side of the shared column is characterized in that it is connected to the power supply line 105DSL of the other row except for the shared portion and controls the other power supply driving pulse DSL as the sampling control signal SC. . That is, the horizontal driving unit is controlled by controlling the second sampling transistor 625 by using the write drive pulse WS of the other row except for the shared portion and the power drive pulse DSL of the other row (different rows in the commonized portion). The number of scanning lines (video signal lines 106HS) drawn out from 106 is reduced, and the video signal Vsig is shared by a plurality of pixels.

First of all, in order to share the video signal Vsig given to the video signal line 106HS in the pixel circuit P for three columns R, G, and B adjacent in the horizontal direction, first, in FIGS. 8A to 8C. Similarly to the first embodiment shown, the sampling transistor has a two-stage cascade configuration of the first sampling transistor 125 and the second sampling transistor 625. As shown in Fig. 9A, for the first sampling transistor 125, the pixel circuit P for three columns (three columns) of R, G, and B is connected to the same video signal line 106HS. The image signal Vsig is supplied in common to the pixel circuits P of three columns by the image signal Vsig from the horizontal driver 106. Further, the control input terminal (gate) of the first sampling transistor 125 in each of the R, G, and B columns is connected to the write scan line 104WS in its own row as usual, and controlled by the write drive pulse WS_N.

The second sampling transistor 625 is connected to the write scan line 104WS other than its own row by connecting one gate of the shared portion to the write drive pulse WS from the write scan line 104WS of the other row. The other gate of the shared portion is connected to a power supply line 105DSL other than its own row to control by the power supply drive pulse DSL from the other driving scan unit 105. At this time, each of the sampling transistors 625 in each of the R, G, and B columns, which are the shared portions, uses the write drive pulses WS and the power drive pulses DSL in different rows as the sampling control signals SC.

For example, in the N-th R, G, and B pixels, the second sampling transistor 625 has the R pixel in the N + 1th write scan line 104WS_N + 1, and the G pixel in the N-3th row. The power supply line 105DSL_N-3 is connected to the N + 2th write scan line 104WS_N + 2 in the B pixel.

As understood from Fig. 9A, since the gate of the second sampling transistor 625 is connected to the other write scan line 104WS or the power supply line 105DSL, it crosses the write scan line 104WS or the power supply line 105DSL. There is a need to. Note that the write scan line 104WS and the power supply line 105DSL for controlling the sampling transistor 625 are insufficient at the end portion (the uppermost portion or the lowermost portion) of the vertical scan of the pixel array unit 102, but as much as that. It is good to arrange a row of piles.

As shown in the timing chart of the second embodiment shown in Fig. 9B, the period of the signal potential Vin is switched to each of the signal potentials Vin_R, Vin_G, and Vin_B corresponding to the grayscales for R, G, and B, and the sampling period & shift is performed. In the degree correction period Q_all, the sampling transistors 625 of each column which are shared in response to the color-coded signal potentials Vin_R, Vin_G, and Vin_B are sequentially turned on.

In addition, in the entire sampling period & mobility correction period Q_all, the prohibition of sampling & mobility correction of other pixels is added. In the sampling period & mobility correction period Q_R of the R pixel, the sampling transistor of the G pixel ( The N-3th power supply driving pulse DSL_N-3, which is also used as the sampling control signal SC_G for controlling the 625, is set to the second potential Vss and then to the first potential Vcc when it is needed next time. When the N + 2nd write drive pulse WS_N + 2 is used as the inactive L, which is also used as the sampling control signal SC_B for controlling the sampling transistor 625 of the B pixel, Set to active (H).

Similarly, in the sampling period & mobility correction period Q_G of the G pixel, the N + 1st row and the N used also as the sampling control signals SC_R and SC_B for controlling the sampling transistor 625 of the R pixel and the B pixel. The write driving pulses WS_N + 1 and WS_N + 2 in the + 2nd row are made inactive L and made active H the next time it is needed.

Further, in the sampling period & mobility correction period Q_B of the B pixel, the write drive pulse WS_N + 1 of the N + 1st line which is also used as the sampling control signal SC_R for controlling the sampling transistor 625 of the R pixel. ) Is set to inactive L, becomes active (H) next time, and is used as the N-3th line power supply used as the sampling control signal SC_G for controlling the sampling transistor 625 of the G pixel. The pulse DSL_N-3 is set to the second potential Vss and is returned to the first potential Vcc when it is needed later. The sampling period & mobility correction period (Q_R, Q_G, Q_B) for each color is determined in the active period of the logical product of the write drive pulse WS of the own row and the write drive pulse WS of the other row or the power drive pulse DSL. Done.

In addition, the write drive pulse WS and the power drive pulse DSL of the other row, which are also used to control the sampling transistor 625, make the write drive pulses of the other row in such a way as to be in a transition state of the same power in each row. The state of the on / off operation of the sampling transistor 125 based on WS) and the on / off operation of the basic power supply line of the driving transistor 121 based on the power supply driving pulse DSL are adjusted to the maximum. In order to prevent unbalance of operation by rows by using another write drive pulse WS or power supply drive pulse DSL as the sampling control signal SC for controlling the sampling transistor 625. Thus, the write drive pulse WS for controlling the write scan line 104WS of each row and the power drive pulse DSL for controlling the power supply line 105DSL of each row generate a reference pulse, and the shift register It can be generated by applying a general structure to sequentially shift by 1H.

Thus, in the structure of the second embodiment, the handling of the control signal for controlling the second sampling transistor 625 is different from that of the first embodiment, but the write drive pulses WS and the power drive pulses DSL in different rows are different. ), And the timing at which the sampling or mobility correction of the signal potential is performed is determined, so that the period in which the power supply driving pulse DSL in its own row also becomes the second potential Vss after the sampling period & mobility correction period have. However, as understood from the description in the first embodiment, the storage capacitor 120 is connected between the gate and the source of the driving transistor 121, and the bootstrap function acts so that the gate-source voltage Vgs is Since it is constant, the organic EL element 127 can emit light normally again when the power supply line 105DSL returns to the 1st electric potential Vcc again (namely, when power supply is turned on).

In addition, one gate of the second sampling transistor 625 is connected to the other write scan line 104WS and controlled by another write drive pulse WS, while the other side of the second sampling transistor 625 is controlled. Since the gate is connected to the power supply line 105DSL of the other row and controlled by the power supply driving pulse DSL of the other row, the control signal outputted from the vertical driver 103 (scanner or driver) is similar to that of the first embodiment. The video signal line 106HS, which is a scanning line for supplying the video signal Vsig to the sampling transistor 125 (in fact, also to the sampling transistor 625) without increasing the number and having no extra control circuit or control line externally. Can be reduced (in this example, 1/3), and the cost can be reduced.

Also in this second embodiment, the number of threshold corrections is equal between the pixels of each of the R, G, and B columns sharing the video signal Vsig and the video signal line 106HS. In this regard, the threshold correction preparation period between pixels sharing the video signal Vsig or the video signal line 106HS varies, but as is understood from the description in the first embodiment, the threshold correction preparation is made. Since the operation is an operation of setting the source voltage of the driving transistor 121 to the second potential Vss, there is no problem.

Also in the structure of the second embodiment, the power supply driving pulse DSL of the other row is set to the second potential Vss (in other words, the power supply to the driving transistor 121 is turned off), and the signal potential of other pixels is sampled. In addition, since the timing for performing mobility correction is determined, specifically, the power supply driving pulse DSL of the N-3th row to the Nth row used for the signal recording of the R pixel and the B pixel is applied to the second potential Vss. Since the timing for sampling and mobility correction of the signal potentials of the R pixels and the B pixels is determined, the power supply driving pulse DSL of its own row also has the second potential Vss after the sampling period & mobility correction period. There is a period of time. However, as will be understood from the description in the first embodiment, even when the power supply line 105DSL in its own row becomes the second potential Vss (that is, the power is turned off) after the signal writing ends, the driving transistor 121 When the storage capacitor 120 is connected between the gate and the source of the capacitor and the bootstrap function is applied to the gate-source voltage Vgs is constant, the power supply line 105DSL is returned to the first potential Vcc again. (I.e., when the power supply is turned on), the organic EL element 127 can emit light again normally, and the emission luminance does not change.

<Improvement method: Third embodiment>

10A and 10B show a third embodiment of an organic EL display device in which the video signal line 106HS of a horizontal scanning system is shared among a plurality of pixels while adopting a structure in which mobility is corrected by writing signals while passing current. It is a figure explaining. 10A shows a pixel circuit P for three pixels (one row and three columns) of the organic EL display device 1 of the third embodiment, each scan line (write scan line 104WS, power supply line 105DSL, and image). It is a figure which shows the detail of the connection relationship of the signal line 106HS. 10B is a timing chart for explaining the driving timing of the third embodiment, and is shown in the case of linear sequential driving. For ease of understanding, as in the first and second embodiments, an example in which the video signal Vsig or the video signal line 106HS is shared in three columns for the subpixels R, G, and B for color display is used. Each figure is shown.

In the third embodiment, similarly to the second embodiment, the control input terminal (gate) of the second sampling transistor 625 is not controlled by the other power supply drive pulse DSL, but by the other write drive pulse WS. ) And the other power supply pulse DSL. The difference from the second embodiment is that the combination and rows of the write drive pulse WS and the power drive pulse DSL used as the sampling control signal SC are different from each other, and in fact, may be considered to be the same as the second embodiment. .

For example, in the N-row R, G, and B pixels, the second sampling transistor 625 has the R pixel in the N-3th power supply driving pulse DSL_N-3, and in the G pixel, N-2. It is connected to the power supply line 105DSL_N-2 of the row, and to the write scanning line 104WS_N + 1 of the N + 1st line in the B pixel, respectively.

As understood from Fig. 10A, since the gate of the second sampling transistor 625 is connected to the other write scan line 104WS or the power supply line 105DSL, it crosses the write scan line 104WS or the power supply line 105DSL. There is a need to. Note that the write scan line 104WS and the power supply line 105DSL for controlling the sampling transistor 625 are insufficient at the end portion (the uppermost or the lowermost portion) of the vertical scan of the pixel array unit 102. It is good to arrange a row of piles.

Also in the second and third embodiments, as described in the first embodiment, the number of the shared write drive pulses WS and the write scan lines 104WS to be shared is not limited to two, but the second sampling transistor is used. The setting of the row of the write drive pulse WS or the power drive pulse DSL controlling the gate of 625 is a separate row from the row to which the pair of the write drive pulse WS and the write scan line 104WS to be shared belong. As long as each is a different row, it is not limited to the above-mentioned example. However, as in the case of three-column sharing, there is a disadvantage in that, as the distance from the shared portion decreases, the wiring length increases, and the dummy row increases, the intersection with the write scanning line 104WS increases.

As in the timing chart of the second embodiment shown in Fig. 10B, similarly to the first and second embodiments, the signal potentials (Vin_R, Vin_G, Vin_B), and in the sampling period & mobility correction period Q_all, the sampling transistors 625 of each column shared in response to the signal potentials Vin_R, Vin_G, and Vin_B for each color are sequentially turned on.

In addition, in the entire sampling period & mobility correction period Q_all, the prohibition of sampling & mobility correction of other pixels is added. In the sampling period & mobility correction period Q_R of the R pixel, the sampling transistor of the G pixel ( The power supply driving pulse DSL_N-2 of the N-2nd line which is also used as the sampling control signal SC_G for controlling the 625 is set to the second potential Vss, and then to the first potential Vcc when it is needed later. When the N + 1st write drive pulse WS_N + 1 is used as the inactive L, which is also used as the sampling control signal SC_B for controlling the sampling transistor 625 of the B pixel, Set to active (H).

Similarly, in the sampling period & mobility correction period Q_G of the G pixel, the N-3th line power supply driving pulse DSL_N-3 which is also used as the sampling control signal SC_R for controlling the sampling transistor 625 of the R pixel. N + 1st line used as the sampling control signal SC_B for controlling the sampling transistor 625 of the B pixel to return to the first potential Vcc when the next time it is necessary. The write drive pulse WS is set to the inactive L and is made active H the next time it is needed.

In addition, in the sampling period & mobility correction period Q_B of the B pixel, the N-3th row and the N− used also as the sampling control signals SC_R and SC_G for controlling the sampling transistor 625 of the R pixel and the G pixel. The second power supply driving pulses DSL_N-3 and DSL_N-2 are set to the second potential Vss and returned to the first potential Vcc when necessary later. The sampling period & mobility correction period (Q_R, Q_G, Q_B) for each color is determined by the active period of the logical product of the write drive pulse WS in the own row and the write drive pulse WS in the other row or the power drive pulse DSL. Done.

In addition, similarly to the second embodiment, the other write drive pulse WS or power supply pulse DSL, which is also used to control the sampling transistor 625, is set to 1H so as to be in the same transition state in each row. The state is shifted gradually.

As described above, in the structure of the third embodiment, the handling of the rows of the write drive pulse WS and the power source drive pulse DSL for controlling the second sampling transistor 625 is different from that of the second embodiment. The basic way of thinking is the same as in the second embodiment, and can enjoy the same effects as in the second embodiment.

However, when the first embodiment is compared with the second and third embodiments by paying attention to the handling of the sampling control signal SC for controlling the second sampling transistor 625 having the double gate structure, the first embodiment In the second and third embodiments, all use the same type of control signal (different line power drive pulse DSL) as the sampling control signal SC. There is a difference that the write drive pulse WS and the power drive pulse DSL are used as the sampling control signal SC.

In terms of the symmetry of the operation, in other words, the timing of the sampling control signal SC for controlling the second sampling transistor 625, the first embodiment uses the same vertical scanning pulse (power supply driving pulse DSL). The courtesy is excellent. The loads are different in the write scan line 104WS and the power supply line 105DSL, and the second sampling transistor 625 is controlled when the video signal Vsig or the video signal line 106HS is shared by a plurality of columns, so that these heterogeneous vertical types are different. This is because the use of the scanning pulse may cause the difference to appear in the image.

<Improvement method: Fourth embodiment>

11A to 11C show a horizontal scanning system, adopting a structure for performing mobility correction by performing signal recording while flowing current when driving the organic EL element 127, which is an example of the current-driven electro-optical element. It is a figure explaining the fourth embodiment of the organic EL display device in which the video signal line 106HS is shared by a plurality of pixels. Here, FIG. 11A shows the pixel circuit P for 12 pixels (3 rows and 4 columns) of the organic EL display device 1 of the fourth embodiment, and each scanning unit (write scanning unit 104 and driving scanning unit 105). And a connection relationship between the scanning lines (the recording scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS) between the horizontal drive unit 106. FIG. FIG. 11B shows details of the connection relationship between the pixel circuit P for the four pixels (one row and four columns) of FIG. 11A and each scan line (the write scan line 104WS, the power supply line 105DSL, and the video signal line 106HS). It is a figure which shows. 11C is a timing chart for explaining the driving timing of the fourth embodiment, and is shown in the case of linear sequential driving.

In the fourth embodiment, the specific configuration in the pixel circuit P is similar to that of the first to third embodiments, in which the sampling transistor is doubled as the cascade connection of the first sampling transistor 125 and the second sampling transistor 625. Adopt gate structure. Different from the first to third embodiments, the control input terminal (gate) of the second sampling transistor 625 is connected regardless of the number of columns to be shared by the video signal line 106HS (video signal Vsig). It is characterized in that it is not controlled only by the other power supply drive pulse DSL, but only by the other write drive pulse WS. Thereby, for each group in which the video signal line 106HS is shared, the other sampling transistor (second sampling transistor 625) is controlled by using the other write drive pulses WS, except for the row to which the group belongs. This reduces the number of scanning lines (video signal lines 106HS) drawn out from the horizontal driver 106.

11A to 11C show examples of sharing the video signal line 106HS (video signal Vsig) in two adjacent columns (odd and even columns). Here, the second sampling transistor 625 controls the write driving pulse WS from the other write scan line 104WS by connecting one gate of the shared portion to the write scan line 104WS other than its own row. At the same time, the other gate of the shared part is also connected to the write drive pulses WS other than its own row to control the write drive pulses WS from the other write scan unit 104. At this time, each of the sampling transistors 625 in the two columns, which are the shared portions, uses the write drive pulses WS in different rows as the sampling control signal SC.

For example, in the N-th pixel circuits P_o and P_e, the second sampling transistor 625 has an odd-numbered pixel circuit P_o in the N + 1th write scan line 104WS_N + 1 and has even-numbered columns. The pixel circuits P_e are connected to the write drive pulses WS_N + 2 of the N + 2th row, respectively.

As understood from FIG. 11A, since the gate of the second sampling transistor 625 is connected to the write scan line 104WS of the other row, it is necessary to cross the write scan line 104WS of each row. Note that the write scanning line 104WS for controlling the sampling transistor 625 is insufficient at the end portion (lowermost portion in this example) of the vertical scanning of the pixel array unit 102, but it is sufficient to provide as many dummy rows.

Also in the fourth embodiment, as described in the first to third embodiments, the number of the common write drive pulses WS and the write scan lines 104WS is not limited to two. The example is shown in the fifth embodiment. The setting of the row of the write drive pulse WS that controls the gate of the second sampling transistor 625 is a separate row from the row to which the group of the write drive pulse WS and the write scan line 104WS to be shared belong. As long as each is a different row, it is not limited to the above-mentioned example. For example, the write drive pulse WS (write scan line 104WS) that controls the sampling transistor 625 is shared with the corresponding row (N + 2nd and N + 3rd rows) with respect to the Nth row. Row), and the write drive pulse WS of any row after the N + 1st row may be used. However, as in the case of three-column sharing, there is a disadvantage in that, as the distance from the shared portion decreases, the wiring length increases, and the dummy row increases, the intersection of the write scanning lines 104WS increases, and so on.

As in the timing chart of the fourth embodiment shown in Fig. 11C, similarly to the first to third embodiments, the signal potential Vin corresponding to the gray level for the pixel circuits P_o and P_o is applied to the period of the signal potential Vin. , Vin_e), and in the sampling period & mobility correction period Q_all, the sampling transistors 625 of each column shared in response to the signal potentials Vin_o and Vin_e for each pixel circuit P are sequentially turned on. Set it.

In addition, in the total sampling period & mobility correction period Q_all, the prohibition of sampling & mobility correction of other pixels is also added, and in even-numbered columns, the sampling period & mobility correction period Q_o of the pixel circuit P_o is even. The N + 2th write drive pulse WS_N + 2, which is also used as the sampling control signal SC_2 for controlling the sampling transistor 625 of the pixel circuit P_e in the column, is set to be inactive L, and is subsequently required. Is set to active (H). Likewise, in the sampling period & mobility correction period Q_e of the even-numbered pixel circuits P_e, N used as the sampling control signal SC_1 for controlling the sampling transistor 625 of the odd-numbered pixel circuits P_o. The write drive pulse WS_N + 1 in the + 1st row is set to the inactive L and becomes active (H) the next time it is needed. The sampling period & mobility correction periods Q_o and Q_e for each pixel circuit P are determined in the active period of the logical product of the write drive pulse WS in the own row and the write drive pulse WS in the other row.

In addition, as in the first to third embodiments, the other write drive pulse WS, which is also used to control the sampling transistor 625, is shifted by 1H so as to have a transition state equal to the maximum in each row. .

Thus, in the structure of the fourth embodiment, the handling of the sampling control signal SC for controlling the second sampling transistor 625 is different from that of the first to third embodiments, and the image signal Vsig (the image signal line ( 106HS)), but the write drive pulse WS of the other row except for the row to which the pair which is shared is made, but the basic way of thinking is the same as in the first to third embodiments, and the same effects as in the first to third embodiments are enjoyed. can do.

For example, without increasing the number of control signals output from the vertical driver 103 (scanner or driver), and without having an extra control circuit or control line externally, the sampling transistor 125 (in fact, a sampling transistor). Also at 625, the number of video signal lines 106HS, which are scanning lines for supplying the video signal Vsig, can be reduced (half in this example), and the cost can be reduced.

In addition, as the sampling control signal SC for controlling the second sampling transistor 625, another write drive pulse is irrespective of the number of columns to be shared by the video signal line 106HS (video signal Vsig). In terms of using only (WS), the same effects as those in the first embodiment using only the other power supply driving pulse DSL can be enjoyed, and are superior to those in the second and third embodiments.

Further, in this fourth embodiment (even in the fifth embodiment described later), the sampling control signal SC for controlling the gate of the sampling transistor 625 in reducing the video signal line 106HS (video signal Vsig). Since only the write drive pulse WS is used instead of the power drive pulse DSL, the video signal line 106HS (video signal Vsig is not affected by the wiring form of the power supply line 105DSL). There is an advantage that can cut)). For example, even if the power supply driving pulse DSL is common in the panel, it can be applied and the cost can be reduced.

Also in this fourth embodiment, the number of times of threshold correction between the odd-numbered and even-numbered pixels sharing the video signal Vsig or the video signal line 106HS is the same. In this regard, the threshold correction preparation periods Q_o and Q_e between odd-numbered columns and even-numbered pixels sharing the video signal Vsig or the video signal line 106HS vary, but the first to third embodiments are different. As will be understood from the description in the above, there is no problem because the threshold correction preparation is an operation of making the source voltage of the driving transistor 121 a second potential Vss.

<Improvement method: fifth embodiment>

12A to 12C show a fifth embodiment of an organic EL display device in which the video signal line 106HS of a horizontal scanning system is shared among a plurality of pixels while adopting a structure in which mobility is corrected by writing signals while passing current. It is a figure explaining. 12A shows a pixel circuit P for 16 pixels (4 rows and 4 columns) of the organic EL display device 1 of the fifth embodiment, each scanning unit (write scanning unit 104, and driving scanning unit 105). And a connection relationship between the scanning lines (the recording scanning line 104WS, the power supply line 105DSL, and the video signal line 106HS) between the horizontal drive unit 106. FIG. FIG. 12B shows the details of the connection relationship between the pixel circuit P for the three pixels (one row and three columns) of FIG. 12A and each scan line (the write scan line 104WS, the power supply line 105DSL, and the video signal line 106HS). It is a figure which shows. P13 is a timing chart for explaining the driving timing of the fifth embodiment, and is shown in the case of linear sequential driving. For ease of understanding, as in the first to third embodiments, an example in which the image signal Vsig or the image signal line 106HS is shared in three columns for the subpixels R, G, and B for color display is used. Each figure is shown.

The fifth embodiment adopts a double gate structure in which the sampling transistors are cascaded between the first sampling transistor 125 and the second sampling transistor 625, similarly to the first to fourth embodiments. As in the fourth embodiment, the control input terminal (gate) of the second sampling transistor 625 is connected to the other power source regardless of the number of columns to be shared by the video signal line 106HS (video signal Vsig). The number of scan lines (video signal lines 106HS) drawn out from the horizontal drive section 106 is reduced by controlling only the write drive pulses WS of the other row, not controlling only the drive pulses DSL. The only difference from the fourth embodiment is that the number of columns to be shared is different.

First of all, in order to share the video signal Vsig given to the video signal line 106HS in the pixel circuit P for three columns R, G, and B adjacent in the horizontal direction, first, in FIGS. 8A to 8C. Similarly to the first embodiment shown, the sampling transistor has a two-stage cascade configuration of the first sampling transistor 125 and the second sampling transistor 625. 12A and 12B, for the first sampling transistor 125, the pixel circuit P for three columns (three columns) for R, G, and B is the same video signal line 106HS. ), The video signal Vsig is supplied in common to the pixel circuits P in the three columns as the video signal Vsig from the horizontal driver 106. Further, the control input terminal (gate) of the first sampling transistor 125 in each of the R, G, and B columns is connected to the write scan line 104WS in its own row as usual, and controlled by the write drive pulse WS_N.

Similarly to the fourth embodiment, the second sampling transistor 625 is connected to the write scanning lines 104WS of the different rows, and uses the write drive pulses WS of the different rows as the sampling control signal SC. To control. For example, in the N-th R, G, and B pixels, the second sampling transistor 625 has the R pixel in the N + 1th write scan line 104WS_N + 1 and in the G pixel in the N + 2th row. Is connected to the write scan pulse WS_N + 2 at the B pixel, and to the write scan line 104WS_N + 3 at the N + 3th line, respectively.

Also in the fifth embodiment, as described in the first to fourth embodiments, the setting of the row of the write drive pulses WS for controlling the gate of the second sampling transistor 625 is common to the write drive. The row WS is separate from the row to which the pair of the pulse WS or the recording scan line 104WS belongs, and is not limited to the above-described example as long as they are different rows. For example, the write drive pulse WS (write scan line 104WS) for controlling the sampling transistor 625 is shared, as in the N + 2th row, the N + 3rd row, and the N + 4th row with respect to the Nth row. The write drive pulses WS in any row after the N + 1st row may be used except for the corresponding row (N row). However, as in the case of three-column sharing, there is a disadvantage in that, as the distance from the shared portion decreases, the wiring length increases, and the dummy row increases, the intersection of the write scanning lines 104WS increases, and so on.

As shown in the timing chart of the fifth embodiment shown in Fig. 12C, the period of the signal potential Vin is switched to each of the signal potentials Vin_R, Vin_G, and Vin_B corresponding to the grayscales for R, G, and B, and the sampling period & shift is performed. In the degree correction period Q_all, the sampling transistors 625 in each of the R, G, and B columns shared in response to the signal potentials Vin_R, Vin_G, and Vin_B for each color are sequentially turned on.

In addition, in the entire sampling period & mobility correction period Q_all, the prohibition of sampling & mobility correction of other pixels is added. In the sampling period & mobility correction period Q_R of R pixels, The write drive pulses WS_N + 2 and WS_3 in the N + 2th row or the N + 3rd row, which are also used as the sampling control signals SC_G and SC_B for controlling the sampling transistor 625, are made inactive (L). When it is needed, it is made active (H). Similarly, in the sampling period & mobility correction period Q_G of the G pixel, the N + 1st line or N + used also as the sampling control signals SC_R and SC_B for controlling the sampling transistor 625 of the R pixel or the B pixel. The write driving pulses WS_N + 1 and WS_N + 3 in the third row are made inactive L and made active H the next time it is needed. In the sampling period & mobility correction period Q_B of the B pixel, the N + 1st row or the N + 2nd row also used as the sampling control signals SC_R and SC_G for controlling the sampling transistor 625 of the R pixel and the G pixel. The write drive pulses WS_N + 1 and WS_N + 2 are set to inactive L and made active (H) the next time they are needed. The sampling period & mobility correction periods Q_R, Q_G, and Q_B for each color are determined in the active period of the logical product of the write drive pulse WS in the own row and the write drive pulse WS in the other row.

The write drive pulse WS of the other row, which is also used to control the sampling transistor 625, is to make the transition state in the same row as that of each row, that is, the sampling transistor based on the write drive pulse WS in the other row. The state of the basic on / off operation of 125 is trimmed to the maximum. By using another write drive pulse WS for the sampling control signal SC for controlling the sampling transistor 625, the write scan line 104WS of each row is prevented from causing unbalance of operation by the rows. The write drive pulse WS for controlling can apply the general structure which produces | generates a reference pulse and shifts it sequentially by 1H by a shift register.

As described above, in the structure of the fifth embodiment, the handling of the control signal for controlling the second sampling transistor 625 is the write drive pulses WS of all other rows as in the fourth embodiment, and the write drive pulses of the other rows ( Since the timing at which the signal potential is sampled and the mobility correction is determined by changing WS), the same effects as in the fourth embodiment can be enjoyed.

For example, without increasing the number of control signals output from the vertical driver 103 (scanner or driver) and without having an extra control circuit or control line externally, the sampling transistor 125 (virtually sampled). In the transistor 625, the number of the video signal lines 106HS, which are the scan lines for supplying the video signals Vsig, can be reduced (in this example, 1/3), and the cost can be reduced.

Also in the fifth embodiment, the number of threshold corrections is equal between the pixels of each of the R, G, and B columns sharing the video signal Vsig and the video signal line 106HS. In this regard, the threshold correction preparation period between the pixels of each of the R, G, and B columns which share the video signal Vsig or the video signal line 106HS varies, but in the first to fourth embodiments, As will be understood from the description, the threshold correction preparation is not a problem because it is an operation of making the source voltage of the driving transistor 121 a second potential Vss.

Further, in the first to fifth embodiments described above, when driving the organic EL element 127, which is an example of the current-driven electro-optical element, signal writing is performed while flowing a current from the driving transistor 121 (i.e., storage). In an example of application to a structure in which mobility correction is performed on the capacitor 120 while sampling information corresponding to the signal potential Vin, a structure in which the video signal Vsig (video signal line 106HS) is shared in a plurality of columns Although shown concretely, the application is a pixel circuit which writes a signal without flowing a current, in other words, the mobility correction | amendment after completing writing a signal to the storage capacitor 120 completely in the state which does not flow a current in the drive transistor 121, (Signal write and mobility correction are performed at different timings) or signal write to storage capacitor 120 in a state in which no current flows to drive transistor 121. After pro, spilling a current to the driving transistor 121 can be continuously applied to a moving type also enter the calibration.

For example, it can apply to the thing of the 5TR structure of patent document 1, In this case, the power supply line 105DSL and power supply drive pulse DSL in the said 1st-5th Example are described in the said publication. Substituted by the scan line DS and the control signal DS connected to the gate of the transistor Tr4, the write scan line 104WS and the write drive pulse WS are connected to the gate of the transistor Tr1 described in the publication. It may be applied by replacing with the scanning line WS or the control signal WS.

The first to fifth embodiments described above can also be applied to a method of recording a signal while performing mobility correction in two steps.

As mentioned above, although this invention was demonstrated using an Example, the technical scope of this invention is not limited to the range as described in the said Example. Various changes or improvement can be added to the said Example in the range which does not deviate from the summary of invention, and the form which added such a change or improvement is also included in the technical scope of this invention.

Incidentally, the above embodiment does not limit the invention related to claims (claims), and not all of the combinations of the features described in the embodiments are essential to the solving means of the invention. The above-described embodiments include inventions of various stages, and various inventions can be extracted by appropriate combinations of a plurality of configuration requirements to be started. Even if some of the constituent requirements are deleted from all the constituent requirements shown in the embodiment, a configuration in which some of the constituent requirements are deleted can be extracted as the invention as long as an effect can be obtained.

<Modification Example of Pixel Circuit>

For example, the change from the side surface of the pixel circuit P is possible. For example, since a "principle of duality" holds true in circuit theory, the pixel circuit P can be modified in this respect. In this case, although shown in the drawing, first, the pixel circuit P shown in each of the above-described embodiments is constructed using the n-type driving transistor 121, so that the p-type driving transistor 121 is used. The pixel circuit P is formed. In accordance with this, a change is made in accordance with the principle of duality, such as reversing the polarity of the signal amplitude DELTA Vin and the magnitude of the power supply voltage with respect to the offset potential Vofs of the video signal Vsig.

For example, in the pixel circuit P in the deformed state according to the "principle of duality", it is stored between the gate terminal and the source terminal of the p-type driving transistor (hereinafter referred to as p-type driving transistor 121p). The capacitor 120 is connected, and the source terminal of the p-type driving transistor 121p is directly connected to the cathode terminal of the organic EL element 127. The anode end of the organic EL element 127 is an anode potential (Vanode) as a reference potential. This anode potential (Vanode) is connected to the reference power supply cloth (high potential side) common to all the pixels which supply a reference potential. The p-type driving transistor 121p has its drain terminal connected to the first potential Vss on the low voltage side, and flows a driving current Ids for causing the organic EL element 127 to emit light.

In the organic EL display device of the modified example in which the driving transistor 121 is p-type by applying the principle of such duality, the threshold correction operation and mobility correction are performed similarly to the organic EL display device having the n-type driving transistor 121. Operations, and bootstrap operations.

When driving such a pixel circuit P, as in the above-described first to fifth embodiments, the sampling transistor has a double gate structure, and the first sampling transistor 125 therein is a normal write drive pulse ( Scanning with WS, the second sampling transistor 625 samples a write drive pulse WS or a power drive pulse DSL other than its own row for sharing the video signal line 106HS (video signal Vsig). By using the control as the control signal SC, similarly to the above-described embodiment, an extra control circuit or control line is externally provided without increasing the number of control signals output from the vertical driver 103 (scanner or driver). The number of video signal lines 106HS, which are scanning lines for supplying the video signal Vsig to the sampling transistor 125 (in fact, also the sampling transistor 625), may be reduced and the cost may be reduced.

In addition, although the modification of the pixel circuit P demonstrated here added the change according to "the principle of duality" with respect to the structure shown to the said 1st-5th embodiment, the method of circuit change is not limited to this. . In executing the threshold correction operation, the video signal Vsig which switches between the offset potential Vofs and the signal potential Vin (= Vofs + ΔVin) within each horizontal period in accordance with the scan in the recording scanning unit 104 is performed. 2TR configuration as long as driving is performed to be transmitted to the video signal line 106HS, and switching driving of the drain side (power supply side) of the driving transistor 121 to the first potential and the second potential is performed for the initialization operation of the threshold correction. Regardless of whether it is recognized or not, three or more transistors may be used, and the video signal line 106HS (video signal Vsig) is applied to all of them by applying the above-described improvement methods of the present embodiment to double gate the sampling transistor. The idea of this embodiment can be applied to reduce cost by reducing the number of.

Further, in the execution of the threshold correction operation, the structure in which the offset potential Vofs and the signal potential Vin are supplied to the gate of the driving transistor 121 is handled by the video signal Vsig as in the 2TR configuration of the above embodiment. For example, as described in Patent Literature 1, a structure for supplying via other transistors may be adopted, and even in these modifications, each improvement technique of the above-described present embodiment in which the gate of the sampling transistor is double gated is also employed. The idea of this embodiment can be applied by reducing the number of video signal lines 106HS (video signals Vsig) to reduce the cost.

The present invention claims priority of Japanese Patent Application No. 2008-89981 filed with the Japan Patent Office on March 31, 2008.

Those skilled in the art will be able to practice various modifications, combinations, partial combinations, and modifications according to design needs or other factors within the scope of the following claims or equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an outline of a configuration of an active matrix display device which is one embodiment of a display device according to the present invention.

Fig. 2 is a diagram showing a first comparative example with respect to the pixel circuit of this embodiment.

3 shows a second comparative example with respect to the pixel circuit of this embodiment;

4A is an explanatory diagram illustrating an operating point of an organic EL element and a driving transistor.

4B is an explanatory diagram illustrating the influence of variation in characteristics of an organic EL element or driving transistor on driving current.

5 is a diagram showing a fourth comparative example with respect to the pixel circuit of this embodiment.

6 is a timing chart for explaining a basic example of driving timing of a third comparative example according to the pixel circuit of the third comparative example shown in FIG. 5;

7A is a diagram for explaining a reference circuit with respect to the pixel circuit of this embodiment.

7B is a timing chart illustrating driving timing of a fourth comparative example in which the structure of the reference circuit is applied to the pixel circuit of the third comparative example.

Fig. 8A is a diagram showing an overall outline of the connection relationship between the scanning lines and the pixel circuits of the organic EL display device of the first embodiment.

8B is a diagram showing details of the connection relationship between a pixel circuit and a scanning line in the first embodiment;

8C is a timing chart for explaining driving timing of the first embodiment.

Fig. 9A is a diagram showing an overall outline of the connection relationship between the scanning lines and the pixel circuits of the organic EL display device of the second embodiment.

9B is a timing chart for explaining the driving timing of the second embodiment.

Fig. 10A is a diagram showing an overall outline of a connection relationship between scanning lines and pixel circuits of an organic EL display device of a third embodiment.

10B is a timing chart for explaining driving timing of the third embodiment.

Fig. 11A is a diagram showing an overall outline of a connection relationship between scanning lines and pixel circuits of an organic EL display device of a fourth embodiment.

Fig. 11B is a diagram showing details of a connection relationship between a pixel circuit and a scanning line in the fourth embodiment.

Fig. 11C is a timing chart for explaining driving timing of the fourth embodiment.

FIG. 12A is a diagram showing an overall outline of a connection relationship between each scanning line and a pixel circuit in the organic EL display device of the fifth embodiment. FIG.

Fig. 12B is a diagram showing details of the connection relationship between a pixel circuit and a scanning line in the fifth embodiment.

12C is a timing chart for explaining driving timing of the fifth embodiment.

(Explanation of symbols for the main parts of the drawing)

1 Organic EL Display 100 Display Panel

101 substrate 102 pixel array portion

103: vertical drive unit 104: recording scanning unit

105: driving scan unit 106: horizontal driving unit

109 control unit 120 storage capacity

121: driving transistor 122: light emitting control transistor

125, 625: sampling transistor

127: organic EL device (an example of electro-optical device)

200: driving signal generation unit 300: image signal processing unit

Cel: Parasitic Capacitor P: Pixel Circuit

Claims (14)

A driving transistor for generating a driving current, an electro-optical element connected to an output terminal of the driving transistor, a storage capacitor for storing information according to a signal amplitude of an image signal, and a slave connection for recording information according to the signal amplitude in the storage capacitor A plurality of pixel circuits each having a first sampling transistor and a second sampling transistor arranged in a matrix; A vertical scanning unit generating a vertical scanning pulse for vertically scanning the pixel circuit; A plurality of vertical scanning lines connected to the vertical scanning unit; A horizontal scanning unit which supplies the image signal to the pixel circuit in synchronization with the vertical scanning by the vertical scanning unit; And A plurality of horizontal scanning lines connected to the horizontal scanning unit, The vertical scanning portion includes a writing scanning portion for vertically scanning at least the pixel circuit to generate a write scanning pulse for writing information according to the signal amplitude into the storage capacitor, The vertical scanning line includes a plurality of recording scanning lines connected to the recording scanning unit, Each of the horizontal scanning lines is wired so that the video signal for signal writing from the horizontal scanning unit is commonly supplied to an input terminal of the first sampling transistor included in a plurality of columns. The control input terminal of the second sampling transistor belonging to each of the pairs each including the plurality of columns to which the video signal is commonly supplied has the vertical to the other rows of the other groups except the group to which the second sampling transistor belongs. And a scanning pulse connected to the vertical scanning line such that a scanning pulse is supplied from the vertical scanning unit to the control input terminal of the second sampling transistor. The method of claim 1, The control input terminal of the second sampling transistor is connected to the vertical scan line of the same type so that the vertical scan pulse for vertical scan of the same row in each of the other sets is supplied from the vertical scan part. Device. The method of claim 2, And the vertical scan line of the same kind is the recording scan line. The method of claim 2, The vertical scanning unit includes a driving scanning unit for switching the first potential used to supply the driving current to the electro-optical device and a second potential different from the first potential to supply the driving current to the power supply terminal of the driving transistor; , The vertical scanning line includes a plurality of power supply lines extending between the driving scanning unit and a power supply terminal of the driving transistors in each row; The same type of vertical scanning line is the power supply line. The method of claim 1, The control input terminal of the second sampling transistor is configured such that the vertical scan pulse for heterogeneous vertical scanning of the different rows of the different sets is supplied from the vertical scan unit to the control input terminal of the second sampling transistor. The display device is connected to the scanning line. The method of claim 1, The horizontal scanning unit sequentially switches the video signal for each column in synchronization with the vertical scanning by the vertical scanning unit, and supplies the video signal to the pixel circuit for each of the plurality of columns in which the video signal is commonly supplied. Supplying The vertical scanning unit vertically scans the first sampling transistor by the write driving pulse, and performs a display processing of any one column in which the video signal is shared in a group in which the video signal is commonly supplied. In all the display processing periods until the display processing of all the columns sharing the video signal is completed, the display processing is conducted by sequentially conducting any one of the second sampling transistors in synchronization with the conduction of the first sampling transistors. And the vertical scan pulses of the same kind or different kinds for the vertical scan, so as to be sequentially formed. The method of claim 6, The vertical scanning unit is configured to receive the same or different vertical scanning pulses for the vertical scanning such that all of the plurality of rows of the second sampling transistors except for being controlled to the conductive state are turned off within all the display processing periods. A display device, characterized in that the setting. The method of claim 6, The vertical scan section conducts both of the first and second sampling transistors in a vertical scan period in which the second sampling transistors do not need to be sequentially turned on, so that the vertical scanning is performed so that normal display processing is performed. A display device characterized by setting a pulse. The method of claim 6, And the vertical scanning unit sets the vertical scanning pulse so that the change state of the vertical scanning pulse is uniform in each row. The method of claim 6, And a drive signal constant circuit for keeping the drive current constant. The method of claim 10, The driving signal regularizing circuit may be provided at a time when a voltage corresponding to a first potential used to supply the driving current to the electro-optical element is supplied to a power supply terminal of the driving transistor and the image signal is a reference potential. And a threshold correction function for retaining the voltage corresponding to the threshold voltage of the driving transistor in the storage capacitor by conducting the first and second sampling transistors. The method of claim 10, The vertical scanning unit vertically scans the pixel circuit and supplies a write scanning pulse for writing information corresponding to the signal amplitude in the storage capacitor to a control input terminal of the first sampling transistor, and the driving current. A driving scan unit for switching the first potential used to supply the second to the electro-optical element and the second potential different from the first potential to supply the power to the power supply terminal of the driving transistor; The horizontal scanning unit supplies an image signal switched to a reference potential and a signal potential to the sampling transistor, In the driving signal constant circuit, under the control of the write scanning unit, the horizontal driving unit, and the driving scanning unit, a voltage corresponding to the first potential is supplied to the power supply terminal of the driving transistor, and an image signal is referenced. The display device is characterized in that the first and second sampling transistors are turned on at a potential time period to realize a threshold correction function for storing a voltage corresponding to a threshold voltage of the driving transistor in the storage capacitor. . The method of claim 10, And the drive signal constant circuit realizes a mobility correction function that suppresses the dependence of the drive current on the mobility of the drive transistor. The method of claim 13, The driving signal scheduling circuit is configured to perform the first and second second operation in a time period when the video signal has a signal potential after a threshold correction function of storing a voltage corresponding to a threshold voltage of the driving transistor in the storage capacitor. Both conducting sampling transistors realize the mobility correction function when writing information according to signal potential in the storage capacitor.

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