CN114863873B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114863873B CN114863873B CN202210473380.5A CN202210473380A CN114863873B CN 114863873 B CN114863873 B CN 114863873B CN 202210473380 A CN202210473380 A CN 202210473380A CN 114863873 B CN114863873 B CN 114863873B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
Abstract
The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a plurality of first signal lines and a plurality of demultiplexers; the demultiplexer comprises a first switch, a second switch and a third switch, wherein the input end of the first switch is electrically connected with the input end of the second switch, and the output end of the first switch and the output end of the second switch are respectively electrically connected with different first signal lines; the input end of the third switch receives the first reset voltage, and the output end of the third switch is electrically connected with the output end of the second switch; the first switch and the second switch are turned on sequentially, and the period of turning on the third switch at least partially overlaps with the period of turning on the first switch. According to the embodiment of the application, the data voltage transmitted by the first switch and the second switch can be more fully transmitted to the driving transistor of the corresponding pixel circuit, so that the accuracy of the luminous driving current generated by the driving transistor is improved, and the display effect of the display panel is improved.
Description
[ field of technology ]
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
[ background Art ]
An organic light-emitting diode (OLED) display panel has advantages of low power consumption, self-luminescence, wide viewing angle, wide temperature characteristics, fast response speed, and the like, and has wide application in the market.
In OLED display panels, a demultiplexer circuit is typically employed to transmit signals. However, the existing demultiplexer circuit and its timing sequence have the problem of inaccurate signal writing, which affects the normal display of the display panel.
[ MEANS FOR SOLVING PROBLEMS ]
In view of the foregoing, embodiments of the present application provide a display panel and a display device to solve the above technical problems.
In a first aspect, embodiments of the present application provide a display panel including a plurality of first signal lines and a plurality of demultiplexers; the demultiplexer comprises a first switch, a second switch and a third switch, wherein the input end of the first switch is electrically connected with the input end of the second switch, and the output end of the first switch and the output end of the second switch are respectively electrically connected with different first signal lines; the input end of the third switch receives the first reset voltage, and the output end of the third switch is electrically connected with the output end of the second switch; the first switch and the second switch are turned on sequentially, and the period of turning on the third switch at least partially overlaps with the period of turning on the first switch.
In one implementation of the first aspect, the period during which the third switch is turned on is the same as the period during which the first switch is turned on.
In an implementation manner of the first aspect, the control terminal of the third switch is connected to the same control signal line as the control terminal of the first switch.
In one implementation of the first aspect, the period in which the second switch is turned on does not overlap with the period in which the third switch is turned on.
In one implementation manner of the first aspect, the display panel further includes a pixel circuit, and the pixel circuit includes a driving transistor and a data voltage writing module; the driving transistor is used for generating light-emitting driving current, the input end of the data voltage writing module is electrically connected with the first signal line, the output end of the data voltage writing module is electrically connected with the driving transistor, and the control end of the data voltage writing module is electrically connected with the first scanning line; when the first scanning line controls the data voltage writing module to be started, the data voltage writing module transmits the data voltage on the first signal line; when the first switch and the second switch are respectively opened, the data voltage is sequentially provided for the first signal line which is electrically connected with the first switch and the second switch.
The at least two pixel circuits electrically connected with the same first scanning line comprise a first pixel circuit and a second pixel circuit, wherein the first pixel circuit is electrically connected with the first switch through a first signal line electrically connected with the first pixel circuit, and the second pixel circuit is electrically connected with the second switch and the third switch through a first signal line electrically connected with the second pixel circuit.
In one implementation manner of the first aspect, a period during which the second switch supplies the data voltage to the second pixel circuit through the first signal line is located within a period during which the data voltage writing module in the second pixel circuit is turned on.
In one implementation manner of the first aspect, the second switch starts to supply the data voltage to the second pixel circuit through the first signal line at a time later than a time at which the data voltage writing module in the second pixel circuit starts to turn on.
In an implementation manner of the first aspect, the pixel circuit further includes a reset module, an output terminal of the reset module is electrically connected to the gate of the driving transistor, and is configured to transmit the second reset voltage to the gate of the driving transistor;
wherein the potential of the first reset voltage is not greater than the potential of the second reset voltage.
In an implementation manner of the first aspect, a time when the data voltage writing module starts to turn on in the second pixel circuit is not earlier than a time when the third switch electrically connected thereto is turned on.
In an implementation manner of the first aspect, an input terminal of the reset module is electrically connected to an input terminal of the third switch.
In one implementation manner of the first aspect, the first pixel circuit is electrically connected to the first color light emitting device, and the second pixel circuit is electrically connected to the second color light emitting device; the charging efficiency of the second color light emitting device is smaller than the charging efficiency of the first color light emitting device.
In a second aspect, embodiments of the present application provide a display device including a display panel as provided in the first aspect.
In this embodiment of the present application, the period during which the third switch is turned on is set to at least partially overlap with the period during which the first switch is turned on, and then, before the second switch is turned on, the first signal line electrically connected to the second switch receives the first reset voltage. Since the first reset voltage does not affect the magnitude of the light-emitting driving current generated by the driving transistor, the first scan line can transmit the on signal in advance, so that the pulse width of the on signal transmitted by the first scan line can be set larger in the scan period of one row of pixel circuits. The data voltage transmitted by the first switch and the second switch is more fully transmitted to the driving transistor of the corresponding pixel circuit, the accuracy of the luminous driving current generated by the driving transistor is improved, and the display effect of the display panel is further improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a display panel in the prior art;
FIG. 2 is a timing diagram of the display panel of FIG. 1;
fig. 3 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 4 is a timing diagram of the display panel shown in FIG. 3;
FIG. 5 is a timing diagram of the display panel of FIG. 3;
FIG. 6 is a schematic diagram of another display panel according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of a pixel circuit according to an embodiment of the present application;
FIG. 8 is a schematic diagram of yet another pixel circuit according to an embodiment of the present disclosure;
FIG. 9 is a timing diagram of the display panel of FIG. 3;
FIG. 10 is a timing diagram of the display panel of FIG. 3;
FIG. 11 is a schematic diagram of another display panel according to an embodiment of the disclosure;
fig. 12 is a schematic diagram of a display device according to an embodiment of the present application.
[ detailed description ] of the invention
For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and examples herein refer to values that are generally agreed upon, rather than exact, within reasonable process operating ranges or tolerances.
It should be understood that although the terms first, second, etc. may be used in embodiments of the present application to describe switches, pixel circuits, etc., these switches, pixel circuits, etc. should not be limited to these terms. These terms are only used to distinguish switches, pixel circuits, etc. from one another. For example, a first switch may also be referred to as a second switch, and similarly, a second switch may also be referred to as a first switch, without departing from the scope of embodiments of the present application.
Fig. 1 is a schematic structural diagram of a display panel in the prior art, and fig. 2 is a timing diagram of the display panel shown in fig. 1.
As shown in fig. 1, in the related art, a display panel 100 'includes a plurality of pixel circuits 001' arrayed in a first direction X and a second direction Y, and the pixel circuits 001 'are used to drive light emitting devices (not shown in fig. 1) in the display panel 100' to emit light.
The display panel 100' further includes a plurality of first signal lines DL1' and a plurality of first scan lines S1'. The first signal lines DL1 'extend along the second direction Y, and the plurality of first signal lines DL1' are arranged along the first direction X. The first scan lines S1 'extend along the first direction X, and the plurality of first scan lines S1' are arranged along the second direction. The pixel circuits 001 'arranged along the first direction X may be electrically connected to the same first scan line S1', and the pixel circuits 001 'arranged along the second direction Y may be electrically connected to the same first signal line DL1'.
Alternatively, the first signal line DL1 'is used to transmit the data voltage Vdata to the pixel circuit 001', i.e., the first signal line DL1 'may be a data signal line in the display panel 100'.
The first scanning line S1 'is a control signal line for driving the pixel circuit 001'. Alternatively, the first scan line S1 'is a signal line for controlling whether the data voltage Vdata transmitted by the first signal line DL1' can be transmitted to the driving transistor. The driving transistor is a portion for generating a light emission driving current in the pixel circuit 001'.
The display panel 100' employs a demultiplexer Q ' to transmit signals to the first signal line DL1'. Specifically, the demultiplexer Q ' includes one input terminal Q1' and two output terminals Q2', and the two output terminals Q2' are electrically connected to different first signal lines DL1', respectively. In addition, the demultiplexer Q ' further includes a first switch T1' and a second switch T2', and the input terminal of the first switch T1' and the input terminal of the second switch T2' are electrically connected to the input terminal Q1' of the demultiplexer Q '. The output terminal of the first switch T1 'is electrically connected to one output terminal Q2' of the demultiplexer Q ', and the output terminal of the second switch T2' is electrically connected to the other output terminal Q2 'of the demultiplexer Q'. That is, the output terminal of the first switch T1' and the output terminal of the second switch T2' are electrically connected to different first signal lines DL1', respectively.
The control end of the first switch T1 'is electrically connected to the first control line CK1', and the control end of the second switch T2 'is electrically connected to the second control line CK 2'. In the operation process of the demultiplexer Q ', the first switch T1' and the second switch T2 'are turned on sequentially, and signals received by the input terminal Q1' of the demultiplexer Q 'are respectively transmitted to different first signal lines DL1'.
Referring to fig. 1 and 2, in the prior art, in order to ensure the accuracy of the signal received by the driving transistor in the pixel circuit 001', in the scanning period T' of one row of the pixel circuit 001', the first switch T1' and the second switch T2 'are generally set to be turned on in sequence, and then the first scanning line S1' transmits the turn-on signal. This results in narrower pulse width of the on signal transmitted by the first scan line S1', and shorter time for transmitting the signals transmitted by the first switch T1' and the second switch T2' to the driving transistor of the corresponding pixel circuit 001', so that the signals transmitted by the first switch T1' and the second switch T2' cannot be sufficiently transmitted to the driving transistor of the corresponding pixel circuit 001', thereby affecting the normal display of the display panel. Particularly in the high-frequency driving mode, the influence on the display screen is very remarkable.
The applicant has provided a solution to the problems existing in the prior art by intensive studies.
Fig. 3 is a schematic diagram of a display panel according to an embodiment of the present application, fig. 4 is a timing chart of the display panel shown in fig. 3, and fig. 5 is a timing chart of the display panel shown in fig. 3.
The embodiment of the application provides a display panel 100, as shown in fig. 3, the display panel 100 includes a plurality of first signal lines DL1 and a plurality of demultiplexers Q. The first signal lines DL1 extend along the second direction Y, and the plurality of first signal lines DL1 are arranged along the first direction, and the first signal lines DL1 are electrically connected to the pixel circuits 001 in the display panel 100.
The demultiplexer Q includes a first switch T1, a second switch T2, and a third switch T3, and an input terminal of the first switch T1 is electrically connected to an input terminal of the second switch T2 and is electrically connected to a first input terminal Q1 of the demultiplexer Q. The output ends of the first switch T1 and the second switch T2 are respectively electrically connected with different first signal lines DL1, that is, the output ends of the first switch T1 and the second switch T2 can respectively serve as an output end Q2 of the demultiplexer Q to transmit signals to the first signal lines DL1 electrically connected therewith.
Alternatively, the first switch T1 and the second switch T2 are used to transmit the data voltage Vdata to the first signal line DL 1. At this time, the first signal line DL1 may be a data signal line for transmitting the received data voltage Vdata to the pixel circuit 001.
The input end of the third switch T3 receives the first reset voltage V1, and the output end of the third switch T3 is electrically connected with the output end of the second switch T2. That is, the third switch T3 is used to transmit the first reset voltage V1 to the first signal line DL1 to which the second switch T2 is electrically connected.
The first switch T1 and the second switch T2 are turned on sequentially, and a period of turning on the third switch T3 at least partially overlaps a period of turning on the first switch T1.
Specifically, referring to fig. 3 and 4, the control end of the first switch T1 is electrically connected to the first control line CK1, the control end of the second switch T2 is electrically connected to the second control line CK2, and the control end of the third switch T3 is electrically connected to the third control line CK 3.
In the scanning period T of one row of the pixel circuits 001, the first control line CK1 and the second control line CK2 transmit effective signals to control the first switch T1 and the second switch T2 to be turned on sequentially, and after the first switch T1 is turned off, the second switch T2 is turned on. The third control line CK3 transmits an active signal to control the third switch T3 to be turned on in a period at least partially overlapping with the period in which the first switch T1 is turned on, and the period in which the second switch T2 is turned on does not overlap with the period in which the third switch T3 is turned on. That is, the third switch T3 is turned off before the second switch T2 is turned on.
Alternatively, as shown in fig. 4, a period in which the third switch T3 starts partially overlaps with a period in which the first switch T1 is turned on.
Alternatively, as shown in fig. 5, the period in which the third switch T3 is turned on is the same as the period in which the first switch T1 is turned on.
It should be noted that, the first switch T1, the second switch T2, and the third switch T3 may be P-type transistors. Of course, at least one of the first switch T1, the second switch T2 and the third switch T3 may be an N-type transistor.
The display panel 100 further includes a first scan line S1, where the first scan line S1 extends along a first direction X, and the plurality of first scan lines S1 are arranged along a second direction Y. The plurality of pixel circuits 001 arranged along the first direction X may be electrically connected to the same first scan line S1, i.e., one row of pixel circuits 001 may share the same first scan line S1. The first scan line S1 is used to control the data voltage Vdata transmitted by the first signal line DL1 to be transmitted to a driving transistor (not shown in fig. 3) in the pixel circuit 001, which is a portion of the pixel circuit 001 that generates the light emission driving current.
It can be understood that, in the scanning period T of each row of the pixel circuits 001, the first switch T1 and the second switch T2 each transmit the data voltage Vdata to the first signal line DL1 electrically connected thereto. In this embodiment of the present application, the first reset voltage V1 may reset the data voltage Vdata of the pixel circuit 001 of the previous row transmitted by the first signal line DL1 electrically connected to the second switch T2, so as to avoid writing the data voltage Vdata of the pixel circuit 001 of the previous row transmitted by the first signal line DL1 into the driving transistor of the pixel circuit 001 of the current row. Further, the first reset voltage V1 does not drive the driving transistor to generate the light emission driving current, which makes it possible to advance the timing of transmitting the on signal of the first scan line S1.
Alternatively, the potential of the first reset voltage V1 is a negative value. For example, the potential of the first reset voltage V1 is-7V or-5V.
In this embodiment, in the scanning period T of one row of pixel circuits 001, the period in which the third switch T3 is turned on is set to at least partially overlap with the period in which the first switch T1 is turned on, so that before the second switch T2 is turned on, the first signal line DL1 electrically connected to the second switch T2 receives the first reset voltage V1, which is equivalent to resetting the first signal line DL 1. Since the first reset voltage V1 does not drive the driving transistor to generate the light-emitting driving current, the first scan line S1 may transmit the on signal in advance, so that the pulse width of the on signal transmitted by the first scan line S1 may be set larger in the scan period T of one row of the pixel circuits 001, and the time for transmitting the data voltage Vdata transmitted by the first switch T1 and the second switch T2 into the driving transistor of the corresponding pixel circuit 001 is increased. The data voltage Vdata transmitted by the first switch T1 and the second switch T2 is sufficiently transmitted to the driving transistor corresponding to the pixel circuit 001, so as to improve the accuracy of the light-emitting driving current generated by the driving transistor Td, and further improve the display effect of the display panel 100.
Fig. 6 is a schematic diagram of another display panel according to an embodiment of the present application.
In an embodiment of the present application, the control end of the third switch T3 is connected to the same control signal line as the control end of the T1 of the first switch, as shown in fig. 6, the control end of the third switch T3 and the control end of the T1 of the first switch may be electrically connected to the first control line CK1, and the signal transmitted by the first control line CK1 controls the switching states of the first switch T1 and the third switch T3 to be the same.
The embodiment of the application can reduce the number of the control lines of the switch in the demultiplexer Q, is beneficial to simplifying the design of the peripheral driving circuit and reduces the design difficulty of the peripheral driving circuit.
Fig. 7 is a schematic diagram of a pixel circuit according to an embodiment of the present application.
In one embodiment of the present application, please refer to fig. 3 and 7, the display panel 100 further includes a pixel circuit 001, and the pixel circuit 001 includes a driving transistor Td and a data voltage writing module 11. The driving transistor Td is used for generating a light emission driving current; the input terminal 111 of the data voltage writing module 11 is electrically connected to the first signal line DL1, the output terminal 112 of the data voltage writing module 11 is electrically connected to the driving transistor Td, and the control terminal 113 of the data voltage writing module 11 is electrically connected to the first scan line S1.
When the first scan line S1 controls the data voltage writing module 11 to be turned on, the data voltage writing module 11 transmits the data voltage Vdata on the first signal line DL1, that is, the data voltage Vdata on the first signal line DL1 is transmitted to the driving transistor Td through the turned-on data voltage writing module 11. When the first switch T1 and the second switch T2 are turned on, the data voltage Vdata is sequentially supplied to the first signal line DL1 electrically connected to the first switch T1 and the second switch T2.
That is, the first and second switches T1 and T2 are used to transmit the data voltage Vdata to the first signal line DL1 electrically connected thereto.
For example, as shown in fig. 3, the first signal line DL1 includes a first sub-signal line DL11 and a second sub-signal line DL12, the first sub-signal line DL11 is electrically connected to the first switch T1, and the second sub-signal line DL12 is electrically connected to the second switch T2. When the first switch T1 is turned on, the first switch T1 transmits the data voltage Vdata to the first sub-signal line DL 11; when the second switch T2 is turned on, the second switch T2 transmits the data voltage Vdata to the second sub-signal line DL 12.
With continued reference to fig. 3, at least two pixel circuits 001 electrically connected to the same first scan line S1 include a first pixel circuit 10 and a second pixel circuit 20. The first pixel circuit 10 is electrically connected to the first switch T1 through the electrically connected first signal line DL1, that is, the first pixel circuit 10 is electrically connected to the first switch T1 through the electrically connected first sub-signal line DL 11. The second pixel circuit 20 is electrically connected to the second switch T2 and the third switch T3 through the electrically connected first signal line DL1, that is, the second pixel circuit 20 is electrically connected to the second switch T2 and the third switch T3 through the electrically connected second sub-signal line DL 12.
In the embodiment of the present application, the first switch T1 is electrically connected to the first pixel circuit 10 through the first sub-signal line DL11, and the second switch T2 and the third switch T3 are electrically connected to the second pixel circuit 20 through the second sub-signal line DL 12. The first pixel circuit 10 and the second pixel circuit 20 are electrically connected to the same first scan line S1, that is, the control terminal 113 of the data voltage writing module 11 in the first pixel circuit 10 and the second pixel circuit 20 is electrically connected to the same first scan line S1. The signal transmitted by the first scan line S1 controls the data voltage writing module 11 in the first pixel circuit 10 and the second pixel circuit 20 to be turned on or off simultaneously.
When the first switch T1 is turned on, the first switch T1 transmits the data voltage Vdata to the first sub-signal line DL11, that is, the input terminal 111 of the data voltage writing module 11 in the first pixel circuit 10 receives the data voltage Vdata. When the second switch T2 is turned on, the second switch T2 transmits the data voltage Vdata to the second sub-signal line DL12, that is, the input terminal 111 of the data voltage writing module 11 in the second pixel circuit 20 receives the data voltage Vdata. When the third switch T3 is turned on, the third switch T3 transmits the first reset voltage V1 to the second sub-signal line DL12, that is, the input terminal 111 of the data voltage writing module 11 in the second pixel circuit 20 receives the first reset voltage V1.
In the scanning period T of the row of the pixel circuits 001 where the first pixel circuit 10 and the second pixel circuit 20 are located, since the period during which the first switch T1 is turned on is earlier than the period during which the second switch T2 is turned on, and the period during which the third switch T3 is turned on at least partially overlaps with the period during which the first switch T1 is turned on, the third switch T3 is turned on before the second switch T2 is turned on. In the scan period T, the first sub-signal line DL11 receives the data voltage Vdata, and the second sub-signal line DL12 receives the first reset voltage V1 and then the data voltage Vdata. The data voltage writing module 11 in the first pixel circuit 10 and the second pixel circuit 20 needs to transmit the data voltage Vdata on the first sub-signal line DL11 and the data voltage Vdata on the second sub-signal line DL12 to the driving transistor Td in the respective pixel circuits, respectively.
Since the first reset voltage V1 is transmitted to the driving transistor Td, the driving current generated by the driving transistor Td in the subsequent stage is not affected. Therefore, the data voltage writing module 11 in the second pixel circuit 20 does not need to be turned on after the second sub-signal line DL12 receives the data voltage Vdata, i.e. the first scan line S1 does not need to transmit the turn-on signal after the second sub-signal line DL12 receives the data voltage Vdata.
The first scan line S1 may transmit the on signal in advance, so that the pulse width of the on signal transmitted by the first scan line S1 is set larger in the scan period T of one row of pixel circuits, the time for transmitting the data voltage Vdata on the first sub-signal line DL11 and the data voltage Vdata on the second sub-signal line DL12 to the driving transistor Td in the respective pixel circuits is increased, so that the data voltage Vdata can be more fully written into the driving transistor Td, the accuracy of the light-emitting driving current generated by the driving transistor Td is improved, and the display effect of the display panel 100 is further improved.
With continued reference to fig. 7, in one embodiment of the present application, the pixel circuit 001 further includes a reset module 12, the input terminal 121 of the reset module 12 receives the second reset voltage V2, the output terminal 122 is electrically connected to the gate of the driving transistor Td, and the reset module 12 is configured to transmit the second reset voltage V2 to the gate of the driving transistor Td.
Wherein the potential of the first reset voltage V1 is not greater than the potential of the second reset voltage V2.
The operation principle that the first reset voltage V1 does not drive the driving transistor Td to generate the light emission driving current is described below.
As shown in fig. 7, the output terminal 112 of the data voltage writing module 11 is electrically connected to the source of the driving transistor Td. To ensure the response speed of the driving transistor Td, the driving transistor Td is usually a P-type transistor. It can be understood that, in the embodiment of the present application, the period in which the reset module 12 is turned on is earlier than the period in which the data voltage writing module 11 is turned on, that is, when the source of the driving transistor Td receives the first reset voltage V1, the potential of the gate of the driving transistor Td is the second reset voltage V2. Since the potential of the first reset voltage V1 is not greater than the potential of the second reset voltage V2, the driving transistor Td is not turned on. At this time, the first reset voltage V1 is not transmitted to the gate of the driving transistor Td. The gate potential of the driving transistor Td is still the second reset voltage V2. When the source of the driving transistor Td receives the data voltage Vdata, the driving transistor Td is turned on because the potential of the data voltage Vdata is greater than the potential of the second reset voltage V2. At the same time, the threshold voltage grabbing transistor Md connected between the gate and the drain of the driving transistor Td is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Td. The driving transistor Td generates a light emitting driving current corresponding to the data voltage Vdata at a subsequent stage.
Therefore, in the embodiment of the present application, the setting of the first reset voltage V1 does not drive the driving transistor Td to generate the light-emitting driving current, which is beneficial to increasing the pulse width of the on signal transmitted by the first scan line S1.
In one embodiment of the present application, please continue to refer to fig. 7, the data voltage writing module 11 includes a first transistor M1, wherein a source of the first transistor M1 is electrically connected to the input terminal 111 of the data voltage writing module 11, a drain of the first transistor M1 is electrically connected to the output terminal 112 of the data voltage writing module 11, and a gate of the first transistor M1 is electrically connected to the control terminal 113 of the data voltage writing module 11. The reset module 12 includes a second transistor M2, where a source of the second transistor M2 is electrically connected to the input terminal 121 of the reset module 12, a drain of the second transistor M is electrically connected to the output terminal 122 of the reset module 12, and a gate of the second transistor M2 is electrically connected to the control terminal 123 of the reset module 12. The source of the threshold voltage grabbing transistor Md is electrically connected to the drain of the driving transistor Td, and the drain is electrically connected to the gate of the driving transistor Td.
In addition, the pixel circuit 001 further includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a capacitor C1, wherein a source of the third transistor M3 receives the second reset voltage V2, and a drain of the third transistor M3 is electrically connected to an input terminal of the light emitting device 002. The source of the fourth transistor M4 receives the power supply voltage VDD, and the drain of the fourth transistor M4 is electrically connected to the source of the driving transistor Td. The source of the fifth transistor M5 is electrically connected to the drain of the driving transistor Td, the drain is electrically connected to the input terminal of the light emitting element 002, and the gate of the fourth transistor M4 and the gate of the fifth transistor M5 are electrically connected to the light emission control signal line EM. One plate of the capacitor C1 receives the power supply voltage VDD, and the other plate is electrically connected to the gate of the driving transistor Td.
The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the threshold voltage grabbing transistor Md may be P-type transistors. Of course, any one of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the threshold voltage grabbing transistor Md may be an N-type transistor.
Fig. 8 is a schematic diagram of still another pixel circuit according to an embodiment of the present application.
In one embodiment of the present application, the input terminal 121 of the reset module 12 is electrically connected to the input terminal of the third switch T3, that is, as shown in fig. 8, the input terminal 121 of the reset module 12 receives the first reset voltage V1, and the reset module 12 may transmit the first reset voltage V1 to the gate of the driving transistor Td.
In the embodiment of the present application, the first reset voltage V1 is multiplexed into the second reset voltage V2, which is beneficial to reducing the number of reset signal lines in the display panel 100 and simplifying the manufacturing process of the display panel 100.
Fig. 9 is a timing diagram of the display panel shown in fig. 3, and fig. 10 is a timing diagram of the display panel shown in fig. 3.
Referring to fig. 3, 4 and 7, in one embodiment of the present application, a period of providing the data voltage Vdata to the second pixel circuit 20 through the first signal line DL1 by the second switch T2 is within a period of turning on the data voltage writing module 11 in the second pixel circuit 20.
That is, the period in which the second control line CK2 transmits the on signal is located in the period in which the first scan line S1 transmits the on signal.
For example, taking the second switch T2 and the first transistor M1 as P-type transistors as an example, as shown in fig. 4, the period in which the second control line CK2 transmits the low level signal is located in the period in which the first scan line S1 transmits the low level signal.
Alternatively, referring to fig. 3, 7 and 9, the timing at which the second switch T2 starts to supply the data voltage Vdata to the second pixel circuit 20 through the first signal line DL1 is later than the timing at which the data voltage writing module 11 in the second pixel circuit 20 starts to turn on. I.e., the timing at which the second control line CK2 starts transmitting the on signal is later than the timing at which the first scan line S1 starts transmitting the on signal.
For example, taking the second switch T2 and the first transistor M1 as P-type transistors as an example, as shown in fig. 9, the timing when the second control line CK2 starts transmitting the low level signal is later than the timing when the first scan line S1 starts transmitting the low level signal. I.e., the falling edge of the second control line CK2 transmission signal is later than the falling edge of the first scan line S1 transmission signal.
Further, as shown in fig. 10, the period in which the first scan line S1 transmits the on signal may also overlap with the period in which the first control line CK1 transmits the on signal. Only the timing at which the first scan line S1 starts transmitting the on signal is required to be later than the timing at which the first control line CK1 starts transmitting the on signal.
The embodiment of the application increases the duration of the first scan line S1 transmitting the on signal, and increases the time for transmitting the data voltage Vdata to the driving transistor Td. So that the data voltage Vdata can be more sufficiently written into the driving transistor Td, it is advantageous to improve the accuracy of the light emitting driving current generated by the driving transistor Td, thereby improving the display effect of the display panel 100. Moreover, when the second switch T2 transmits the data voltage Vdata, the data voltage writing module 11 in the second pixel circuit 20 is in the on state, so that the efficiency of writing the data voltage Vdata transmitted by the second switch into the driving transistor in the second pixel circuit 20 can be greatly improved.
In one embodiment of the present application, please refer to fig. 3, 7 and 10, the time when the data voltage writing module 11 starts to turn on in the second pixel circuit 20 is not earlier than the time when the third switch T3 electrically connected thereto is turned on.
That is, in the first scan line S1 and the third switch T3 electrically connected to the same second pixel circuit 20, the timing at which the first scan line S1 starts transmitting the on signal is not earlier than the timing at which the third switch T3 is turned on, that is, the timing at which the first scan line S1 starts transmitting the on signal is not earlier than the timing at which the third control line CK3 starts transmitting the on signal.
For example, taking the first transistor M1 and the third switch T3 as P-type transistors as an example, as shown in fig. 10, the timing at which the first scan line S1 starts transmitting the low level signal is not earlier than the timing at which the third control line CK3 starts transmitting the low level signal.
Fig. 10 only shows that the timing at which the first scan line S1 starts transmitting the low level signal is later than the timing at which the third control line CK3 starts transmitting the low level signal. The timing at which the first scan line S1 starts transmitting the low level signal may also be the same as the timing at which the third control line CK3 starts transmitting the low level signal.
In this embodiment of the present application, the time when the first scan line S1 starts transmitting the on signal is not earlier than the time when the third control line CK3 starts transmitting the on signal, so that when the data voltage writing module 11 in the second pixel circuit 20 is turned on, the voltage on the first signal line DL1 electrically connected to the second pixel circuit 20 is ensured to be the first reset voltage V1, so that the data voltage Vdata transmitted by the first signal line DL1 in the previous stage is prevented from being written into the driving transistor Td again, and the accuracy of the data voltage Vdata received by the driving transistor Td in the second pixel circuit 20 in the present stage is ensured.
Fig. 11 is a schematic view of another display panel according to an embodiment of the present application.
As shown in fig. 11, in one embodiment of the present application, the first pixel circuit 10 is electrically connected to the first color light emitting device 21, the second pixel circuit 20 is electrically connected to the second color light emitting device 22, and the charging efficiency of the second color light emitting device 22 is smaller than that of the first color light emitting device 21.
Wherein, the smaller the charging efficiency, the longer the charging time of the color light emitting device before entering the stable light emitting stage.
In the present embodiment, the charging efficiency of the second color light emitting device 22 is smaller than that of the first color light emitting device 21. That is, the charging period before the second color light emitting device 22 enters the steady light emitting period is longer than the charging period before the first color light emitting device 21 enters the steady light emitting period.
Alternatively, the second color light emitting device 22 is a green light emitting device, and the first color light emitting device 21 is a red light emitting device or a blue light emitting device.
It can be understood that, in the scanning period T of one row of the pixel circuits 001, since the first pixel circuit 10 receives the data voltage Vdata before the second pixel circuit 20, after the pulse width of the first scanning line S1 transmission on signal is increased, the effect of increasing the efficiency of the driving transistor Td in the second pixel circuit 20 to receive the data voltage Vdata is greater than the effect of increasing the efficiency of the driving transistor Td in the first pixel circuit 10 to receive the data voltage Vdata.
In this embodiment, the second pixel circuit 20 is electrically connected with the second color light emitting device 22 with smaller charging efficiency, so that the accuracy of the light emitting driving current received by the second color light emitting device 22 can be greatly improved, and the accuracy of the brightness of the second color light emitting device 22 is greatly improved, and the color cast is reduced.
Fig. 12 is a schematic diagram of a display device according to an embodiment of the present application.
The embodiment of the application provides a display device 200, as shown in fig. 12, where the display device 200 includes the display panel 100 provided in the above embodiment. The display device 200 provided in the embodiment of the present application may be a mobile phone. In addition, the display device 200 provided in the embodiment of the present application may be an electronic product such as a computer or a television.
In the display device 200, in the scanning period T of one row of the pixel circuits 001, the period in which the third switch T3 is turned on and the period in which the first switch T1 is turned on are set to at least partially overlap, and before the second switch T2 is turned on, the first signal line DL1 electrically connected to the second switch T2 receives the first reset voltage V1, which is equivalent to resetting the first signal line DL 1. Since the first reset voltage V1 does not affect the magnitude of the light-emitting driving current generated by the driving transistor, the first scan line S1 may transmit the on signal in advance, so that the pulse width of the on signal transmitted by the first scan line S1 may be set larger in the scan period T of one row of the pixel circuits 001. The data voltage Vdata transmitted by the first switch T1 and the second switch T2 is more fully transmitted to the driving transistor corresponding to the pixel circuit 001, so as to improve the accuracy of the light-emitting driving current generated by the driving transistor Td, and further improve the display effect of the display panel 100.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (11)
1. A display panel, comprising:
a plurality of first signal lines;
the demultiplexer comprises a first switch, a second switch and a third switch, wherein the input end of the first switch is electrically connected with the input end of the second switch, and the output end of the first switch and the output end of the second switch are respectively electrically connected with different first signal lines; the input end of the third switch receives a first reset voltage, and the output end of the third switch is electrically connected with the output end of the second switch;
the plurality of pixel circuits comprise first pixel circuits and second pixel circuits which are in the same row, the first pixel circuits are electrically connected with the first switch through the first signal lines, and the second pixel circuits are electrically connected with the second switch and the third switch through the first signal lines;
the first switch and the second switch are turned on sequentially, and the period of turning on the third switch at least partially overlaps with the period of turning on the first switch;
the first pixel circuit is electrically connected with the first color light emitting device, the second pixel circuit is electrically connected with the second color light emitting device, and the charging efficiency of the second color light emitting device is smaller than that of the first color light emitting device.
2. The display panel according to claim 1, wherein a period in which the third switch is turned on is the same as a period in which the first switch is turned on.
3. The display panel according to claim 2, wherein a control terminal of the third switch is connected to the same control signal line as a control terminal of the first switch.
4. The display panel of claim 1, wherein the period in which the second switch is on does not overlap the period in which the third switch is on.
5. The display panel according to claim 1, wherein the pixel circuit comprises:
a driving transistor for generating a light emission driving current;
the input end of the data voltage writing module is electrically connected with the first signal line, the output end of the data voltage writing module is electrically connected with the driving transistor, and the control end of the data voltage writing module is electrically connected with the first scanning line;
when the first scanning line controls the data voltage writing module to be started, the data voltage writing module transmits the data voltage on the first signal line; when the first switch and the second switch are respectively opened, the data voltage is sequentially provided for the first signal line which is electrically connected with the first switch and the second switch.
6. The display panel according to claim 5, wherein a period during which the second switch supplies the data voltage to the second pixel circuit through the first signal line is within a period during which the data voltage writing module in the second pixel circuit is turned on.
7. The display panel according to claim 6, wherein a timing at which the second switch starts supplying the data voltage to the second pixel circuit through the first signal line is later than a timing at which the data voltage writing module in the second pixel circuit starts turning on.
8. The display panel of claim 5, wherein the pixel circuit further comprises a reset module having an output electrically connected to the gate of the drive transistor for transmitting a second reset voltage to the gate of the drive transistor;
wherein the potential of the first reset voltage is not greater than the potential of the second reset voltage.
9. The display panel according to claim 8, wherein the data voltage writing module in the second pixel circuit starts to turn on at a timing not earlier than a timing at which the third switch electrically connected thereto is turned on.
10. The display panel of claim 8, wherein an input of the reset module is electrically connected to an input of the third switch.
11. A display device comprising a display panel as claimed in any one of claims 1-10.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106469547A (en) * | 2015-08-21 | 2017-03-01 | 三星显示有限公司 | Demultiplexer, display device and the method for driving this display device |
| CN111613183A (en) * | 2020-05-28 | 2020-09-01 | 昆山国显光电有限公司 | Display panel, driving method of display panel and display device |
| CN114299865A (en) * | 2021-12-31 | 2022-04-08 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100796136B1 (en) * | 2006-09-13 | 2008-01-21 | 삼성에스디아이 주식회사 | Organic electro luminescence display device and driving method for the same |
| JP2009122231A (en) * | 2007-11-13 | 2009-06-04 | Sony Corp | Display device and method for driving the display device |
| KR101473844B1 (en) * | 2012-09-28 | 2014-12-17 | 엘지디스플레이 주식회사 | Organic Light-Emitting Diode Display DEVICE |
| CN105810143B (en) * | 2014-12-29 | 2018-09-28 | 昆山工研院新型平板显示技术中心有限公司 | A kind of data drive circuit and its driving method and organic light emitting display |
| CN105761675B (en) * | 2016-05-18 | 2018-03-20 | 上海天马微电子有限公司 | Organic electroluminescence display panel and its driving method, organic light-emitting display device |
| KR102605050B1 (en) * | 2017-02-21 | 2023-11-23 | 삼성디스플레이 주식회사 | Driving Method For Display Device |
| KR102459706B1 (en) * | 2017-09-13 | 2022-10-28 | 엘지디스플레이 주식회사 | Organic Light Emitting Display Using a Multiplexer |
| KR101949222B1 (en) * | 2017-10-20 | 2019-02-18 | 엘지디스플레이 주식회사 | Light emitting display device and method for driving the same |
| CN108630146B (en) * | 2018-05-14 | 2019-11-12 | 上海天马有机发光显示技术有限公司 | Driving method, organic light emitting display panel and the display device of array substrate |
| CN108682399B (en) * | 2018-05-21 | 2020-03-06 | 京东方科技集团股份有限公司 | Display device, pixel driving circuit and driving method thereof |
| KR20200072769A (en) * | 2018-12-13 | 2020-06-23 | 엘지디스플레이 주식회사 | Flat Panel display device |
| CN110599941A (en) * | 2019-09-23 | 2019-12-20 | 京东方科技集团股份有限公司 | Display panel, driving method and display device |
| KR20210059391A (en) * | 2019-11-15 | 2021-05-25 | 엘지디스플레이 주식회사 | Organic light emitting diode display device and driving method thereof |
| CN112435628B (en) * | 2020-12-17 | 2021-12-28 | 武汉天马微电子有限公司 | Display panel, display control method thereof, duty ratio adjusting method and display device |
-
2022
- 2022-04-29 CN CN202210473380.5A patent/CN114863873B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106469547A (en) * | 2015-08-21 | 2017-03-01 | 三星显示有限公司 | Demultiplexer, display device and the method for driving this display device |
| CN111613183A (en) * | 2020-05-28 | 2020-09-01 | 昆山国显光电有限公司 | Display panel, driving method of display panel and display device |
| CN114299865A (en) * | 2021-12-31 | 2022-04-08 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
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