CN116524866A

CN116524866A - Display panel and display device

Info

Publication number: CN116524866A
Application number: CN202310484558.0A
Authority: CN
Inventors: 匡建; 张蒙蒙; 周星耀; 高娅娜
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-08-01

Abstract

The embodiment of the application provides a display panel and a display device, wherein a pixel circuit in the display panel comprises a driving transistor and a data writing module, wherein the input end of the data writing module is electrically connected with a first signal line, and the output end of the data writing module is electrically connected with the driving transistor; the working process of displaying one frame of picture by the display panel comprises a first stage and n second stages, wherein n is more than or equal to 2; the first stage comprises a data writing stage and a light emitting stage, and the second stage comprises a regulating stage and a light emitting stage; the data writing module is started in a data writing stage and an adjusting stage, the first signal line transmits data voltage in the data writing stage, and transmits adjusting voltage in the adjusting stage; in the second phase with different light-emitting periods, the adjusting voltage transmitted by the first signal line is different. The bias states of the driving transistors in different second stages can be differently corrected, so that the light-emitting brightness of each second stage is basically the same as that of the first stage, and the flicker problem of the display panel is improved.

Description

Display panel and display device

[ field of technology ]

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

[ background Art ]

In the display panel, a pixel circuit for controlling light emission of the light emitting device is a core technical content of the display panel, and has important research significance.

In the existing pixel circuit, due to the working characteristics of the driving transistor, the display panel has larger brightness fluctuation in the process of displaying one frame of picture, and the display effect is seriously affected. Thus, a solution is needed.

[ MEANS FOR SOLVING PROBLEMS ]

In view of this, the embodiments of the present application provide a display panel and a display device.

In a first aspect, an embodiment of the present application provides a display panel, including a pixel circuit and a light emitting device that are electrically connected, where the pixel circuit includes a driving transistor and a data writing module, the driving transistor is used to generate a light emitting driving current, an input end of the data writing module is electrically connected to a first signal line, and an output end of the data writing module is electrically connected to the driving transistor; the working process of displaying one frame of picture by the display panel comprises a first stage and n second stages which are carried out after the first stage, wherein n is more than or equal to 2; the first phase includes a data writing phase and a light emitting phase performed after the data writing phase, and the second phase includes a conditioning phase and a light emitting phase performed after the conditioning phase; the data writing module is started in a data writing stage and an adjusting stage, the first signal line transmits data voltage in the data writing stage, and transmits adjusting voltage in the adjusting stage; in the second phase with different light-emitting periods, the adjusting voltage transmitted by the first signal line is different.

In a second aspect, embodiments of the present application provide a display device including a display panel as provided in the first aspect.

In the embodiment of the application, in the adjusting stage of the second stage, the adjusting voltage transmitted by the first signal line can be transmitted to the driving transistor through the turned-on data writing module so as to correct the bias state of the driving transistor, which is favorable for reducing the bias state difference of the driving transistor in the second stage and the first stage, thereby being favorable for reducing the climbing speed difference of the current received by the light emitting device in the first stage and the second stage, further being favorable for reducing the brightness difference of the display panel in the first stage and the second stage, and improving the flicker problem of the display panel.

Also, the brightness difference between each second stage and the first stage may be different in consideration of the difference in the duration of the light-emitting stage in the different second stages. Therefore, when the same frame of picture is displayed, in the second stages with different time periods of the lighting stage, the adjustment voltages transmitted by the first signal lines are different, so that the bias states of the driving transistors in the different second stages can be differently corrected, the climbing speed of the current received by the lighting devices in each second stage corresponds to the lighting time, the lighting brightness of the lighting devices in each second stage is basically the same as that of the lighting devices in the first stage, and the flicker problem of the display panel is further improved.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;

FIG. 2 is a schematic diagram of the pixel circuit of FIG. 1;

FIG. 3 is a schematic diagram of the pixel circuit shown in FIG. 2;

FIG. 4 is a timing diagram of the pixel circuit shown in FIG. 3;

fig. 5 is a schematic diagram of a correspondence relationship between an adjustment voltage and a light-emitting period in a second stage according to an embodiment of the present application;

FIG. 6 is a timing diagram of the pixel circuit shown in FIG. 3;

FIG. 7 is a schematic diagram of the pixel circuit shown in FIG. 2;

FIG. 8 is a timing diagram of the pixel circuit shown in FIG. 7;

fig. 9 is a schematic diagram of a display device according to an embodiment of the present application.

[ detailed description ] of the invention

For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and examples herein refer to values that are generally agreed upon, rather than exact, within reasonable process operating ranges or tolerances.

It should be understood that although the terms first, second, etc. may be used in embodiments of the present application to describe directions, transistors, scan lines, etc., these directions, transistors, scan lines, etc. should not be limited to these terms. These terms are only used to distinguish one direction, transistor, scan line, etc. from another. For example, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction, without departing from the scope of embodiments of the present application.

In the field of display technology, a pixel circuit is generally provided to drive a light emitting device to emit light so that a display panel can display a picture. In order to avoid the influence of the leakage current of the pixel circuit on the brightness of the display panel, the pixel circuit is generally configured to sequentially execute a first stage and a second stage in the process of displaying a frame of picture on the display panel, and dynamically adjust the light-emitting duration of the driving light-emitting device in different second stages so as to improve the brightness fluctuation of the display panel in the frame of picture. The first phase is a phase including a data writing phase and a light emitting phase, and the second phase is a phase which is performed after the first phase and does not include the data writing phase but includes the light emitting phase.

However, in the prior art, the light-emitting brightness of the display panel in the first stage and the light-emitting brightness in the second stage still have a large difference, so that the flicker problem occurs in the display screen. Especially in the low gray scale low frequency display state of the display panel, flicker is very noticeable.

The applicant has provided a solution to the problems existing in the prior art by intensive studies.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application, fig. 2 is a schematic diagram of the pixel circuit in fig. 1, fig. 3 is a schematic diagram of the pixel circuit in fig. 2, and fig. 4 is a timing diagram of the pixel circuit in fig. 3.

The embodiment of the present application provides a display panel 01, as shown in fig. 1 to 4, the display panel 01 includes a pixel circuit 10 and a light emitting device 20 electrically connected, and the pixel circuit 10 is used for driving the light emitting device 20 to emit light. In the display panel 01, the plurality of pixel circuits 10 may be arranged along a first direction X, which may be a row direction in the display panel 01, and a second direction Y, which may be a column direction in the display panel 01. That is, in the display panel 01, the pixel circuits 10 may be arrayed in the row direction and the column direction.

The pixel circuit 10 includes a driving transistor Md for generating a light emission driving current and a data writing module 101. The input end of the data writing module 101 is electrically connected to the first signal line DL1, the output end is electrically connected to the driving transistor Md, and the data writing module 101 can transmit the signal on the first signal line DL1 to the driving transistor Md. Alternatively, the data writing module 101 may transmit the signal on the first signal line DL1 to the source of the driving transistor Md.

The same first signal line DL1 may be electrically connected to the data writing modules 101 in the plurality of pixel circuits 10, and sequentially transmit signals to the different data writing modules 101.

The display panel 01 comprises a first stage T1 and n second stages T2 which are performed after the first stage T1 in the working process of displaying one frame of picture, wherein n is more than or equal to 2. The first phase T1 includes a data writing phase E1 and a light emitting phase E2 performed after the data writing phase E1, and the second phase T2 includes a conditioning phase E3 and a light emitting phase E2 performed after the conditioning phase E3.

It is understood that the pixel circuits 10 in the display panel 01 each include a data writing stage E1 and a light emitting stage E2, a regulating stage E3 and a light emitting stage E2. Since the plurality of pixel circuits 10 in the display panel 01 typically sequentially enter the data writing stage E1 along the extending direction of the first signal line DL1, the display panel 01 includes a plurality of data writing stages E1 in the first stage T1 when displaying one frame of picture, and the plurality of data writing stages E1 correspond to the data writing stages E1 sequentially performed by the plurality of pixel circuits 10. In addition, the pixel circuit 10 in the display panel 01 may sequentially enter the adjustment stage E3 along the extending direction of the first signal line DL1, and the display panel 01 includes a plurality of adjustment stages E3 in one second stage T2 when displaying one frame of image, and the plurality of adjustment stages E3 correspond to the adjustment stages E3 sequentially performed by the plurality of pixel circuits 10.

In addition, the first stage T1 and the n second stages T2 sequentially performed when the display panel 01 displays one frame of image may be identical to the first stage T1 and the n second stages T2 sequentially performed when the pixel circuit 10 displays one frame of image.

The data writing module 101 is turned on in the data writing stage E1 and the adjusting stage E3, the first signal line DL1 transmits the data voltage Vdata in the data writing stage E1, and transmits the adjusting voltage Vp in the adjusting stage E3. That is, in the data writing stage E1, the first signal line DL1 transmits the data voltage Vdata, and the data voltage Vdata can be transmitted to the driving transistor Md through the turned-on data writing module 101; in the adjusting stage E3, the first signal line DL1 transmits the adjusting voltage Vp, which can be transmitted to the driving transistor Md through the turned-on data writing module 101.

Alternatively, as shown in fig. 3, the data writing module 101 includes a first transistor M1, a first electrode of the first transistor M1 is electrically connected to the first signal line DL1, a second electrode of the first transistor M is electrically connected to the first electrode of the driving transistor Md, and a gate electrode of the first transistor M1 is electrically connected to the first scan line S1. The first pole of the driving transistor Md may be its source.

Referring to fig. 4, in the data writing stage E1 of the first stage T1, the first scan line S1 transmits an active signal (e.g., a low level signal) to control the first transistor M1 to be turned on, and the data voltage Vdata transmitted by the first signal line DL1 at this time can be transmitted to the first pole of the driving transistor Md through the turned-on first transistor M1.

In the adjusting stage E3 of the second stage T2, the first scan line S1 transmits an active signal (e.g., a low level signal) to control the first transistor M1 to be turned on, and the adjusting voltage Vp transmitted by the first signal line DL1 at this time can be transmitted to the first pole of the driving transistor Md through the turned-on first transistor M1.

In the second phase T2, in which the light emitting phases E2 have different durations, the adjustment voltage Vp transmitted by the first signal line DL1 is different.

That is, in the plurality of second phases T2 in which the display panel 01 displays one frame, if the duration of the light-emitting phase E2 of the pixel circuit 10 in the two second phases T2 is different, the adjustment voltage Vp received by the pixel circuit 10 in the two second phases T2 is different.

In the prior art, in the first stage T1 of displaying one frame of image on the display panel 01, in order to generate a light-emitting driving current that meets the requirements of the driving transistor Md, the gate of the driving transistor Md needs to be reset, and then the data voltage Vdata needs to be written into the gate of the driving transistor Md. To ensure that the driving transistor Md can generate a desired light emission driving current and transmit it to the light emitting device 20 in the light emitting stage E2 of the first stage T1. There is a current ramp up process at the initial stage of the light emission of the light emitting device 20, and the current ramp up speed is related to the bias state of the driving transistor Md.

However, in the display panel 01 of the prior art, in the second stage T2 in which the same frame is displayed, the gate of the driving transistor Md is not reset and the data voltage Vdata is written, and the gate of the driving transistor Md maintains the potential substantially equivalent to the previous light-emitting stage and transmits the light-emitting driving current to the light-emitting device 20 after the light-emitting driving current is generated. This results in a larger difference in bias state of the driving transistor Md between the initial stage of the light emitting stage E2 of the second stage T2 and the initial stage of the light emitting stage E2 of the first stage T1, so that the current received by the light emitting device 20 in the first stage T1 and the second stage T2 has a larger difference in ramp speed, and the display panel has a larger difference in brightness between the first stage T1 and the second stage T2, which results in a flicker problem, especially in a low frequency and low gray scale display state of the display panel 01, which is very obvious.

In the embodiment of the present application, in the adjusting stage E3 of the second stage T2, the adjusting voltage Vp transmitted by the first signal line DL1 may be transmitted to the driving transistor Md through the turned-on data writing module 101 to correct the bias state of the driving transistor Md, which is favorable to reducing the bias state difference of the driving transistor Md in the second stage T2 and the first stage T1, so as to reduce the ramp speed difference of the current received by the light emitting device 20 in the first stage T1 and the second stage T2, and further to reduce the brightness difference of the display panel 01 in the first stage T1 and the second stage T2, and improve the flicker problem of the display panel 01.

Moreover, the brightness difference between each second stage T2 and the first stage T1 may be different in consideration of the difference in the duration of the light-emitting stage E2 in the different second stages T2. Therefore, when the same frame of picture is displayed, in the second stage T2 with different durations of the light-emitting stage E2, the adjustment voltage Vp transmitted by the first signal line DL1 is different, and the bias states of the driving transistors Md in the different second stages T2 can be differently corrected, so that the ramp rate of the current received by the light-emitting device 20 in each second stage T2 corresponds to the light-emitting time, and further the light-emitting brightness of the light-emitting device 20 in each second stage T2 is substantially the same as the light-emitting brightness of the light-emitting device 20 in the first stage T1, so as to further improve the flicker problem of the display panel 01.

In one embodiment of the present application, please continue to refer to fig. 4, in the second phase T2, the longer the light-emitting phase E2, the larger the regulated voltage Vp transmitted by the first signal line DL 1. That is, in each second stage T2 in which the display panel 01 displays one frame, the longer the light emission time in which the pixel circuit 10 drives the light emitting device 20, the larger the adjustment voltage Vp received by the driving transistor Md in the pixel circuit 10.

For example, as shown in fig. 4, the display panel 01 displays n second phases T2 included in a frame of picture, including a first second phase T2 (1) and a second phase T2 (2), the regulated voltage Vp transmitted by the first signal line DL1 in the first second phase T2 (1) is the first regulated voltage Vp (1), the regulated voltage Vp transmitted by the second phase T2 (2) is the second regulated voltage Vp (2), the duration of the light-emitting phase E2 in the first second phase T2 (1) is less than the duration of the light-emitting phase E2 in the second phase T2 (2), and the first regulated voltage Vp (1) transmitted by the first signal line DL1 in the first second phase T2 (1) is less than the second regulated voltage Vp (2) transmitted in the second phase T2 (2).

It can be understood that, during the process of displaying a frame of picture on the display panel 01, since the gate of the driving transistor Md is still required to be reset in the first stage T1, the bias state of the driving transistor Md in the first stage T1 is usually biased negatively with respect to the bias state of the driving transistor Md in the second stage T2, and the greater the bias state of the driving transistor Md, the smaller the speed of generating the light-emitting driving current, which results in that the light-emitting brightness of the display panel 02 in the first stage T1 is usually smaller than the light-emitting brightness in the second stage T2. And the longer the light-emitting period E2 in the second period T2 is, the larger the display brightness of the display panel 01 in the second period T2 is, the larger the brightness difference between the second period T2 and the first period T1 is

The adjustment voltage Vp provided in the embodiment of the present application may be transmitted to the source of the driving transistor Md, and the adjustment voltage Vp is generally greater than the source potential of the driving transistor Md at the start time of the second stage T2, so that the bias state of the driving transistor Md in the second stage T2 may be biased negatively, thereby reducing the difference between the bias state of the driving transistor Md in the first stage T1 and the bias state of the driving transistor Md in the second stage T2. Meanwhile, in the second stage T2 with longer luminous stage E2, the larger the adjusting voltage Vp transmitted by the first signal line DL1 is, the larger the negative bias degree of the bias state of the driving transistor Md in the second stage T2 with larger luminous brightness is, and the speed of the driving transistor Md generating luminous driving current in the second stage T2 is smaller, so that the brightness of each second stage T2 is basically the same as the brightness of the first stage T1, and the flicker problem of the display panel 01 is improved.

Fig. 5 is a schematic diagram of a correspondence relationship between an adjustment voltage and a light-emitting period duration in a second stage according to an embodiment of the present application.

In one embodiment of the present application, as shown in fig. 5, in the plurality of second phases T2, the adjustment voltage Vp is linearly related to the duration of the light-emitting phase E2. I.e. the ratio of the difference between the regulated voltages Vp in any two second phases T2 to the difference between the durations of the light-emitting phases E2 in the two second phases T2 is the same.

For example, in n second phases T2 included in one frame of the display panel 01, the duration of the light-emitting phase E2 in the first second phase T2 (1) is a (1), and the regulated voltage Vp transmitted by the first signal line DL1 in the first second phase T2 (1) is Vp (1); the duration of the light-emitting phase E2 in the nth second phase T2 (n) is a (n), and the regulated voltage Vp transmitted by the first signal line DL1 in the nth second phase T2 (n) is Vp (n); the duration of the light-emitting phase E2 in the ith second phase T2 (i) is a (i), and the regulated voltage Vp transmitted by the first signal line DL1 in the ith second phase T2 (i) is Vp (i), 1 < i < n. The relation between the regulated voltage Vp (i) and the duration a (i) of the lighting phase E2 satisfies:

according to the embodiment of the application, the magnitude of the adjusting voltage Vp in the second stage T2 can be easily determined according to the duration of the light-emitting stage E2 in the second stage T2, so that the power of a driving chip in the display panel 01 can be saved.

With continued reference to fig. 2, in one embodiment of the present application, the output terminal of the data writing module 101 is electrically connected to the first pole of the driving transistor Md, and the pixel circuit 10 includes a threshold grabbing module 102, where the input terminal of the threshold grabbing module 102 is electrically connected to the second pole of the driving transistor Md, and the output terminal is electrically connected to the gate of the driving transistor Md. The first pole of the driving transistor Md may be a source thereof and the second pole may be a drain thereof. Of course, in some other embodiments, the first pole of the driving transistor Md may be the drain thereof and the second pole may be the source thereof.

The threshold grabbing module 102 is turned on in the data writing phase E1 of the first phase T1 and turned off in the adjustment phase E3 of the second phase T2.

In this embodiment of the present application, the threshold grabbing module 102 is turned on in the data writing stage E1 of the first stage T1, and since the data writing module 101 is also turned on at this time, the data voltage Vdata transmitted by the first signal line DL1 may be transmitted to the first pole of the driving transistor Md, so that the first pole potential of the driving transistor Md is greater than the gate potential thereof, thereby turning on the driving transistor Md, and the data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned on driving transistor Md and the threshold grabbing module 102, so as to complete the data writing to the gate of the driving transistor Md.

The threshold grabbing module 102 is turned off in the adjusting stage E3 of the second stage T2, so as to avoid the transmission of the adjusting voltage Vp to the gate of the driving transistor Md, and to avoid the generation of undesirable light-emitting driving current due to the change of the gate potential of the driving transistor Md.

Alternatively, as shown in fig. 3, the threshold grabbing module 102 includes a second transistor M2, where a first pole of the second transistor M2 is electrically connected to a second pole of the driving transistor Md, the second pole is electrically connected to a gate of the driving transistor Md, and the gate is electrically connected to the second scan line S2.

Referring to fig. 4, in the data writing stage E1 of the first stage T1, the second scan line S2 transmits an active signal (e.g., a low level signal) to control the second transistor M2 to turn on, and the data voltage Vdata may be transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the second transistor M2.

In the adjusting phase E3 of the second phase T2, the second scan line S2 transmits an active signal (e.g., a high level signal) to control the second transistor M2 to be turned off, so as to avoid the influence of the adjusting voltage Vp on the gate potential of the driving transistor Md.

In one embodiment of the present application, please further combine fig. 2-4, the pixel circuit 10 includes a first reset module 103, an input terminal of the first reset module 103 is electrically connected to the first reset signal line SL1, and an output terminal of the first reset module is electrically connected to the gate of the driving transistor Md. The first reset signal line SL1 may be used to transmit the reset voltage Vref.

The first phase T1 further includes a reset phase E0 performed before the data writing phase E1, the first reset module 103 is turned on during the reset phase E0, and the first reset module 103 is configured to reset the gate of the driving transistor Md.

Alternatively, as shown in fig. 3 and 4, the first reset module 103 includes a third transistor M3, a first electrode of the third transistor M3 is electrically connected to the first reset signal line SL1, a second electrode is electrically connected to a gate of the driving transistor Md, and a gate is electrically connected to the third scan line S3.

In the reset stage E0, the third scan line S3 transmits an active signal (e.g., a low level signal) to control the third transistor M3 to be turned on, and the reset voltage Vref transmitted on the first reset signal line SL1 may be transmitted to the gate of the driving transistor Md through the turned-on third transistor M3, so as to complete the reset of the gate of the driving transistor Md.

With continued reference to fig. 2, the pixel circuit 10 further includes a power supply voltage writing module 104 and a light emitting control module 105, where an input terminal of the power supply voltage writing module 104 is electrically connected to the power supply voltage signal line DY1, and an output terminal of the power supply voltage writing module is electrically connected to the first pole of the driving transistor Md. The input terminal of the light emitting control module 105 is electrically connected to the second pole of the driving transistor Md, and the output terminal is electrically connected to the light emitting device 20.

The power supply voltage writing module 104 and the light emission control module 105 are turned on in the light emission period E2.

That is, in the light emitting stage E2 of the first stage T1 and the light emitting stage E2 of the second stage T2, the power supply voltage writing module 104 and the light emitting control module 105 are turned on. The duration of the light emitting phase E2 is determined by the duration of the power supply voltage writing module 104 and the light emitting control module 105 on.

Further, the control end of the power supply voltage writing module 104 and the control end of the light emitting control module 105 are electrically connected to the light emitting control signal line EM, and the signal transmitted by the light emitting control signal line EM controls the light emitting control module 105 to have the same switching state as the power supply voltage writing module 104. The duration of the light emission control signal line EM transmitting the valid signal to control the power supply voltage writing module 104 and the light emission control module 105 to be turned on is the duration of the light emission phase E2.

Alternatively, as shown in conjunction with fig. 3 and 4, the power supply voltage writing module 104 includes a fourth transistor M4, a first pole of the fourth transistor M4 is electrically connected to the power supply voltage signal line DY1, a second pole is electrically connected to the first pole of the driving transistor Md, and a gate is electrically connected to the light emission control signal line EM. The light emission control module 105 includes a fifth transistor M5, a first electrode of the fifth transistor M5 is electrically connected to a second electrode of the driving transistor Md, a second electrode is electrically connected to a first electrode of the light emitting device 20, a gate is electrically connected to the light emission control signal line EM, and a channel type of the fifth transistor M5 is the same as a channel type of the fourth transistor M4. The light emitting device 20 may be an organic light emitting diode and the first pole of the light emitting device 20 may be an anode thereof.

In the light emitting stage E2 of the first stage T1 and the light emitting stage E2 of the second stage T2, the light emitting control signal line EM transmits an effective signal (e.g., a low level signal) to control the fourth transistor M4 and the fifth transistor M5 to be turned on, the power supply voltage VDD transmitted by the power supply voltage signal line DY1 is transmitted to the first electrode of the driving transistor Md through the turned-on fourth transistor M4, and since the potential of the power supply voltage VDD is greater than the potential of the data voltage Vdata, the driving transistor Md generates a light emitting driving current and is transmitted to the light emitting device 20 through the fifth transistor M5, thereby driving the light emitting device 20 to emit light.

With continued reference to fig. 2-4, the pixel circuit 10 further includes a second reset module 106, wherein an input end of the second reset module 106 is electrically connected to the first reset signal line SL1, an output end of the second reset module 106 is electrically connected to the first electrode of the light emitting device 20, a control end of the second reset module is electrically connected to the first scan line S1, and signals transmitted by the first scan line S1 control the switching states of the data writing module 101 and the second reset module 106 to be the same. The second reset module 106 is used to reset the first pole of the light emitting device 20.

Alternatively, the second reset module 106 includes a sixth transistor M6, a first electrode of the sixth transistor M6 is electrically connected to the first reset signal line SL1, a second electrode is electrically connected to the first electrode of the light emitting device 20, a gate is electrically connected to the first scan line S1, and a channel type of the sixth transistor M6 is the same as a channel type of the first transistor M1.

In the data writing stage E1 and the adjusting stage E3, the sixth transistor M6 is turned on, and the reset voltage Vref on the first reset signal line SL1 is transmitted to the first electrode of the light emitting device 20 through the sixth transistor M6, so as to reset the first electrode of the light emitting device 20.

Fig. 6 is a timing diagram of the pixel circuit shown in fig. 3.

In one embodiment of the present application, as shown in fig. 6, the lighting phase E2 of the second phase T2 includes at least two sub lighting phases E21, and the power supply voltage writing module 104 and the lighting control module 105 are turned on in the sub lighting phase E21. The power supply voltage writing module 104 and the light emission control module 105 may be turned off between adjacent sub-light emission phases E21.

That is, the sub-light-emitting stage E21 may be a partial period of the light-emitting stage E2. When the pixel circuit 10 drives the light emitting device 20 to emit light a plurality of times in one second stage T2, each light emitting period of the light emitting device 20 may be a sub-light emitting stage E21 described herein, and the operation of the pixel circuit 10 in the sub-light emitting stage E21 is the same as that of the light emitting stage E2 described above.

Of course, in the second phase T2, the conditioning phase E3 is located before the first sub-lighting phase E21. It should be noted that fig. 6 only illustrates a case where the light-emitting stage E2 of one second stage T2 includes two sub-light-emitting stages E21, and the light-emitting stage E2 of one second stage T2 may further include three or more sub-light-emitting stages E21.

In this embodiment of the present application, the light emitting stage E2 in the second stage T2 is set to include a plurality of sub-light emitting stages E21, which is favorable to further reduce the influence of the leakage current of the pixel circuit 10 in the second stage T2 on the display brightness, thereby being favorable to further improving the accuracy of the brightness of the light emitting device 20 and improving the display effect.

Further, the lighting stage E2 of the second stage T2 includes at least two sub-lighting stages E21, and in the same second stage T2, the duration of the lighting stage E2 is the sum of the durations of the sub-lighting stages E21. That is, in one second stage T2, the duration of the light emission stage E2 is the total duration of the light emission of the light emitting device 20 driven by the pixel circuit 10.

Fig. 7 is a schematic diagram of the pixel circuit shown in fig. 2, and fig. 8 is a timing diagram of the pixel circuit shown in fig. 7.

The pixel circuit 10 shown in fig. 7 differs from the pixel circuit 10 shown in fig. 3 in that: the second transistor M2 and the third transistor M3 are N-type transistors including a metal oxide active layer.

Compared to the timing shown in fig. 4, the timing variation shown in fig. 8 is that: the on signal transmitted by the second scan line S2 and the third scan line S3 is a high level signal, and the off signal is a low level signal.

The embodiment of the present application provides a display device 02, as shown in fig. 9, where the display device 02 includes the display panel 01 provided in the above embodiment. The display device 02 may be, for example, an electronic device such as a mobile phone, a computer, a television, a vehicle-mounted display, etc., which is not limited in this application.

In the display device 02, in the adjustment stage E3 of the second stage T2, the adjustment voltage Vp transmitted by the first signal line DL1 can be transmitted to the driving transistor Md through the turned-on data writing module 101 to correct the bias state of the driving transistor Md, which is favorable for reducing the bias state difference of the driving transistor Md in the second stage T2 and the first stage T1, thereby being favorable for reducing the ramp speed difference of the current received by the light emitting device 20 in the first stage T1 and the second stage T2, and further being favorable for reducing the brightness difference of the display panel 01 in the first stage T1 and the second stage T2, and improving the flicker problem of the display panel 01.

The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A display panel comprising a pixel circuit and a light emitting device electrically connected, the pixel circuit comprising:

a driving transistor for generating a light emission driving current;

the input end of the data writing module is electrically connected with the first signal line, and the output end of the data writing module is electrically connected with the driving transistor;

the working process of displaying one frame of picture by the display panel comprises a first stage and n second stages which are carried out after the first stage, wherein n is more than or equal to 2; the first phase includes a data writing phase and a light emitting phase performed after the data writing phase, and the second phase includes a conditioning phase and a light emitting phase performed after the conditioning phase;

the data writing module is started in the data writing stage and the adjusting stage, the first signal line transmits data voltage in the data writing stage and transmits adjusting voltage in the adjusting stage;

in the second phase, the light emitting phases are different in duration, and the adjustment voltages transmitted by the first signal lines are different.

2. The display panel according to claim 1, wherein in the second stage in which the longer the light-emitting stage is, the larger the adjustment voltage transmitted by the first signal line is.

3. The display panel of claim 2, wherein the adjustment voltage is linear with respect to a duration of the light-emitting phase in a plurality of the second phases.

4. The display panel according to claim 1, wherein the light-emitting stage of one of the second stages includes at least two sub-light-emitting stages, and a duration of the light-emitting stage in the same second stage is a sum of durations of the sub-light-emitting stages.

5. The display panel of claim 1, wherein the output of the data writing module is electrically connected to a first pole of the driving transistor, the pixel circuit comprises a threshold grabbing module, the input of the threshold grabbing module is electrically connected to a second pole of the driving transistor, and the output is electrically connected to a gate of the driving transistor;

the threshold grabbing module is opened in a data writing stage of the first stage and closed in an adjusting stage of the second stage.

6. The display panel according to claim 5, wherein the pixel circuit includes a first reset module having an input terminal electrically connected to a first reset signal line and an output terminal electrically connected to a gate of the driving transistor;

the first phase further includes a reset phase performed before the data writing phase, and the first reset module is turned on in the reset phase.

7. The display panel of claim 5, wherein the pixel circuit further comprises:

the input end of the power supply voltage writing module is electrically connected with the power supply voltage signal line, and the output end of the power supply voltage writing module is electrically connected with the first pole of the driving transistor;

the input end of the light-emitting control module is electrically connected with the second electrode of the driving transistor, and the output end of the light-emitting control module is electrically connected with the light-emitting device;

the power supply voltage writing module and the light-emitting control module are started in the light-emitting stage.

8. The display panel according to claim 7, wherein the control terminal of the power supply voltage writing module and the control terminal of the light emitting control module are electrically connected to a light emitting control signal line, and a signal transmitted by the light emitting control signal line controls the light emitting control module to have the same switching state as the power supply voltage writing module.

9. The display panel of claim 7, wherein the light-emitting phase of one of the second phases includes at least two sub-light-emitting phases, the power supply voltage writing module and the light-emitting control module being turned on in the sub-light-emitting phases.

10. A display device comprising a display panel as claimed in any one of claims 1-9.