CN116028289A

CN116028289A - Inter-chip interconnection USB signal testing device, method and medium

Info

Publication number: CN116028289A
Application number: CN202310124296.7A
Authority: CN
Inventors: 吴忠良; 荣世立
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-02-16
Filing date: 2023-02-16
Publication date: 2023-04-28

Abstract

The invention relates to the field of USB signal testing, and particularly discloses a device, a method and a medium for testing interconnection USB signals among chips, wherein a first electronic switch is connected to a signal wire of a chip, meanwhile, the signal wire is connected with a grounding wire, and a second electronic switch is connected to the grounding wire; the test controller is connected with the first electronic switch and the second electronic switch respectively, and when in test, the test controller controls the opening and closing states of the first electronic switch and the second electronic switch, and meanwhile, the connection point is used as a test point to be connected with a probe of the test instrument for test. The invention sets an electronic switch on the signal line on the chip, connects the signal line to one ground line, sets an electronic switch on the ground line, and controls the sending and receiving of the chip signal by the opening and closing of the electronic switch. According to the invention, the test circuit is arranged in the chip, so that the transmission and the reception of signals of the chip are controlled, the quality test of the interconnection USB signals among the chips is realized, the operation is simple, and the test result is reliable.

Description

Inter-chip interconnection USB signal testing device, method and medium

Technical Field

The invention relates to the field of USB signal testing, in particular to an inter-chip interconnection USB signal testing device, method and medium.

Background

USB has become a versatile and widely used signal and interface in current server and PC platforms. In addition to the common USB interface used as an external plug-in device, a high-speed bus is also frequently used between the internal chips of the motherboard. The quality of USB signals relates to whether the external devices such as a mouse, a keyboard, a USB flash disk and the like can normally identify, the transmission speed is high or low, and even the server can stably work for USB signals which are connected with important chips, such as USB2.0 signals which are connected with a CPU and a BMC on the server platform.

Fig. 1 is a schematic diagram of a conventional USB signal test topology, in which a standard USB2.0 interface can be tested, a chip is connected to a test fixture through a USB interface, the test fixture is connected to a test instrument (e.g., an oscilloscope), and a signal consistency test is performed using a commonly known test method.

However, for the test method of the USB2.0 signal without standard for chip interconnection, fig. 2 is a schematic diagram of chip interconnection, two chips on the motherboard are directly interconnected through the PCB trace of the USB2.0, the trace of the USB2.0 is on the inner layer of the PCB, and there is no test point between the chips, so that the test of signal quality (introduced into the oscilloscope for testing) cannot be performed under the condition that the test condition of consistency of the USB2.0 signal is not satisfied, therefore, the signal quality cannot be judged by the traditional standard of consistency, and the standard test of signal quality cannot be performed.

Disclosure of Invention

In order to solve the problems, the invention provides a device, a method and a medium for testing interconnection USB signals between chips, wherein a test circuit is arranged in the chips to control the sending and receiving of the signals of the chips, so that the quality test of the chips is realized, the operation is simple, and the test result is reliable.

In a first aspect, the present invention provides an inter-chip interconnection USB signal testing apparatus, where the chips are connected by a USB signal trace on a PCB, a connection point connected to the USB signal trace is on the chip, and the connection point on the chip is connected to a signal line, the apparatus includes a test controller, a first electronic switch and a second electronic switch; the first electronic switch is connected to the signal wire, the signal wire is connected to the grounding wire, and the second electronic switch is connected to the grounding wire;

the test controller is connected with the first electronic switch and the second electronic switch respectively, and when in test, the test controller controls the opening and closing states of the first electronic switch and the second electronic switch, and meanwhile, the connection point is used as a test point to be connected with a probe of the test instrument for test.

Further, a pull-down resistor is also arranged on the grounding wire.

Further, the USB signals transmitted between the chips are differential signals, the signal lines comprise DP signal lines and DN signal lines, and the connection points comprise DP signal connection points and DN signal connection points;

the DP signal line and the DN signal line are respectively connected with a first electronic switch; the DP signal line and the DN signal line are respectively connected with a grounding wire, and each grounding wire is connected with a second electronic switch and a pull-down resistor;

the DP signal connection point and the DN signal connection point are both connected to the probe of the test instrument.

Further, during testing, the first electronic switch on the chip serving as the transmitting end is closed, the second electronic switch on the chip serving as the receiving end is opened, and the first electronic switch on the chip serving as the receiving end is closed.

Further, the first electronic switch is a MOS tube, a triode or a relay, and the second electronic switch is a MOS tube, a triode or a relay.

Further, the device also comprises a first switch control circuit and a second switch control circuit, wherein the test controller is connected with the first electronic switch through the first switch control circuit, and the test controller is connected with the second electronic switch through the second switch control circuit.

In a second aspect, the present invention provides a method for testing an inter-chip interconnection USB signal, including the steps of:

receiving a test instruction, wherein the test instruction comprises a test transmitting end chip and a test receiving end chip;

and controlling the on state of the signal line on the corresponding chip according to the test instruction.

Further, the method for controlling the on state of the signal line on the corresponding chip according to the test instruction specifically comprises the following steps:

the signal line of the control transmitting end chip is normally connected, and the signal line of the receiving end chip is grounded.

Further, the method specifically comprises the following steps:

a first electronic switch on a signal wire of the control transmitting end chip is connected, and a second electronic switch on a grounding wire is disconnected;

the first electronic switch on the signal wire of the control receiving end chip is turned off, and the second electronic switch on the grounding wire is turned on.

In a third aspect, the present invention provides a computer readable storage medium, where an inter-chip interconnection USB signal test program is stored, where the inter-chip interconnection USB signal test program, when executed by a processor, implements the steps of the inter-chip interconnection USB signal test method according to any one of the above described embodiments.

The method, the device and the medium for testing the interconnection USB signals between chips have the following beneficial effects compared with the prior art: an electronic switch is arranged on a signal wire on the chip, the signal wire is connected with a ground wire, the electronic switch is arranged on the ground wire, and the sending and receiving of signals of the chip are controlled through the opening and closing of the electronic switch. According to the invention, the test circuit is arranged in the chip, so that the transmission and the reception of signals of the chip are controlled, the quality test of the interconnection USB signals among the chips is realized, the operation is simple, and the test result is reliable.

Drawings

For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.

Fig. 1 is a schematic diagram of a conventional test topology of USB signals.

Fig. 2 is a schematic diagram of chip interconnection.

Fig. 3 is a schematic structural diagram of an inter-chip USB signal testing apparatus according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an inter-chip USB signal testing apparatus according to a second embodiment of the present invention.

Fig. 5 is a schematic structural diagram of an embodiment of an inter-chip USB signal testing device according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating transmission of interconnection signals between the first chip and the second chip when the embodiment shown in FIG. 5 is used for testing the USB2.0 signal of the first chip.

Fig. 7 is an eye diagram of the second chip side test when the electronic switch ST22 is closed while the embodiment shown in fig. 5 tests the first chip USB2.0 signal.

Fig. 8 is an eye diagram of the second chip side test when the electronic switch ST22 is turned off while the embodiment shown in fig. 5 tests the first chip USB2.0 signal.

Fig. 9 is a flow chart of a method for testing an inter-chip interconnection USB signal according to a third embodiment of the present invention.

Detailed Description

In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Fig. 2 is a schematic diagram of chip interconnection, two chips on a motherboard are directly interconnected through a PCB wiring of USB2.0, a conventional USB interface is not provided on the chips, and quality test of USB signals cannot be performed through a conventional test method in which the conventional USB interface is connected with an oscilloscope through a test fixture.

Example 1

Fig. 3 is a schematic structural diagram of an inter-chip USB signal testing device according to an embodiment of the present invention, and as shown in fig. 3, the device includes a first electronic switch ST1 and a second electronic switch ST2, and a testing controller is also provided to realize testing control.

The first electronic switch ST1 is disposed on the signal line 2, the signal line 2 is connected to the ground line 3, and the second electronic switch ST2 is connected to the ground line 3. When the first electronic switch ST1 is closed and the second electronic switch ST2 is opened, the chip 1 normally communicates; when the first electronic switch ST1 is opened and the first electronic switch ST1 is closed, the signal is grounded, and the chip 1 does not enter the actions such as handshaking of normal communication.

The test controller is respectively connected with the first electronic switch ST1 and the second electronic switch ST2, and during testing, the test controller controls the opening and closing states of the first electronic switch ST1 and the second electronic switch ST2, and meanwhile, the connection point 4 is used as a test point to be connected with a probe of a test instrument for testing.

For a certain chip 1, if the chip 1 is a transmitting end in the test, the USB signal of the chip 1 is tested, the first electronic switch ST1 of the chip 1 is closed, the second electronic switch ST2 is opened, the first electronic switch ST1 of the opposite-end chip is opened, the second electronic switch ST2 is closed, the opposite-end chip is a receiving end, and the signal is grounded. And meanwhile, the connection point 4 of the receiving end chip is used as a probe of a test instrument connected to the test end, and the test instrument detects the USB signal.

According to the inter-chip interconnection USB signal testing device provided by the embodiment of the invention, the electronic switch is arranged on the signal wire 2 on the chip 1, meanwhile, the signal wire 2 is connected with one ground wire, the electronic switch is arranged on the ground wire, and the sending and receiving of signals of the chip 1 are controlled through the opening and closing of the electronic switch. The invention sets the testing circuit in the chip 1, controls the sending and receiving of the chip 1 signal, realizes the quality test of the interconnection USB signal between chips, and has simple operation and reliable testing result.

Example two

Fig. 4 is a schematic structural diagram of an inter-chip USB signal testing device according to a second embodiment of the present invention, as shown in fig. 4, the device includes a first electronic switch ST1, a second electronic switch ST2, and a pull-down resistor R. Of course, a test controller is also provided for implementing the test control.

The first electronic switch ST1 is disposed on the signal line 2, while the signal line 2 is connected to the ground line 3, and the second electronic switch ST2 and the pull-down resistor R are connected in series to the ground line 3, so that the signal is grounded through the pull-down resistor R. When the first electronic switch ST1 is closed and the second electronic switch ST2 is opened, the chip 1 communicates normally; when the first electronic switch ST1 is opened and the first electronic switch ST1 is closed, the signal is grounded through the pull-down resistor R, and the chip 1 does not enter the handshake of normal communication.

The USB signals transmitted between the chips are differential signals, and correspondingly, the signal line 2 includes a DP signal line and a DN signal line, and the connection point 4 also includes two connection points, namely a DP signal connection point and a DN signal connection point.

When the electronic switch and the pull-down resistor R are arranged, a first electronic switch ST1 is respectively connected to the DP signal line and the DN signal line, meanwhile, the DP signal line and the DN signal line are respectively connected with a grounding wire 3, and each grounding wire 3 is connected with a second electronic switch ST2 and the pull-down resistor R.

When the electronic switches are turned on and off, it is necessary to simultaneously turn on and off the two electronic switches on the two signal lines 2. For example, a certain chip 1 is used as a transmitting end, the first electronic switch ST1 on the DP signal line and the DN signal line of the chip 1 is closed, and the second electronic switch ST2 on the two ground lines 3 is opened.

Meanwhile, the DP signal connection point and the DN signal connection point are both connected to the probe of the test instrument.

During testing, if the chip 1 is a transmitting end and the USB signal of the chip 1 is tested, the two first electronic switches ST1 of the chip 1 are closed, the two second electronic switches ST2 are opened, the two first electronic switches ST1 of the opposite-end chip are opened, the two second electronic switches ST2 are closed, the opposite-end chip is a receiving end, and the signal is grounded.

In some embodiments, the first electronic switch ST1 may be a MOS transistor, a triode, or a relay, and the second electronic switch ST2 may be a MOS transistor, a triode, or a relay.

For controlling the electronic switch, in some embodiments, a first switch control circuit and a second switch control circuit are further provided, the test controller is connected to the first electronic switch ST1 through the first switch control circuit, and the test controller is connected to the second electronic switch ST2 through the second switch control circuit. It should be noted that, each first electronic switch ST1 corresponds to one first switch control circuit, and one first switch control circuit may also control two first electronic switches ST1 simultaneously. The second electronic switch ST2 is the same.

For further understanding of the present invention, a detailed description of the present invention is provided below, and fig. 5 is a schematic diagram of the structure of the detailed embodiment.

As shown in fig. 5, in the motherboard to be tested, the first chip 101 and the second chip 102 are interconnected through USB2.0 PCB traces, the traces are differential traces, DP is +, and DN is-. DP1 and DN1 are test points of the first chip 101, and are tested by connecting a differential probe to a test instrument (such as an oscilloscope), DP2 and DN2 are test points of the second chip 102, and are tested by connecting another differential probe to the oscilloscope.

Inside the first chip 101 and the second chip 102, a test circuit is provided, consisting of an electronic switch which can be freely controlled to be turned on and off and a 50 ohm resistor which is grounded to the DP/DN, respectively.

When the USB2.0 signal of the first chip 101 is to be tested, the first chip 101 enters a test mode as a transmitting end: the electronic switch ST11 is controlled to be closed, the electronic switch ST21 is opened, the first chip 101 does not enter the actions such as handshake of normal communication, and the like, and the signal inside the chip 1 directly sends out a continuous test waveform signal from the DP1/DN 1. Meanwhile, the second chip 102 is used as a receiving end to enter a test mode, the electronic switch ST12 is controlled to be opened, the electronic switch ST22 is controlled to be closed, the second chip 102 does not enter the handshake and other actions of normal communication, and meanwhile, signals are grounded through the 50 ohm resistor R2, so that the influence of other USB2 code patterns in normal communication in the test process on the test can be eliminated, and the test accuracy is improved.

With the above arrangement, in this case, as shown in fig. 6, the first chip 101 and the second chip 102 are interconnected, and the first chip 101 transmits, and the second chip 102 receives, and the signal direction is the arrow direction in the figure. At this time, the test condition of the USB2.0 signal is realized, and the signal is led into the test instrument through the differential probe by the test points DP2 and DN2 on the second chip 102 for signal test.

It should be noted that, during testing, the signal of the receiving end is grounded, so that the influence of other USB2 code patterns during normal communication during testing can be eliminated, the testing accuracy is improved, the comparison result is shown in fig. 7 and 8, fig. 7 is an eye diagram of the second chip 102 end test when the electronic switch ST22 is closed, fig. 8 is an eye diagram of the normal communication between the first chip 101 and the second chip 102 when the electronic switch ST22 is opened, and the eye diagram of the second chip 102 end test is more accurate, so that the eye diagram of the electronic switch ST22 is obviously closed.

When USB2.0 signals of the second chip 102 are to be tested, roles of the first chip 101 and the second chip 102 are exchanged (the first chip 101 is used as a receiving end, the second chip 102 is used as a transmitting end), the corresponding electronic switch is turned on and off, and the signal direction is opposite to that of fig. 6, and the test points DP1 and DN1 of the first chip 101 are used for signal testing.

The specific test flow comprises the following steps:

1) The main board is normally electrified, and the first chip 101 and the second chip 102 work normally;

2) When the USB2.0 signal of the first chip 101 is to be tested, the first chip 101 enters a transmitting end test mode, and the second chip 102 enters a receiving end test mode;

3) Controlling the on-off of each electronic switch according to the description, and controlling the flow direction of internal signals so as to realize the test condition of the signals;

4) Testing the USB2.0 signal at the DP2/DN2 of the second chip 102;

5) When the USB2.0 signal of the second chip 102 is to be tested, the second chip 102 enters a transmitting end test mode, and the first chip 101 enters a receiving end test mode;

6) And controlling the on-off of each electronic switch according to the description, and controlling the flow direction of the internal signal so as to realize the test condition of the signal.

7) The test of the USB2.0 signal is performed at DP1/DN1 of the first chip 101.

Example III

The embodiment of the inter-chip interconnection USB signal testing device is described in detail above, and based on the inter-chip interconnection USB signal testing device described in the above embodiment, the embodiment of the invention further provides an inter-chip interconnection USB signal testing method corresponding to the device.

Fig. 9 is a flow chart of a method for testing an inter-chip interconnection USB signal according to a third embodiment of the present invention, as shown in fig. 9, the method includes the following steps.

S1, receiving a test instruction, wherein the test instruction comprises a test transmitting end chip 1 identifier and a receiving end chip 1 identifier.

S2, controlling the on state of the signal line 2 on the corresponding chip 1 according to the test instruction.

The background sends a test instruction to a test controller according to the test requirement, wherein the test instruction comprises a transmitting end chip 1 identifier and a receiving end chip 1 identifier of the test, the test controller finds a corresponding chip 1 according to the chip 1 identifier, and then controls the on and off of an electronic switch according to the test state (transmitting end or receiving end) of the chip 1.

After the electronic switch is set, the probe of the testing instrument is connected to the testing point of the corresponding chip 1 for testing.

Wherein, according to the test instruction, the on state of the signal line 2 on the corresponding chip 1 is controlled, specifically including: the signal line 2 of the control transmitting end chip 1 is normally connected, and the signal line 2 of the receiving end chip 1 is grounded.

The signal transmission is realized by controlling the on-off of the electronic switch, which comprises the steps of controlling the on-off of a first electronic switch ST1 on a signal wire 2 of a transmitting end chip 1 to be turned on and controlling a second electronic switch ST2 on a grounding wire 3 to be turned off; the first electronic switch ST1 on the signal line 2 of the control receiving-end chip 1 is turned off, and the second electronic switch ST2 on the ground line 3 is turned on.

The inter-chip interconnection USB signal testing method of this embodiment is implemented based on the inter-chip interconnection USB signal testing device described above, and therefore, the specific implementation of this method may be found in the foregoing example portion of the inter-chip interconnection USB signal testing device, so, the specific implementation thereof may refer to the description of the corresponding examples of each portion, and will not be described herein.

In addition, since the inter-chip interconnection USB signal testing method of this embodiment is implemented based on the inter-chip interconnection USB signal testing device described above, the functions thereof correspond to those of the device described above, and will not be described herein again.

Example IV

The invention also provides a computer storage medium, which can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (randomaccess memory, RAM) and the like.

The computer storage medium stores an inter-chip interconnection USB signal test program, and the inter-chip interconnection USB signal test program realizes the following steps when being executed by a processor:

s1, receiving a test instruction, wherein the test instruction comprises a test transmitting end chip 1 identifier and a receiving end chip 1 identifier;

The invention sets an electronic switch on the signal line 2 on the chip 1, connects the signal line 2 to a ground line, sets an electronic switch on the ground line, and controls the sending and receiving of the chip 1 signal through the opening and closing of the electronic switch. The invention sets the testing circuit in the chip 1, controls the sending and receiving of the chip 1 signal, realizes the quality test of the interconnection USB signal between chips, and has simple operation and reliable testing result.

It will be apparent to those skilled in the art that the techniques of embodiments of the present invention may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solution in the embodiments of the present invention may be embodied essentially or what contributes to the prior art in the form of a software product stored in a storage medium such as a U-disc, a mobile hard disk, a Read-only Memory (ROM), a random access Memory (RAM, randomAccess Memory), a magnetic disk or an optical disk, etc. various media capable of storing program codes, including several instructions for causing a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the method described in the embodiments of the present invention.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The foregoing disclosure is merely illustrative of the preferred embodiments of the invention and the invention is not limited thereto, since modifications and variations may be made by those skilled in the art without departing from the principles of the invention.

Claims

1. The device is characterized by comprising a test controller, a first electronic switch and a second electronic switch; the first electronic switch is connected to the signal wire, the signal wire is connected to the grounding wire, and the second electronic switch is connected to the grounding wire;

2. The inter-chip interconnect USB signal testing device of claim 1, wherein a pull-down resistor is further disposed on the ground line.

3. The inter-chip interconnect USB signal testing apparatus of claim 2, wherein USB signals transmitted between chips are differential signals, the signal lines include a DP signal line and a DN signal line, and the connection points include a DP signal connection point and a DN signal connection point;

4. The inter-chip interconnect USB signal testing apparatus of claim 3, wherein the first electronic switch on the chip as the transmitting side is closed and the second electronic switch on the chip as the receiving side is opened and the second electronic switch on the chip as the receiving side is closed during testing.

5. The inter-chip interconnect USB signal testing device of claim 4, wherein the first electronic switch is a MOS transistor, a triode, or a relay, and the second electronic switch is a MOS transistor, a triode, or a relay.

6. The inter-chip interconnect USB signal testing device of claim 5, further comprising a first switch control circuit and a second switch control circuit, wherein the test controller is coupled to the first electronic switch via the first switch control circuit and the test controller is coupled to the second electronic switch via the second switch control circuit.

7. The method for testing the interconnection USB signals between chips is characterized by comprising the following steps of:

receiving a test instruction, wherein the test instruction comprises a test transmitting end chip identifier and a receiving end chip identifier;

8. The method for testing inter-chip interconnect USB signals according to claim 7, wherein controlling the on-state of the signal lines on the respective chips according to the test command comprises:

9. The method for testing the inter-chip interconnection USB signal according to claim 8, wherein the method specifically comprises:

10. A computer readable storage medium, wherein an inter-chip interconnect USB signal test program is stored on the readable storage medium, which when executed by a processor, implements the steps of the inter-chip interconnect USB signal test method according to any one of claims 7-9.