CN111274076A - Debugging system - Google Patents
Debugging system Download PDFInfo
- Publication number
- CN111274076A CN111274076A CN202010085717.6A CN202010085717A CN111274076A CN 111274076 A CN111274076 A CN 111274076A CN 202010085717 A CN202010085717 A CN 202010085717A CN 111274076 A CN111274076 A CN 111274076A
- Authority
- CN
- China
- Prior art keywords
- signal
- channel
- signal output
- debugging
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 46
- 238000004891 communication Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 6
- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides a debugging system. The debugging system provided by the invention comprises: the device comprises a device to be debugged, a signal conversion device and a main control device. According to the technical scheme, the signal conversion equipment is designed between the equipment to be debugged and the main control equipment, and the serial port debugging information of the equipment to be debugged is converted by the signal conversion equipment and then is output to the main control equipment, so that pins do not need to be designed on the equipment to be debugged, such as a notebook computer mainboard or a product with strict height limitation, the condition that the TX and RX signals can be connected only by disassembling the machine when the whole machine is debugged is avoided, and the debugging process of the notebook computer mainboard and the whole notebook computer is simplified.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a debugging system.
Background
The notebook computer mainboard can use the serial port to output related debugging information to assist in analyzing related problems during research, development and debugging. When the motherboard is designed, TX (Transmit) and RX (Receive) for outputting and receiving serial port information on the motherboard are usually connected to a pin header. When a mainboard is used for research, development and debugging (Debug), a serial port line of converting USB to TTL is needed, one end of the serial port line is correspondingly connected to a pin header connected with a TX/RX signal of equipment to be debugged, a USB plug at the other end of the serial port line is inserted into a USB interface of a main control computer, serial port debugging software is opened on the main control computer and is correspondingly set, and serial port debugging information of a notebook computer mainboard can be output to the serial port debugging software to assist research and development engineers in analyzing related problems. Because the height of row needle is generally about 8.5mm, can't design row needle on notebook computer mainboard or the product that has the height restriction to require stricter, and when needs carry out the analysis to the complete machine, even if the design has row needle on the mainboard, when debugging information is looked over through the serial ports to needs, still need the machine of tearing open and connect TX and RX signal, lead to the operation flow complicated.
Disclosure of Invention
The invention mainly aims to provide a debugging system, aiming at solving the technical problem of complex operation flow when debugging information is checked through a serial port at present.
In order to achieve the above object, the present invention provides a debugging system, including:
the device to be debugged comprises a signal output interface, and the signal output interface is used for outputting debugging information of the device to be debugged;
the signal conversion equipment comprises a first joint, a signal conversion chip and a second joint, the signal conversion chip is electrically connected with the first joint and the second joint, and the first joint is inserted into the signal output interface so as to realize the communication connection between the signal conversion chip and the equipment to be debugged;
the main control equipment comprises a signal input interface, and the second connector is inserted into the signal input interface so as to realize the communication connection between the signal conversion chip and the main control equipment.
Optionally, the device to be debugged further includes:
the channel switching chip is electrically connected with the signal output interface and comprises a USB2.0 signal channel and a debugging signal output channel, and the channel switching chip is used for controlling the conduction of the debugging signal output channel.
Optionally, the model of the channel switching chip is PI3USB221ze, and the signal output interface is a USB3.0 female connector.
Optionally, the device to be debugged further includes a level shift circuit, where the level shift circuit is connected to the channel switching chip and the signal output interface.
Optionally, the channel switching chip includes: the USB device comprises a channel control pin, a first input pin group, a second input pin group and an output pin group, wherein when the channel control pin is at a low level, the first input pin group is conducted with the output pin group to form the debugging signal output channel, and when the channel control pin is at a high level, the second input pin group is conducted with the output pin group to form the USB2.0 signal channel;
the signal output interface comprises a first level control pin;
the level conversion circuit is an MOS tube, the grid electrode of the MOS tube is connected to the first level control pin of the signal output interface, the source electrode of the MOS tube is connected to the channel control pin, and the drain electrode of the MOS tube is grounded.
Optionally, the first connector is a USB3.0 male connector, the USB3.0 male connector includes a second level control pin, the second level control pin is connected to a power supply, and after the USB3.0 male connector is plugged into the USB3.0 female connector, the first level control pin is in contact with the second level control pin for conduction.
Optionally, the signal type output by the debug signal output channel is a TX/RX signal, and the signal conversion chip converts the TX/RX signal into a DP/DM signal and transmits the DP/DM signal to the master device.
Optionally, the signal input interface is electrically connected to the signal output interface to form a channel for transmitting USB2.0 signals.
Optionally, the second connector is a Micro USB2.0 connector.
Optionally, the signal conversion chip has a model of CP2102, CH340 or FT 232.
According to the technical scheme, the signal conversion equipment is designed between the equipment to be debugged and the main control equipment, and the serial port debugging information of the equipment to be debugged is converted by the signal conversion equipment and then is output to the main control equipment, so that pins do not need to be designed on a notebook computer mainboard or a product with strict height limitation requirements, the condition that the TX and RX signals can be connected only by disassembling the machine when the whole machine is debugged is avoided, and the debugging process of the notebook computer mainboard and the whole machine of the notebook computer is simplified.
Drawings
FIG. 1 is a circuit diagram of a debugging system according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a circuit structure of a channel switching chip in the device to be debugged according to the present invention;
FIG. 3 is a schematic structural diagram of a level shift circuit in the device to be debugged according to the present invention;
FIG. 4 is a schematic circuit diagram of a signal output interface in the device to be debugged according to the present invention;
fig. 5 is a schematic circuit diagram of a first connector in the signal conversion device of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back) are involved in the embodiment of the present invention, the directional indications are only used for explaining the relative positional relationship, the motion situation, and the like between the components in a certain posture, and if the certain posture is changed, the directional indications are changed accordingly.
In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a hardware architecture diagram of a debugging system of the present invention, the debugging system comprising:
the device to be debugged 1, wherein the device to be debugged 1 comprises a signal output interface 1a, and the signal output interface 1a is used for outputting debugging information of the device to be debugged 1;
the signal conversion device 2 comprises a first connector 2a, a signal conversion chip 2b and a second connector 2c, the signal conversion chip 2b is electrically connected with the first connector 2a and the second connector 2c, and the first connector 2a is inserted into the signal output interface 1a to realize the communication connection between the signal conversion chip 2b and the device to be debugged 1;
the main control device 3, the main control device 3 includes a signal input interface 3a, and the second connector 2c is inserted into the signal input interface 3a to realize the communication connection between the signal conversion chip 2b and the main control device 3.
In this embodiment, the device to be debugged 1 may be a computer motherboard, a computer complete machine, or other devices that need to be debugged, and the signal output interface 1a is disposed on the device to be debugged 1, where the signal output interface 1a may be a USB interface, a DP interface, or other types of interfaces that can perform data transmission. The debug information may be TX/RX signals, and besides, the device to be debugged 1 may also transmit USB signals through the signal output interface 1 a.
In this embodiment, the signal conversion device 2 is an intermediate device that connects the device 1 to be debugged and the main control device 3, the signal conversion device 2 is provided with a first connector 2a that can be in communication connection with the device 1 to be debugged, the first connector 2a corresponds to the signal output interface 1a, and the first connector 2a can be plugged onto the signal output interface 1a, so that if the signal output interface 1a is a USB female connector, the corresponding first connector 2a is a USB male connector. The signal conversion device 2 is further provided with a second connector 2c capable of achieving communication connection with the main control device 3, and the second connector 2c may be a USB interface, a DP interface, or other types of interfaces capable of performing data transmission. A signal conversion chip 2b may be further disposed between the first connector 2a and the second connector 2c, where the signal conversion chip 2b is configured to convert the debugging information output by the device to be debugged into other information that can be received and identified by the main control device 3, for example, when the debugging information is a TX/RX signal, the signal conversion chip 2b is configured to convert the signal conversion chip 2b into a DP/DM signal, so that the DP/DM signal can be received and identified by the main control identification device 3.
In this embodiment, the main control device 3 may be a computer, and the main control device 3 may process the received debugging information or the common USB information. The main control device 3 is provided with a signal input interface 3a capable of realizing communication connection with the second connector 2c, and the signal input interface 3a corresponds to the second interface 2c, so that if the second connector 2c is a Micro USB male connector, the signal input interface 3a is a USB female connector, and the second connector 2c is inserted into the signal input interface 3a, so that communication connection between the signal conversion chip 2b and the main control device 3 can be realized.
In this embodiment, the debugging signal in the device 1 to be debugged may be transmitted to the signal conversion chip 2b through the signal output interface 1a and the first connector 2a, and after being converted by the signal conversion chip 2b, the debugging signal is transmitted to the main control device 2 through the second connector 2c and the signal input interface 3a for debugging.
In the embodiment, the signal conversion device is designed between the device to be debugged and the main control device, and the serial port debugging information of the device to be debugged is converted by the signal conversion device and then output to the main control device, so that pins do not need to be designed on a notebook computer mainboard or a product with strict height limitation requirements, connection of TX and RX signals can be realized only by disassembling the notebook computer mainboard when the whole notebook computer is debugged, and the debugging process of the notebook computer mainboard and the whole notebook computer is simplified.
Referring to fig. 2, the device to be debugged 1 further includes: the channel switching chip U2, the channel switching chip U2 with signal output interface 1a electric connection, and the channel switching chip U2 includes USB2.0 signal channel (formed when being connected by 2D and D) and debugging signal output channel (formed when being connected by 1D and D), the channel switching chip U2 is used for controlling the debugging signal output channel to switch on.
In this embodiment, the USB2.0 signal channel is formed when 2D and D are connected, the USB2.0 signal channel can be used to transmit a conventional USB signal when it is turned on, the debug signal output channel is formed when 1D and D are connected, the channel switching chip U2 is used to control the turn on of the debug signal output channel, and the debug signal output channel is used to transmit a TX/RX signal when it is turned on.
Further, referring to fig. 3 and 4, the device to be debugged 1 further includes a level shift circuit, and the level shift circuit connects the channel switching chip U2 and the signal output interface 1 a.
In this embodiment, the UARTA _ USB _ SEL port of the level shifter circuit is connected to the 9 th pin of the channel switch chip U2, and the UARTA _ P80_ EN port of the level shifter circuit is connected to the 7 th pin of the signal output interface 1a, so that the communication connection between the channel switch chip U2 and the signal output interface 1a is realized through the level shifter circuit.
In this embodiment, the level shift circuit may be configured to implement potential shift between the channel switching chip U2 and the signal output interface 1a, that is, if the signal output interface 1a is at a high level, the pin 9 of the channel switching chip U2 is connected to a low level through the level shift circuit, and at this time, the channel switching chip U2 controls the conduction of the debug signal output channel; if the signal output interface 1a is at low level, the pin 9 of the channel switching chip U2 is at high level after passing through the level shifter, and at this time, the channel switching chip U2 controls the USB2.0 signal channel.
Further, the channel switching chip U2 includes: a channel control pin (SEL), a first input pin set (1D + and 1D-), a second input pin set (2D + and 2D-) and an output pin set (D + and D-), wherein when the channel control pin (SEL) is at a low level, the first input pin set (1D + and 1D-) and the output pin set (D + and D-) are conducted to form the debug signal output channel, and when the channel control pin (SEL) is at a high level, the second input pin set (2D + and 2D-) and the output pin set (D + and D-) are conducted to form the USB2.0 signal channel;
in this embodiment, the channel control pin (SEL), that is, the 9 th pin of the channel control pin, when the channel control pin (SEL) is at a low level, the channel switching chip U2 controls the first input pin group (1D + and 1D-) to be conducted with the output pin group (D + and D-) to form a debug signal output channel (formed when 1D and D are connected), which can realize transmission of TX/RX signals; when the channel control pin (SEL) is at a high level, the channel switching chip U2 controls the second input pin group (2D + and 2D-) to be conducted with the output pin group (D + and D-) to form a USB2.0 signal channel (formed when 2D and D are connected), which can realize the transmission of USB signals.
The signal output interface comprises a first level control pin;
in this embodiment, the first level control pin is the 7 th pin of the signal output interface 1a, and the first level control pin is connected to the UARTA _ P80_ EN port of the level shift circuit.
The level conversion circuit is an MOS tube, a grid (G) of the MOS tube is connected to a first level control pin of the signal output interface 1a, a source (D) of the MOS tube is connected to the channel control pin, and a drain (S) of the MOS tube is grounded.
In this embodiment, the first level control pin is connected to the gate (G) of the MOS transistor, and the channel control pin (SEL) is connected to the source (D) of the MOS transistor, so as to implement communication connection among the level shift circuit, the channel switching chip U2, and the signal output interface 1 a. Specifically, if the first level control pin is at a high level, after passing through the MOS transistor, the channel control pin (SEL) is at a low level, and at this time, the channel switching chip U2 controls the conduction of the debug signal output channel; if the first level control pin is at a low level, the channel control pin (SEL) passes through the MOS transistor and then is at a high level, and at this time, the channel switching chip U2 controls the USB2.0 signal channel.
Further, referring to fig. 5, the first connector 2a is a USB3.0 male connector, the USB3.0 male connector includes a second level control pin, the second level control pin is connected to a power supply, and after the USB3.0 male connector is plugged into the USB3.0 female connector, the first level control pin and the second level control pin are in contact conduction.
In this embodiment, the first connector 2a is a USB3.0 male connector, and the corresponding signal output interface 1a is a USB female connector. The first connector 2a comprises a second level control pin, the second level control pin is the 7 th pin of the first connector 2a, and because the 7 th pin of the first connector 2a is connected with the power supply, when the first connector 2a is plugged in the signal output interface 1a, the first level control pin is in contact conduction with the second level control pin, the signal output interface 1a is pulled high to be high level and is converted into low level through the level conversion circuit, and at the moment, when the channel control pin (SEL) is low level, the first input pin group (1D + and 1D-) is in conduction with the output pin group (D + and D-) to form a debugging signal output channel (1D and D connection), thereby realizing the transmission of TX/RX signals.
Furthermore, the signal type output by the debugging signal output channel is a TX/RX signal, and the signal conversion chip converts the TX/RX signal into a DP/DM signal and transmits the DP/DM signal to the master control device.
In this embodiment, when a debug signal output channel (formed by connecting 1D and D) is formed in the device 1 to be debugged, so as to transmit a TX/RX signal, after receiving the TX/RX signal, the first connector 2a converts the TX/RX signal through the signal conversion chip 2b, so that the TX/RX signal is converted into the DP/DM signal, and then the DP/DM signal is transmitted to the main control device through the second connector 2 c.
Furthermore, the signal input interface is electrically connected with the signal output interface to form a channel for transmitting USB2.0 signals.
In this embodiment, if the signal conversion device 2 is not used, the main control device 3 and the device to be debugged 1 are directly connected in a communication manner, specifically, the signal input interface 3a is directly plugged into the signal input interface 1a, and a USB2.0 signal channel (formed when 2D and D are connected) is directly formed in the device to be debugged 1, so that transmission of USB signals in the device to be debugged 1 to the main control device 3 is realized.
Further, the second connector 2c is a Micro USB2.0 connector.
In this embodiment, since the second connector 2c corresponds to the signal input interface 3a, if the second connector 2c is a Micro USB2.0 connector, the signal input interface 3a is also a Micro USB2.0 connector. Specifically, if the second connector 2c is a Micro USB2.0 male connector, the signal input interface 3a is a Micro USB2.0 female connector; on the contrary, if the second connector 2c is a Micro USB2.0 female connector, the signal input interface 3a is a Micro USB2.0 male connector.
Further, the model of the signal conversion chip 2b is CP2102, CH340 or FT 232.
In this embodiment, the signal conversion chip 2b has a plurality of types, which are selectable, and has been implemented to convert the TX/RX signal into the DP/DM signal.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A debugging system, characterized in that the debugging system comprises:
the device to be debugged comprises a signal output interface, and the signal output interface is used for outputting debugging information of the device to be debugged;
the signal conversion equipment comprises a first joint, a signal conversion chip and a second joint, the signal conversion chip is electrically connected with the first joint and the second joint, and the first joint is inserted into the signal output interface so as to realize the communication connection between the signal conversion chip and the equipment to be debugged;
the main control equipment comprises a signal input interface, and the second connector is inserted into the signal input interface so as to realize the communication connection between the signal conversion chip and the main control equipment.
2. The debugging system of claim 1 wherein the device to be debugged further comprises:
the channel switching chip is electrically connected with the signal output interface and comprises a USB2.0 signal channel and a debugging signal output channel, and the channel switching chip is used for controlling the conduction of the debugging signal output channel.
3. The debugging system of claim 2 wherein the channel switch chip is of the type PI3USB221ze and the signal output interface is a USB3.0 female.
4. The debugging system of claim 3, wherein the device to be debugged further comprises level shifting circuitry connecting the channel switching chip and the signal output interface.
5. The debugging system of claim 4 wherein the channel switch chip comprises: the USB device comprises a channel control pin, a first input pin group, a second input pin group and an output pin group, wherein when the channel control pin is at a low level, the first input pin group is conducted with the output pin group to form the debugging signal output channel, and when the channel control pin is at a high level, the second input pin group is conducted with the output pin group to form the USB2.0 signal channel;
the signal output interface comprises a first level control pin;
the level conversion circuit is an MOS tube, the grid electrode of the MOS tube is connected to the first level control pin of the signal output interface, the source electrode of the MOS tube is connected to the channel control pin, and the drain electrode of the MOS tube is grounded.
6. The debugging system of claim 5, wherein the first connector is a USB3.0 male connector, the USB3.0 male connector comprises a second level control pin, the second level control pin is connected to a power supply, and after the USB3.0 male connector is plugged into the USB3.0 female connector, the first level control pin and the second level control pin are in contact conduction.
7. The debugging system of claim 6, wherein the signal type output by the debugging signal output channel is a TX/RX signal, and the signal conversion chip converts the TX/RX signal into a DP/DM signal and transmits the DP/DM signal to the master device.
8. The debugging system of claim 1, wherein the signal input interface is electrically connected to the signal output interface to form a channel for transmitting USB2.0 signals.
9. The debugging system of claim 1 wherein the second connector is a Micro USB2.0 connector.
10. The debugging system of any one of claims 1-7 wherein the signal conversion chip has a model number CP2102, CH340, or FT 232.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010085717.6A CN111274076A (en) | 2020-02-10 | 2020-02-10 | Debugging system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010085717.6A CN111274076A (en) | 2020-02-10 | 2020-02-10 | Debugging system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111274076A true CN111274076A (en) | 2020-06-12 |
Family
ID=70997101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010085717.6A Pending CN111274076A (en) | 2020-02-10 | 2020-02-10 | Debugging system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111274076A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111984530A (en) * | 2020-07-24 | 2020-11-24 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Method and system capable of flexibly and dynamically configuring debugging interface |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204557471U (en) * | 2015-03-02 | 2015-08-12 | 合肥宝龙达信息技术有限公司 | A kind of novel USB turns UART serial communication circuit |
| CN105653410A (en) * | 2015-12-29 | 2016-06-08 | 湖南长城银河科技有限公司 | Device and method based on printing and outputting of debugging information of Phytium platform, and computer |
| CN105868140A (en) * | 2016-03-25 | 2016-08-17 | 乐视控股（北京）有限公司 | A mobile apparatus |
| CN107515341A (en) * | 2017-09-11 | 2017-12-26 | 歌尔科技有限公司 | A kind of test board |
| CN110502381A (en) * | 2019-08-19 | 2019-11-26 | 惠州Tcl移动通信有限公司 | Mobile terminal and its serial port debugging method, computer-readable medium |
-
2020
- 2020-02-10 CN CN202010085717.6A patent/CN111274076A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204557471U (en) * | 2015-03-02 | 2015-08-12 | 合肥宝龙达信息技术有限公司 | A kind of novel USB turns UART serial communication circuit |
| CN105653410A (en) * | 2015-12-29 | 2016-06-08 | 湖南长城银河科技有限公司 | Device and method based on printing and outputting of debugging information of Phytium platform, and computer |
| CN105868140A (en) * | 2016-03-25 | 2016-08-17 | 乐视控股（北京）有限公司 | A mobile apparatus |
| CN107515341A (en) * | 2017-09-11 | 2017-12-26 | 歌尔科技有限公司 | A kind of test board |
| CN110502381A (en) * | 2019-08-19 | 2019-11-26 | 惠州Tcl移动通信有限公司 | Mobile terminal and its serial port debugging method, computer-readable medium |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111984530A (en) * | 2020-07-24 | 2020-11-24 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Method and system capable of flexibly and dynamically configuring debugging interface |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8151018B2 (en) | Dual-mode data transfer of uncompressed multimedia contents or data communications | |
| CN107301148B (en) | USB Type-C interface conversion module, system and connection method | |
| US20160336694A1 (en) | Usb type-c connector module | |
| CN107203483A (en) | The interface circuit and electronic equipment of a kind of electronic equipment | |
| US7802047B2 (en) | Universal serial bus device and universal serial bus system including the same | |
| CN111274076A (en) | Debugging system | |
| CN110362058A (en) | The system tested for multiple interfaces | |
| CN107480085A (en) | Multiplex roles integrated test system | |
| CN106610909B (en) | System, device and method for separating half-duplex signals | |
| CN105320634A (en) | Data conversion system and control method thereof | |
| CN213987487U (en) | Mainboard interface expansion circuit and display device | |
| CN212659070U (en) | Adapter | |
| US20160117278A1 (en) | Peripheral protocol negotiation | |
| CN106484577A (en) | AccessPort device and method | |
| CN114281745A (en) | Docking station capable of switching connection of multiple uplink hosts | |
| CN103853572A (en) | Starting-up method and electronic equipment | |
| CN111782455A (en) | Portable equipment for testing screen end product | |
| US6895576B2 (en) | Method and system for device driver and operating system debugging of portable computers | |
| CN112821156A (en) | Electronic tags chip and TYPE-C data line | |
| KR101264179B1 (en) | Rs232 serial cable convertor module and rs232 serial cable convertor including the module | |
| CN220367375U (en) | Test circuit board, test device, intelligent terminal and test system | |
| CN210605696U (en) | Circuit for realizing OTG function by USB Type-A interface | |
| CN113836064B (en) | Serial port compatible with multiple bottom control ports | |
| CN219349492U (en) | Touch display device | |
| CN217983761U (en) | Interface connection device and vehicle |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 518000 501-2, building a, wisdom Plaza, 4068 Qiaoxiang Road, Gaofa community, Shahe street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: Shenzhen baoxinchuang Technology Co.,Ltd. Address before: 518000 floor 6, workshop 7, Tongfu industrial city, No. 351, tangxing Road, Tanglang community, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Applicant before: Shenzhen Baolong Daxin Technology Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20231113 Address after: 518000, 4th Floor, No. 31, Xiacun Community, Gongming Street, Guangming District, Shenzhen City, Guangdong Province Applicant after: Shenzhen Baoxinchuang Information Technology Co.,Ltd. Address before: 518000 501-2, building a, wisdom Plaza, 4068 Qiaoxiang Road, Gaofa community, Shahe street, Nanshan District, Shenzhen City, Guangdong Province Applicant before: Shenzhen baoxinchuang Technology Co.,Ltd. |