CN116013691A - High-voltage ceramic capacitor with high bias voltage and high capacity and preparation method thereof - Google Patents
High-voltage ceramic capacitor with high bias voltage and high capacity and preparation method thereof Download PDFInfo
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- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 20
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 239000000919 ceramic Substances 0.000 claims description 23
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 19
- 238000000227 grinding Methods 0.000 claims description 14
- 238000001035 drying Methods 0.000 claims description 13
- 238000007639 printing Methods 0.000 claims description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 13
- 238000000462 isostatic pressing Methods 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000002002 slurry Substances 0.000 claims description 8
- 239000000843 powder Substances 0.000 claims description 7
- 238000005245 sintering Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000002245 particle Substances 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- XJKVPKYVPCWHFO-UHFFFAOYSA-N silicon;hydrate Chemical compound O.[Si] XJKVPKYVPCWHFO-UHFFFAOYSA-N 0.000 claims description 3
- 238000010345 tape casting Methods 0.000 claims description 3
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 238000002791 soaking Methods 0.000 claims description 2
- 238000003466 welding Methods 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 4
- 239000000047 product Substances 0.000 description 52
- 230000035882 stress Effects 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 229910052573 porcelain Inorganic materials 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005266 casting Methods 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012216 screening Methods 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 241001268993 Heterochrosis Species 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000003618 dip coating Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000000498 ball milling Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000013530 defoamer Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000009659 non-destructive testing Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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Abstract
The invention discloses a high-voltage ceramic capacitor with bias voltage and large capacity and a preparation method thereof, which belong to the technical field of capacitors and solve the technical problems of bias voltage characteristics, capacity and product quality of the existing high-voltage ceramic capacitor; according to the invention, through optimizing the product design and the preparation process, the product electric resistance and bias voltage temperature characteristics are ensured, and meanwhile, large capacity is realized, and the stability, reliability and quality of the product are effectively improved.
Description
Technical Field
The invention relates to the technical field of capacitors, in particular to a high-voltage ceramic dielectric capacitor with bias voltage and high capacity and a preparation method thereof.
Background
The high-voltage multilayer ceramic capacitor (high-voltage MLCC for short) has small volume, high voltage shock resistance, high temperature shock resistance, moisture resistance, mechanical shock resistance and other capabilities, has good environmental adaptability and high reliability, is widely applied to the fields of aviation, aerospace, ships and the like, and is an important element in a switching power supply (input filter, resonator, resonant circuit, buffer circuit, output filter), a voltage multiplier circuit and a traveling wave tube power supply circuit, and mainly plays roles of high-voltage coupling, direct current blocking, multi-path high voltage generation and the like.
With the continuous development of the application field of users, higher requirements are put on the performance and reliability of products, but the bias characteristics and the capacity of the existing series products are still to be improved, and the limitation of the process manufacturing of the products leads to the fact that the stability, the reliability and the quality of the products cannot meet the higher requirements.
Disclosure of Invention
The invention aims to solve the technical problems of the existing high-voltage ceramic capacitor in terms of bias characteristics, capacity and product quality, and aims to provide the high-voltage ceramic capacitor with bias and large capacity and the preparation method thereof, thereby realizing the technical effects of good bias characteristics, large capacity, stable and reliable product and improved quality.
The invention is realized by the following technical scheme:
the utility model provides a high-voltage ceramic dielectric capacitor with bias voltage large capacity, includes terminal electrode, dielectric layer and internal electrode, the printing has the internal electrode figure on the internal electrode, dielectric layer and internal electrode are crisscross to be stacked and set up, internal electrode figure four corners is the circular arc, the internal electrode includes internal electrode one, internal electrode two and internal electrode three, internal electrode one, internal electrode two, internal electrode three and middle dielectric layer form two series connection's condenser, dielectric layer thickness is 92 + -5 um.
Further, the radius of the inverted arc is 0.03mm.
Further, the electrode margin between the first inner electrode and the second inner electrode is 1.0 plus or minus 0.1mm, and the electrode margin at the three end parts of the inner electrode is 0.45 plus or minus 0.1mm.
Further, the facing length of the inner electrode is 4.0+/-0.4 mm.
The invention also provides a preparation method of the high-voltage ceramic dielectric capacitor with the bias voltage and the large capacity, which comprises the following steps:
s1, manufacturing a ceramic dielectric film, and printing an inner electrode pattern on the ceramic dielectric film, wherein the printing thickness of the inner electrode pattern is controlled to be 2-3um, and the inner electrode pattern is overlapped in a staggered way to obtain a green bar block;
s2, carrying out temperature isostatic pressing treatment on the bar block, and cutting into a chip green body;
s3, removing organic matters in the green body and sintering;
s4, placing the sintered chip and the grinding medium in chamfering equipment, carrying out ultrasonic cleaning after the first chamfering, and carrying out secondary chamfering, wherein the first chamfering grinding medium adopts alumina balls, silicon carbide powder and water, and the second chamfering grinding medium adopts alumina balls, alumina powder and water;
s5, respectively soaking and sealing upper-end slurry at two ends of the chip, drying, and then burning the end for treatment;
s6, electroplating a blocking layer and a welding layer on the end of the chip to form a terminal electrode with a three-layer structure, thereby obtaining the high-voltage ceramic dielectric capacitor.
Further, the step S1 of manufacturing a ceramic dielectric film sheet specifically includes: the prepared ceramic slurry is uniformly coated on a PET carrier tape through a tape casting head, a ceramic dielectric film is formed after drying, the tape is delayed in flow, the carrier tape speed is 12m/min, the feeding pressure is 0.258MPa, and the temperature of a drying channel is 60-90 ℃.
Further, the bar block is subjected to heat drying before the step S2 of temperature isostatic pressing treatment, wherein the heat drying temperature is 65 ℃, the heat drying time is 30min, the temperature isostatic pressing pressure is 6000PSI, and the temperature isostatic pressing time is 30min.
Further, in step S4, the volume ratio of the alumina balls, the silicon carbide powder and the water in the first chamfering grinding medium is 15:4:25, and the volume ratio of the alumina balls, the alumina powder and the water in the second chamfering grinding medium is 3:4:5.
Further, in step S4, the diameter of the alumina balls is 3-4mm, the particle size of the silicon carbide powder is 1200 meshes, and the particle size of the alumina powder is 2000 meshes.
Further, in step S4, the first chamfering time is 20h, the rotation speed is 65rpm, the second chamfering time is 12h, and the rotation speed is 65rpm.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the invention designs and optimizes the product structure, improves the edge field intensity of the capacitor by reversing the arc of the electrode pattern, prevents the tip discharge, improves the internal field intensity distribution by suspending the electrode arrangement, improves the voltage withstand capability and the reliability of the product, ensures the electric resistance and the bias temperature characteristic of the product by optimizing parameters such as the thickness of a dielectric layer, the margin of an electrode, the dead length of an inner electrode and the like, and realizes high capacity at the same time, so that the capacity change rate of the product is less than or equal to +/-15% when no bias is applied, the capacity change rate is not more than-40% -15% under the bias of 0.5 times rated voltage, and the capacity can reach 198000 ～ 242000pF.
2. When the invention is used for printing the inner electrode, the printing thickness of the inner electrode is controlled to be 2-3um, the electric performance and the internal structure quality of the product can be ensured, the risks of layering, dark field heterochrosis and crack generation are reduced, and the product quality is improved.
3. According to the invention, the electrode layer and the dielectric layer are tightly combined under the action of certain pressure by adopting the temperature isostatic pressing, so that the compactness of the sintered porcelain body can be effectively improved. Meanwhile, the proper temperature isostatic pressure and time are set, so that the problems of layering and side cracking during cutting caused by too small pressure and difficult pressing of products are avoided, and meanwhile, the problems of unfavorable cutting of products caused by too large pressure and easy deformation or hardening after lamination are also avoided, thereby improving the stability and quality of the products.
4. The invention carries out twice chamfering on the sintered chip, the first chamfering aims at enabling the corners of the chip to be rolled and polished smoothly, eliminating the corner stress, and simultaneously leading out the inner electrode so as to be beneficial to the full contact of the inner electrode and the outer electrode, thereby ensuring the electric performance of the product, and the second chamfering can remove the silicon carbide powder attached to the product in the first step besides eliminating the corner stress, solve the problem that the end electrode is not tight with the porcelain body after the silver coating is carried out due to the attachment of the silicon carbide powder on the surface of the product, and further ensure the reliability and the quality of the product.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a schematic perspective view of a capacitor according to the present invention;
fig. 2 is a cross-sectional view of a capacitor of the present invention.
Fig. 3 is a schematic plan view of the internal electrode pattern.
In the drawings, the reference numerals and corresponding part names:
the electrode comprises a 1-end electrode, a 2-protective sheet, a 3-dielectric layer, a 4-inner electrode, a 401-inner electrode pattern, a 402-inverted arc, a 403-inner electrode I, a 404-inner electrode II and a 405-inner electrode III.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: no such specific details are necessary to practice the invention. In other instances, well-known structures, circuits, materials, or methods have not been described in detail in order not to obscure the invention.
Throughout the specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an example," or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Moreover, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and that the illustrations are not necessarily drawn to scale. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
The embodiment provides a high-voltage ceramic capacitor with high bias voltage and high capacity, as shown in fig. 1-3, fig. 1 is a schematic perspective view of the capacitor of the invention, fig. 2 is a cross-sectional view of the capacitor of the invention, the cross-sectional view only shows a part of the structure, fig. 3 is a schematic plan view of an internal electrode pattern, and the schematic view of the electrode pattern also only shows a part of the structure.
The high-voltage ceramic capacitor comprises a protective sheet 2, end electrodes 1, a dielectric layer 3 and an inner electrode 4, wherein an inner electrode pattern 401 is printed on the inner electrode 4, the dielectric layer 3 and the inner electrode 4 are arranged in the protective sheet 2, the end electrodes 1 are arranged at two ends and are tightly connected with the inner electrode 4, and electric properties are led out through metal conduction between the inner electrode 4 and the end electrodes 1.
The dielectric layers 3 and the internal electrodes 4 are staggered and laminated, and the reverse arcs 402 are formed at four corners of the internal electrode graph 401, as shown in fig. 3, the reverse arc 402 design of the internal electrode graph 401 can improve the edge field intensity of the capacitor and prevent the tip discharge; the inner electrode 4 includes an inner electrode one 403, an inner electrode two 404 and an inner electrode three 405, and the inner electrode one 403, the inner electrode two 404, the inner electrode three 405 and the intermediate dielectric layer 3 form two capacitors connected in series, as shown in fig. 2. The invention adopts the series electrode pattern to increase the anti-electric strength of the capacitor, and according to the principle of series voltage division, the more the internal series capacitors are, the smaller the voltage born by a single capacitor is, and meanwhile, the arrangement of the suspension electrodes can improve the internal field intensity distribution and the voltage resistance and the reliability of the product.
The thickness G of the dielectric layer 3 is 92+/-5 um (as marked in fig. 2), and as the dielectric thickness is an important guarantee of the product electric resistance strength and bias temperature characteristics, in order to ensure good performance of the product under long-time electric stress and thermal stress, the invention adds a certain thickness on the basis of the minimum dielectric thickness calculated theoretically, optimizes the thickness of the dielectric layer 3 and can further ensure the reliability of the product.
The radius of the inverted arc 402 is 0.03mm, the electrode margin C between the first inner electrode 403 and the second inner electrode 404 is 1.0±0.1mm (as marked in fig. 2), the electrode margin a=f=0.45±0.1mm (as marked in fig. 2) at the end of the third inner electrode 405, and the facing length b=d=4.0±0.4mm (as marked in fig. 2) of the inner electrode 4.
The invention designs and optimizes the product structure, improves the edge field intensity of the capacitor by reversing the arc of the electrode pattern, prevents the tip discharge, improves the internal field intensity distribution by suspending the electrode arrangement, improves the voltage withstand capability and reliability of the product, ensures the product anti-electric strength and bias temperature characteristics by optimizing parameters such as the thickness of a dielectric layer, the margin of an electrode, the dead length of an inner electrode and the like, and simultaneously realizes large capacity, so that the capacity change rate of the product is less than +/-15% when no bias is applied, the capacity change rate is not more than-40% -15% when the product is biased by 0.5 times of rated voltage, and the capacity can reach 198000 ～ 242000pF.
Example 2
The embodiment provides a preparation method of a high-voltage ceramic dielectric capacitor with bias voltage and large capacity, which comprises the following steps:
step one, slurry preparation: mixing materials such as porcelain, an organic adhesive and a solvent according to a proportion, and uniformly mixing the materials in a ball milling mode to prepare porcelain slurry with certain fluidity, wherein the mass ratio of the porcelain to the organic adhesive to the solvent is 1:0.33:0.41.
Step two, casting: and uniformly coating the prepared ceramic slurry on a PET carrier tape through a casting head, and drying to form a ceramic dielectric film sheet to provide a dielectric material for the capacitor. Wherein, when the tape casting operation is carried out, the carrier speed is 12m/min, the feeding pressure is 0.258MPa, and the temperature of a drying tunnel is 60-90 ℃. The casting process parameters are continuously optimized through experiments, so that the cracking of the ceramic dielectric film can be effectively reduced, and the defects of pinholes, bubbles, impurities, black and white lines and the like on the surface of the ceramic dielectric film are avoided.
Step three, printing and stacking: the method comprises two steps of silver printing and film laminating, wherein the inner electrode paste is printed on a printing object by extruding a scraper through a mesh in the middle of a silk screen on a ceramic dielectric film sheet which is cast by utilizing a silk screen printing principle to form an inner electrode pattern with a certain shape and size, and the inner electrode structure of the capacitor is formed by utilizing a dislocation and film laminating method, wherein the printing thickness of the inner electrode pattern is controlled to be 2-3 mu m.
Step four, temperature isostatic pressing and cutting: and carrying out temperature isostatic pressing and cutting on the manufactured multi-layer structural bar block to prepare the multi-layer ceramic dielectric capacitor green chip. The temperature static pressure is to firmly laminate an inner electrode layer and a medium layer of the bar block after the film lamination is printed by adopting a certain pressure, the bar block is required to be heated before the temperature isostatic pressure treatment, the heating temperature is 65 ℃, the heating time is 30min, the temperature isostatic pressure is 6000PSI, and the temperature isostatic pressure time is 30min. The cutting is to cut the bar block into single-chip green bodies by a cutting machine.
Fifthly, discharging and sticking: the cut green body contains organic matters such as adhesive, defoamer, dispersing agent and the like, so that the organic matters can be slowly removed by discharging and sticking, most of the organic matters in the product are removed before sintering, and the deformation and layering of the product caused by rapid decomposition and volatilization of the organic matters in high-temperature sintering are avoided.
Step six, sintering: the sintering temperature is 1105+/-10 ℃, and the high-temperature sintering process ensures that the green body is densified at a higher temperature to complete the expected physicochemical reaction, so that the green body becomes a compact MLCC with medium and internal electrode structure, and the compact MLCC has high mechanical strength and excellent electrical performance.
Step seven, chamfering: the chip and the medium are placed in chamfering equipment, the edges and corners of the chip are polished smoothly by the grinding action between the grinding medium and the chip at a certain rotating speed, the edge and corner stress is eliminated, and meanwhile, the inner electrode is led out, so that the inner electrode and the outer electrode are in full contact, and the electric performance of a product is ensured.
The first chamfering, the grinding medium is 1500ml alumina ball (diameter is 3-4 mm) +400ml silicon carbide powder (1200 mesh) +2500ml water, the chamfering time is 20h, the rotating speed is 65rpm, the step aims at chamfering the chip edge, and simultaneously, the inner electrode is led out higher to prepare for the subsequent coating end;
the ultrasonic cleaning is carried out before the second chamfering, 1500ml of alumina balls (with the diameter of 3-4 mm) +2000ml of alumina powder (2000 meshes) +2500ml of water are selected as grinding media, the chamfering time is 12h, the rotating speed is 65rpm, the purpose of the step is to further chamfer the edges of the chip and remove silicon carbide powder (a part which cannot be cleaned) still attached to the product in the first step, and the problem that after silver burning is carried out on the coated end due to the attachment of the silicon carbide powder on the surface of the product, the end electrode and the ceramic body (edge position) are not tight is solved, so that the reliability and the quality of the product are ensured.
Step eight, coating: and (3) respectively dip-coating upper-end slurry at two ends of the capacitor in a dip-coating mode, and drying in a drying furnace to form an outer electrode of the capacitor.
Step nine, silver burning: and (3) carrying out high-temperature end burning treatment on the end-capped chip, wherein the silver burning temperature is 800+/-10 ℃, so that organic components in the end are completely decomposed, the end is sintered and compact, and the inner electrode and the outer electrode are well combined.
Step ten, electroplating: under the action of an electric field, metal ions are diffused and migrated towards the direction of the terminal electrode, electrons are obtained at the cathode and reduced into metal, so that the anode metal is electroplated on the surface of the terminal electrode, and a barrier layer (nickel) and a weldable layer (tin-lead) are plated on the bottom silver layer in sequence to form the terminal electrode with a three-layer structure.
Step eleven, semi-finished product measurement: early failure products are removed through 100% electrical property tests (voltage resistance, damp insulation resistance, capacitance and loss tangent) and appearance inspection, and whether the product size, the electric resistance and the internal structure meet the requirements is confirmed through sampling tests such as external dimension, breakdown voltage, DPA and the like.
Step twelve, screening (temperature impact, high temperature load screening, finished product measurement): certain temperature stress and electric stress are applied to 100% of the product, so that defects existing in the product are further expanded, and the product is identified through performance test, so that early failure products are effectively removed.
Thirteenth, ultrasonic nondestructive testing: the method utilizes the penetrating and reflecting characteristics of ultrasonic waves to nondestructively detect 100% of the chip capacitor, and identifies and eliminates products with air defects inside.
Fourteen, appearance after screening: the capacitor is subjected to 100% appearance inspection by adopting an appearance inspection machine or a microscope sorting mode so as to eliminate products with appearance which does not meet the requirements of detailed specifications.
When the invention is used for printing the inner electrode, the printing thickness of the inner electrode is controlled to be 2-3um, so that the electrical property and the internal structure quality of the product can be ensured, and the risks of layering, dark field heterochrosis and crack generation are reduced.
According to the invention, the electrode layer and the dielectric layer are tightly combined under the action of certain pressure by adopting the temperature isostatic pressing, so that the compactness of the sintered porcelain body can be effectively improved. Meanwhile, the proper temperature isostatic pressure and time are set, so that the problems that the pressure is too small, the product is not easy to press firmly, layering and side cracking are caused during cutting, and meanwhile, the problems that the product is easy to deform or harden after lamination and is unfavorable for cutting of the product are avoided.
The invention carries out twice chamfering on the sintered chip, the first chamfering aims at enabling the corners of the chip to be rolled and polished smoothly, eliminating the corner stress, and simultaneously leading out the inner electrode so as to be beneficial to the full contact of the inner electrode and the outer electrode, thereby ensuring the electric performance of the product, and the second chamfering can remove the silicon carbide powder attached to the product in the first step besides eliminating the corner stress, solve the problem that the end electrode is not tight with the porcelain body after the silver coating is carried out due to the attachment of the silicon carbide powder on the surface of the product, and further ensure the reliability and the quality of the product.
The invention relates to a high-voltage ceramic capacitor: package size 4040, temperature coefficient: BR, rated voltage: 1000V, nominal capacity: 220000pF, capacity precision: 10% of the total weight of the capacitor, the electrical properties that the capacitor can meet and the main test requirements are shown in tables 1 and 2 below.
TABLE 1 Main Performance index
TABLE 2 requirements for product testing
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The utility model provides a take high-voltage ceramic capacitor of biasing large capacity, includes terminal electrode (1), dielectric layer (3) and internal electrode (4), print on internal electrode (4) has internal electrode figure (401), its characterized in that, dielectric layer (3) and internal electrode (4) are crisscross to be stacked and set up, internal electrode figure (401) four corners arc (402) down, internal electrode (4) include internal electrode one (403), internal electrode two (404) and internal electrode three (405), internal electrode one (403), internal electrode two (404), internal electrode three (405) and medium layer (3) in centre form two capacitors of establishing ties, dielectric layer (3) thickness is 92+ -5 um.
2. A high voltage ceramic capacitor with bias voltage of large capacity according to claim 1, characterized in that the radius of the inverted arc (402) is 0.03mm.
3. The high-voltage ceramic capacitor with bias voltage and high capacity according to claim 1, wherein the electrode margin between the first inner electrode (403) and the second inner electrode (404) is 1.0+ -0.1 mm, and the electrode margin at the end of the third inner electrode (405) is 0.45+ -0.1 mm.
4. A high voltage ceramic capacitor with bias voltage of large capacity according to claim 1, wherein the facing length of said inner electrode (4) is 4.0±0.4mm.
5. The preparation method of the high-voltage ceramic capacitor with the bias voltage and the large capacity is characterized by comprising the following steps:
s1, manufacturing a ceramic dielectric film, and printing an inner electrode pattern on the ceramic dielectric film, wherein the printing thickness of the inner electrode pattern is controlled to be 2-3um, and the inner electrode pattern is overlapped in a staggered way to obtain a green bar block;
s2, carrying out temperature isostatic pressing treatment on the bar block, and cutting into a chip green body;
s3, removing organic matters in the green body and sintering;
s4, placing the sintered chip and the grinding medium in chamfering equipment, carrying out ultrasonic cleaning after the first chamfering, and carrying out secondary chamfering, wherein the first chamfering grinding medium adopts alumina balls, silicon carbide powder and water, and the second chamfering grinding medium adopts alumina balls, alumina powder and water;
s5, respectively soaking and sealing upper-end slurry at two ends of the chip, drying, and then burning the end for treatment;
s6, electroplating a blocking layer and a welding layer on the end of the chip to form a terminal electrode with a three-layer structure, thereby obtaining the high-voltage ceramic dielectric capacitor.
6. The method for manufacturing a high-voltage ceramic capacitor with high bias voltage and high capacity as claimed in claim 5, wherein the step S1 of manufacturing the ceramic dielectric film comprises the following steps: the prepared ceramic slurry is uniformly coated on a PET carrier tape through a tape casting head, a ceramic dielectric film is formed after drying, the tape is delayed in flow, the carrier tape speed is 12m/min, the feeding pressure is 0.258MPa, and the temperature of a drying channel is 60-90 ℃.
7. The method for manufacturing a high-voltage ceramic capacitor with high bias voltage and high capacity according to claim 5, wherein the block is heated before the step S2 of isostatic pressing treatment, the heating temperature is 65 ℃, the heating time is 30min, the isostatic pressing pressure is 6000PSI, and the isostatic pressing time is 30min.
8. The method of manufacturing a high-voltage ceramic capacitor with a high bias voltage according to claim 5, wherein in step S4, the volume ratio of alumina balls, silicon carbide powder and water in the first chamfering grinding medium is 15:4:25, and the volume ratio of alumina balls, alumina powder and water in the second chamfering grinding medium is 3:4:5.
9. The method for manufacturing a high-voltage ceramic capacitor with a high bias voltage according to claim 5, wherein in step S4, the diameter of the alumina balls is 3-4mm, the particle size of the silicon carbide powder is 1200 mesh, and the particle size of the alumina powder is 2000 mesh.
10. The method of manufacturing a high-voltage ceramic capacitor with a high bias voltage according to claim 5, wherein in step S4, the first chamfering time is 20h, the rotation speed is 65rpm, the second chamfering time is 12h, and the rotation speed is 65rpm.
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