JP2002231558A - Laminated ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax a mechanical stress induced by the mismatch of a ceramic dielectric layer with an inner electrode layer and a mechanical deformation induced by an inverse piezoelectric effect, thereby providing a high-performance laminated ceramic capacitor superior in stability of electric characteristics and reliability. SOLUTION: A laminated ceramic capacitor element is composed of an active layer composed of a ceramic dielectric layer and an inner electrode layer and reactive layers of ceramic dielectric layers formed on the upper and lower sides of the active layer so as to sandwich it and openings are formed at the ends of the inner electrode layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor widely used for medium and high voltages in a switching power supply circuit, a DC-DC converter circuit, a lighting inverter circuit and the like.

[0002]

2. Description of the Related Art Conventionally, various chip-type electronic components mounted on a printed circuit board have been known. For example, there is a multilayer ceramic capacitor as an example. The conventional technology of this multilayer ceramic capacitor will be described below with reference to the drawings.

FIG. 5 is a sectional view showing a conventional multilayer ceramic capacitor. The multilayer ceramic capacitor is shown in FIG.
As shown in (1), an effective layer is formed by alternately laminating the ceramic dielectric layers 13 and the internal electrode layers 12a, 12b, 12c, and an invalid layer composed of a plurality of ceramic dielectric layers is formed above and below the effective layer. The internal electrodes 12b, 12c
Is connected to a lower external electrode 14 provided on both end surfaces of the multilayer body 11, and an upper external electrode 15 is provided on the lower external electrode 14.

FIG. 6 is a partially enlarged view showing a conventional multilayer ceramic capacitor, and shows a portion A in FIG. 5 in an enlarged manner. As is apparent from FIG. 6, the conventional multilayer ceramic capacitor includes internal electrode layers 12a and 12b.
In this case, there is no gap such as a gap at the end not connected to the lower external electrode 14, and the internal electrode layers 12a and 12b are structurally restrained.

[0005]

However, in such a conventional structure, the stress generated at the interface between the internal electrode layer and the ceramic dielectric layer is concentrated at the end of the internal electrode layer, and internal defects such as cracks occur. However, there is a problem that the electrical characteristics are deteriorated and the reliability is lowered. In addition, the multilayer ceramic capacitor with the conventional configuration has an internal distortion due to the inverse piezoelectric effect that occurs especially during use for medium and high pressure,
In particular, there have been problems such as structural defects occurring at the interface between the internal electrode layer and the ceramic dielectric layer, and undesired noise in electronic circuits.

Therefore, the present invention solves the above problems,
An object of the present invention is to provide a high-performance multilayer ceramic capacitor having excellent stability and reliability of electrical characteristics, in which stress induced by mismatch between a ceramic dielectric layer and an internal electrode layer and distortion due to an inverse piezoelectric effect are alleviated. Things.

[0007]

To achieve this object, a chip-type electronic component according to the present invention comprises an effective layer having an internal electrode layer between a first plurality of ceramic dielectric layers and a second plurality of ceramic dielectric layers. A chip-type multilayer ceramic capacitor comprising: a base having an ineffective layer made of a ceramic dielectric layer; and a pair of external electrodes provided at both ends of the base and electrically connected to the internal electrode layer. Wherein, among the internal electrode layers provided between the first plurality of ceramic dielectric layers, a void is formed at an end of the internal electrode layer that is not connected to the external electrode.

As a result, the stress induced by the mismatch between the expansion and contraction of the ceramic dielectric layer and the internal electrode layer and the mechanical strain generated by the inverse piezoelectric effect are alleviated, so that structural defects such as cracks are formed inside. Thus, a high-performance chip-type multilayer ceramic capacitor having excellent electrical characteristics and excellent reliability can be obtained.

Further, the multilayer ceramic capacitor of the present invention is a chip type capacitor in which a void is formed at an end of the internal electrode layer which is not connected to an external electrode among internal electrode layers provided between ceramic dielectric layers. The multilayer ceramic capacitor is provided with a lead terminal or the like and processed into a mold type and a lead type, and can be selectively used according to the user's demand by mainly utilizing the characteristics of each type for medium and high pressure.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is an effective layer comprising an internal electrode layer provided between a first plurality of ceramic dielectric layers and an ineffective layer comprising a second plurality of ceramic dielectric layers. And a pair of external electrodes provided at both ends of the substrate and electrically connected to an internal electrode layer, wherein the first plurality of ceramic dielectric capacitors are provided. Voids are formed at the ends of the internal electrode layers that are not connected to the external electrodes, of the internal electrode layers provided between the body layers, thereby reducing the expansion and contraction of the ceramic dielectric layer and the internal electrode layers. Since the stress induced by the mismatch and the stress concentrated at the end of the internal electrode layer and the mechanical strain generated by the inverse piezoelectric effect are alleviated by the air gap, there are no structural defects such as cracks inside, and the electrical characteristics and circuit resistance Excellent reliability such as substrate bending And an effect that high performance can be realized a laminated ceramic capacitor.

According to a second aspect of the present invention, there is provided an effective layer having an internal electrode layer provided between the first plurality of ceramic dielectric layers and an ineffective layer comprising the second plurality of ceramic dielectric layers. A mold provided with a base and a pair of external electrodes provided at both ends of the base and electrically connected to the internal electrode layer, and terminals respectively connected to the external electrodes, wherein the base and the external electrodes are embedded with resin; Wherein a void is formed at an end of an internal electrode layer not connected to an external electrode among internal electrode layers provided between the first plurality of ceramic dielectric layers. The stress induced at the end of the internal electrode layer and the mechanical strain caused by the inverse piezoelectric effect are alleviated by the air gap, which is caused by the mismatch between the expansion and contraction of the ceramic dielectric layer and the internal electrode layer. To Since there is no structural defect such as a crack, and even if a structural defect occurs, it is a mold type, so it is a surface mount type medium / high pressure which has excellent durability against mechanical stress such as circuit board bending resistance. Has the function of realizing a multilayer ceramic capacitor for use.

According to a third aspect of the present invention, there is provided an effective layer having an internal electrode layer provided between the first plurality of ceramic dielectric layers, and an ineffective layer comprising the second plurality of ceramic dielectric layers. A lead provided on both ends of the base, a pair of external electrodes electrically connected to the internal electrode layer, and lead wires respectively connected to the external electrodes, wherein the base and the external electrodes are covered with a resin; Type multilayer ceramic capacitor, wherein a void is formed at an end of an internal electrode layer not connected to an external electrode among internal electrode layers provided between a first plurality of ceramic dielectric layers. It has excellent electrical characteristics, there is no risk of structural defects such as cracks inside, and since the lead wires are soldered to the circuit board, mechanical stress such as bending resistance of the circuit board is reduced. Lamination for medium and high pressures that are not applied at all Has the effect of the La ceramic capacitor can be realized.

According to a fourth aspect of the present invention, in the multilayer ceramic capacitor according to the first, second and third aspects, an ineffective layer is provided on both sides of the effective layer so as to sandwich the effective layer. In addition, it has the effect of improving reliability and realizing a high-quality multilayer ceramic capacitor.

According to a fifth aspect of the present invention, there is provided a base having an internal electrode layer between ceramic dielectric layers, and a pair of external electrodes provided at both ends of the base and electrically connected to the internal electrode layer. Chip-type multilayer ceramic capacitor, wherein a void is formed at the end of the internal electrode layer that is not connected to the external electrode, so that stress concentrated on the end of the internal electrode layer and reverse It has an effect of reducing mechanical distortion generated by the piezoelectric effect.

In the multilayer ceramic capacitor of the present invention, a titanate such as BaTiO ₃ , SrTiO ₃ , MgTiO ₃ is mainly used as a main component compound constituting a ceramic dielectric layer, and a metal constituting an internal electrode layer is used. As an alternative, an Ag-Pd-based or Cu-based material may be used in addition to Ni. In addition, as a lower external electrode that is fired simultaneously with the laminated body in the method, Ni as described above is used.
Can be applied, but in that case, an Ag-based external electrode is mainly used. Further, it is possible to use only Cu for the external electrode.

Hereinafter, the multilayer ceramic capacitor of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of a multilayer ceramic capacitor according to Embodiment 1 of the present invention, in which 11 is a laminated body, 12a, 12b and 12c are internal electrode layers, and 13 is a ceramic dielectric layer. , 14 are lower external electrodes,
Reference numeral 15 denotes an upper external electrode.

FIG. 2 is a partially enlarged view showing the multilayer ceramic capacitor according to the first embodiment of the present invention.
A part of FIG. 1 is enlarged. In addition, 16 is a space.

As shown in FIG. 2, a gap 16 is formed at an end of the internal electrode layers 12a and 12b which is not connected to the lower external electrode 14.

Here, a method for manufacturing the multilayer ceramic capacitor will be described.

Predetermined amounts of BaTiO ₃ powder as the main component and each powder of the additives were weighed by an electronic balance, and mixed with a sintering aid component in a ball mill for 20 hours. The mixture was filtered through a silk screen, placed in a stainless steel vat covered with a Teflon (registered trademark) sheet, and dried. The dried mass was pulverized in an alumina mortar and then heat-treated to obtain a slurry powder.

Next, a predetermined amount of the slurry powder was wetted by mixing with a solvent and a plasticizer. After the wetting, a sheet forming slurry was prepared by applying a vehicle made of a polyvinyl butyral resin.

Next, the slurry was filtered through a 150-mesh silk screen and then formed into a film to obtain a green ceramic sheet. Then, using the ceramic raw sheet and the internal electrode sheet prepared from the Ni paste, the layers were laminated according to a predetermined lamination specification by a transfer method, and then cut to obtain a green chip.

Next, after chamfering the obtained green chip, a Ni paste to be a lower external electrode was applied to both end surfaces thereof, dried, and then degreased by a degreasing furnace. Then, firing in a reducing atmosphere was performed using a rotary atmosphere furnace. It was maintained at a temperature of 1250 ° C. for 2 hours in an oxygen partial pressure atmosphere two orders of magnitude lower than the equilibrium oxygen partial pressure of Ni adjusted by green gas, CO ₂ and N ₂ .

Then, an Ag paste as an upper layer external electrode is applied from both end surfaces to the side surfaces of the fired chip, baked in the air, and then subjected to Ni plating and Sn plating to form a chip-type laminate according to the first embodiment. The ceramic capacitor was completed.

Next, the multilayer ceramic capacitor was embedded in a thermosetting resin and polished, and the cross section was observed with a metallographic microscope.

As a result, as shown in FIG. 1, the ceramic dielectric layer 13 and the internal electrode layers 12a, 12b,
12c as an ineffective layer above and below an effective layer serving as a capacitance acquisition layer formed by alternately stacking the ceramic dielectric layers 12c and 12c.
3 are laminated to form a laminated body 11. One end of each of the internal electrode layers 12 b and 12 c is joined to the opposing lower external electrode 14, and the upper external electrode 14 is placed on the lower external electrode 14. 15 were provided.

Further, as shown in FIG.
A gap 16 having a size of about several μm was formed at an end of each of the ends a and 12b that was not connected to the lower external electrode 14. Also, the ceramic dielectric layer 13 and the internal electrode layer 12
There were no defects such as cracks in the interface with a, 12b, and 12c and in the vicinity thereof, and in the vicinity of the voids formed at the ends of the internal electrode layers 12a, 12b, and 12c, and had a favorable internal structure.

Next, the chip-type multilayer ceramic capacitor according to the first embodiment was subjected to a board bending resistance test.

The board bending test is an important evaluation item for judging the reliability of chip-type electronic components. After soldering the device under test to a dedicated printed circuit board, three-point bending is performed with a dedicated jig. The capacitance is measured while being added, and the bending width (mm) of the substrate at the time when the capacitance value sharply decreases is regarded as the substrate bending resistance. Normally, cracks often occur in the DUT at the time when the capacitance value sharply decreases.

The chip-type multilayer ceramic capacitor according to the first embodiment did not decrease in capacitance value even when the deflection width reached 10 mm, and was excellent in reliability.

As described above, according to the chip-type multilayer ceramic capacitor of the first embodiment, there is no defect such as a crack inside, and the internal stress generated by the mechanical stress such as bending resistance of the substrate and the reverse piezoelectric effect. Is alleviated, so that a multilayer ceramic capacitor having excellent reliability and durability can be realized.

(Embodiment 2) FIG. 3 is a sectional view of a molded multilayer ceramic capacitor according to Embodiment 2 of the present invention, in which 21 is a laminate, 22a, 22b and 22c.
Is an internal electrode layer, 23 is a ceramic dielectric layer, 24 is a lower external electrode, and 25 is an upper external electrode. 26 is a thermosetting resin, and 27 is a terminal.

Also in the second embodiment, the first embodiment
Similarly, the ceramic dielectric layer 23 and the internal electrode layer 22
a, 22b, and 22c are alternately stacked, and a ceramic dielectric layer 23 is stacked as an ineffective layer above and below an effective layer serving as a capacitance acquisition layer formed as a capacitance acquisition layer. The internal electrode layers 22b, 2
A lower external electrode 24 electrically connected to 2c is provided, and an upper external electrode 25 is provided thereon. In addition, the end portions of the internal electrode layers 22a, 22b, and 22c that are not connected to the lower external electrodes 24 are provided with the gaps 16 shown in FIG.
Are formed.

In the molded multilayer ceramic capacitor according to the second embodiment, the terminal 27 is connected to the upper external electrode 25, and the laminated body and the lower external electrode 2 are further connected.
4. A chip-type multilayer ceramic capacitor composed of the upper external electrodes 25 and a part of the terminals 27 are embedded in a thermosetting resin 26 as an exterior material.

That is, the conductive terminals 27 are drawn out from both ends of the laminated body 21 embedded in the thermosetting resin 26, and can be surface-mounted on the circuit board via the terminals 27.

In the method of manufacturing a molded multilayer ceramic capacitor according to the second embodiment, terminals are provided on both end surfaces of a chip-type multilayer ceramic capacitor element manufactured by the same procedure as in the first embodiment. The element body was embedded in an epoxy thermosetting resin to complete the device.

Next, the molded multilayer ceramic capacitor was embedded in a resin and polished, and the cross section was observed with a metallographic microscope. As a result, as in the first embodiment, as shown in FIG. The end of the internal electrode layers 22a and 22b that is not connected to the lower external electrode 24 has a thickness of several micrometers.
A void 16 having a size as large as the above was formed. Further, the ceramic dielectric layer 23 and the internal electrode layers 22a, 22b, 22
c and the vicinity thereof and the internal electrode layers 22a, 22b,
There was no defect such as a crack near the void formed at the end of 22c, and the structure had a good internal structure.

Next, when a bending resistance test was performed on the fabricated molded multilayer ceramic capacitor, the capacitance value did not decrease even when the deflection width exceeded 15 mm, and the chip resistance of the chip of the first embodiment was reduced. It had a higher level of substrate bending resistance than the monolithic ceramic capacitor. Further, in the chip-type multilayer ceramic capacitor of the first embodiment, a creeping leak may occur for an abnormal voltage that is out of specification due to condensation on the element surface or the like. However, the mold-type multilayer ceramic capacitor of the second embodiment may be used. Was reliable without that possibility.

As described above, according to the present embodiment, there is no defect such as a crack inside, and it has excellent durability against substrate bending, and at the same time, it is high by using a buried mold type with a thermosetting resin. Reliability and excellent surface mountability can be realized.

(Embodiment 3) FIG. 4 is a cross-sectional view of a lead type multilayer ceramic capacitor according to Embodiment 3 of the present invention, in which 31 is a laminate, 32a, 32b, and 32c are internal electrode layers, and 33 is a ceramic. A dielectric layer, 34 is a lower external electrode, 35 is an upper external electrode, 36 is a thermosetting resin, 37 is a lead wire, and 38 is solder.

In the third embodiment, as in the first and second embodiments, a capacitance acquisition layer formed by alternately stacking ceramic dielectric layers 33 and internal electrode layers 32a, 32b, 32c. A ceramic dielectric layer 33 is laminated as an ineffective layer above and below an effective layer to be a laminated body, thereby forming a laminated body 31.
A lower external electrode 34 electrically connected to the external electrodes b and 32c is provided, and an upper external electrode 35 is provided thereon.
In addition, the ends of the internal electrode layers 32a, 32b, and 32c that are not connected to the lower external electrodes 34 are provided with the gap 1 shown in FIG.
6 are formed.

In the lead-type multilayer ceramic capacitor according to the third embodiment, the lead wire 37 is connected to the upper layer external electrode 35 by solder 38, and further includes the multilayer body 31, the lower layer external electrode 34, and the upper layer external electrode 35. The chip-type multilayer ceramic capacitor and a part of the lead wire 37 are embedded in a thermosetting resin 36 as an exterior material.

That is, conductive lead wires 37 are connected from both ends of the laminated body 31 embedded in the thermosetting resin 36 as an exterior material.
Are drawn out and can be soldered to the circuit board via the lead wire 37.

The method of manufacturing a lead-type multilayer ceramic capacitor according to the third embodiment is the same as that of the first embodiment except that lead wires are provided to both end surfaces of the chip-type multilayer ceramic capacitor element manufactured by the same procedure as in the first embodiment. The element body was completed by coating with an epoxy-based thermosetting resin.

Next, the lead-type multilayer ceramic capacitor was embedded in a resin and polished, and the cross section was observed with a metallographic microscope. As a result, as in the first embodiment, as shown in FIG. A gap 16 having a size of about several μm was formed at an end of the internal electrode layers 32 a and 32 b which was not connected to the lower external electrode 34. Further, the ceramic dielectric layer 33 and the internal electrode layers 32a, 32b, 32c
And the vicinity thereof and the internal electrode layers 32a, 32b, 3
There was no defect such as a crack near the void formed at the end of 2c, and it had a good internal structure.

In the lead-type multilayer ceramic capacitor of the third embodiment, internal distortion which may be caused by the inverse piezoelectric effect is reduced, and there is no fear of creeping discharge due to abnormal voltage. Is soldered, so that no mechanical stress such as bending resistance of the substrate is applied, which is superior in circuit design.

[0048]

As described above, according to the present invention, a laminated structure formed by providing an ineffective layer composed of a ceramic dielectric layer above and below an effective layer composed of a ceramic dielectric layer and an internal electrode layer. In the ceramic capacitor element, since a gap is formed at an end of the internal electrode layer, stress induced by incompatibility between the ceramic dielectric layer and the internal electrode layer and distortion due to an inverse piezoelectric effect are alleviated. It is possible to provide a multilayer ceramic capacitor having excellent reliability such as performance and having stable electric characteristics and high performance quality.

[Brief description of the drawings]

FIG. 1 is a sectional view of a multilayer ceramic capacitor according to a first embodiment of the present invention.

FIG. 2 is a partially enlarged view showing the multilayer ceramic capacitor according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a molded multilayer ceramic capacitor according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a lead-type multilayer ceramic capacitor according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a conventional multilayer ceramic capacitor.

FIG. 6 is a partially enlarged view showing a conventional multilayer ceramic capacitor.

[Explanation of symbols]

11, 21, 31 laminated body 12a to 12c, 22a to 22c, 32a to 32c internal electrode layer 13, 23, 33 ceramic dielectric layer 14, 24, 34 lower external electrode 15, 25, 35 upper external electrode 16 gap 26, 36 Thermosetting resin 27 Terminal 37 Lead wire 38 Solder

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masuhiro Yamamoto 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5E001 AB03 AC03 AC06 AD00 AF01 AF06 AG00 AG01

Claims (5)

[Claims] 1. A base having an effective layer having an internal electrode layer provided between a first plurality of ceramic dielectric layers and an ineffective layer comprising a second plurality of ceramic dielectric layers, and both ends of the base. And a pair of external electrodes electrically connected to the internal electrode layer, the chip-type multilayer ceramic capacitor being provided between the first plurality of ceramic dielectric layers. A multilayer ceramic capacitor, wherein a void is formed at an end of the internal electrode layer that is not connected to the external electrode, among the internal electrode layers. 2. A base having an effective layer having an internal electrode layer provided between a first plurality of ceramic dielectric layers and an ineffective layer comprising a second plurality of ceramic dielectric layers, and both ends of the base. And a pair of external electrodes electrically connected to the internal electrode layer and terminals respectively connected to the external electrodes, wherein the base and the external electrodes are embedded with a resin. A capacitor, wherein, among the internal electrode layers provided between the first plurality of ceramic dielectric layers, a void is formed at an end of the internal electrode layer that is not connected to the external electrode. Characteristic multilayer ceramic capacitor. 3. A base having an effective layer having an internal electrode layer provided between a first plurality of ceramic dielectric layers and an ineffective layer comprising a second plurality of ceramic dielectric layers, and both ends of the base. A lead-type laminate including a pair of external electrodes electrically connected to the internal electrode layer and lead wires respectively connected to the external electrodes, wherein the base and the external electrodes are covered with a resin. A ceramic capacitor, wherein a void is formed at an end of the internal electrode layer that is not connected to the external electrode among internal electrode layers provided between the first plurality of ceramic dielectric layers. A multilayer ceramic capacitor characterized by the following. 4. An effective layer is provided on both sides of said effective layer so as to sandwich said effective layer.
3. The multilayer ceramic capacitor according to item 1. 5. A chip type comprising: a base provided with an internal electrode layer between ceramic dielectric layers; and a pair of external electrodes provided at both ends of the base and electrically connected to the internal electrode layer. A multilayer ceramic capacitor, wherein a void is formed at an end of the internal electrode layer on a side not connected to an external electrode.