CN115988350A - A CMOS Image Sensing, Memory and Computing Integrated Circuit Integrated with Sampling and Computing - Google Patents

A CMOS Image Sensing, Memory and Computing Integrated Circuit Integrated with Sampling and Computing Download PDF

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CN115988350A
CN115988350A CN202211288849.4A CN202211288849A CN115988350A CN 115988350 A CN115988350 A CN 115988350A CN 202211288849 A CN202211288849 A CN 202211288849A CN 115988350 A CN115988350 A CN 115988350A
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CN115988350B (en
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胡绍刚
刘子超
黄家�
李浩玮
乔冠超
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University of Electronic Science and Technology of China
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Abstract

本发明公开了一种整合采样计算的CMOS图像感存算一体电路,属于集成电路技术领域,包括光电感存算模块、运算模块、采样模块;所述的光电感存算模块,将光强信号转换为电信号并与存储的权值进行乘法运算,以电流输出;所述运算模块,耦接到所述光电感存算模块的输出端,能够实现电压输出,并用于对输入实现求和;所述采样模块,耦接到所述运算模块的输出端,用于对电压波形进行固定周期的采样和减法运算,得到加权求和的光强信息。本发明提供了一种具有高精度光学传感,以及自动采样处理的权值运算电路,可以在单片上完成传感、存储、计算功能。该电路结构可以应用于图像识别和图像处理等领域,具有体积小、速度快、集成度高的特点。

Figure 202211288849

The invention discloses a CMOS image sensing, storage and calculation integrated circuit integrating sampling and calculation, which belongs to the technical field of integrated circuits, and includes a photoelectric storage and calculation module, an operation module, and a sampling module; the photoelectric storage and calculation module converts light intensity signals into Converting it into an electrical signal and multiplying it with the stored weight value, and outputting it as a current; the operation module, coupled to the output terminal of the photoelectric storage and calculation module, can realize voltage output, and is used for summing the input; The sampling module is coupled to the output terminal of the operation module, and is used for performing fixed-period sampling and subtraction operations on the voltage waveform to obtain weighted and summed light intensity information. The invention provides a weight calculation circuit with high-precision optical sensing and automatic sampling processing, which can complete sensing, storage and calculation functions on a single chip. The circuit structure can be applied to fields such as image recognition and image processing, and has the characteristics of small size, high speed and high integration.

Figure 202211288849

Description

一种整合采样计算的CMOS图像感存算一体电路A CMOS Image Sensing, Memory and Computing Integrated Circuit Integrated with Sampling and Computing

技术领域technical field

本发明属于集成电路技术领域,具体是涉及一种整合采样计算的CMOS图像感存算一体电路。The invention belongs to the technical field of integrated circuits, and in particular relates to a CMOS image sensing, storage and calculation integrated circuit integrating sampling and calculation.

背景技术Background technique

近年来,随着人工神经网络技术的高速发展,基于神经网络的图像识别也逐渐成为成熟的技术。图像识别在当今具有非常广泛的应用,如人脸识别、卫星遥感乃至军事侦察等等。神经网络的实质是一系列结构化的可训练参数,通过对输入张量进行加权求和等运算输出最终结果,从而实现对输入张量的处理,或在此过程中提取数据特征以进行分类、识别等操作。广义上来说,计算机进行的图像识别可分为三个步骤:传感器将光强信号转换为电信号以实现图像采集;计算机软件将采集到的图像信息进行存储和数据处理;人工神经网络将处理后的数据进行前向运算,输出图像信息的某些特征值以实现图像的最终识别。In recent years, with the rapid development of artificial neural network technology, image recognition based on neural network has gradually become a mature technology. Image recognition has a very wide range of applications today, such as face recognition, satellite remote sensing, and even military reconnaissance. The essence of the neural network is a series of structured trainable parameters, and the final result is output by performing operations such as weighted summation on the input tensor, thereby realizing the processing of the input tensor, or extracting data features for classification, recognition etc. In a broad sense, image recognition by computer can be divided into three steps: the sensor converts the light intensity signal into an electrical signal to realize image acquisition; the computer software stores and processes the collected image information; the artificial neural network converts the processed Forward calculation of the data, and output some feature values of the image information to realize the final recognition of the image.

由于使用通用计算机进行神经网络计算需要大量的运行资源,而且使用传统架构的计算机中CPU和内存的速度不匹配也极大限制了运行的速度,一种解决途径是搭建专用的片上系统,从而能高效地完成特定类型的神经网络计算。感存算一体电路,指的是在结构上将图像采集、权值存储和神经网络计算紧密结合的一类电路。Since the use of general-purpose computers for neural network calculations requires a large amount of operating resources, and the mismatch between CPU and memory speeds in computers with traditional architectures also greatly limits the speed of operation, one solution is to build a dedicated system-on-chip. Efficiently complete certain types of neural network computations. The sensor-memory-computing integrated circuit refers to a type of circuit that closely combines image acquisition, weight storage and neural network calculation in structure.

目前还没有一种能够使用成熟工艺完成的结合感存算一体电路与后期数据采样整理的电路,感存算结果的读取往往依赖复杂的片外读出电路。At present, there is no circuit that can use mature technology to combine the integrated circuit of sense-memory-computing and post-data sampling and sorting. The reading of sense-memory-calculation results often relies on complex off-chip readout circuits.

发明内容Contents of the invention

为了解决现有技术的问题,本发明实施例提供了一种整合采样计算的CMOS感存算一体电路结构,该电路可在片上自动实现传感、存储、计算和数据采样整理。In order to solve the problems in the prior art, the embodiment of the present invention provides a CMOS sensor-storage-computing integrated circuit structure integrating sampling and computing, which can automatically realize sensing, storage, computing and data sampling and sorting on the chip.

本发明的技术方案是:Technical scheme of the present invention is:

一种整合采样计算的CMOS图像感存算一体电路,包括光电感存算模块、运算模块与采样模块;所述光电感存算模块是由n*n个光电感存单元构成的矩阵,每个光电感存单元连接两条列线和两条行线,其中两条列线分别为每一列光电感存单元的存储权值提供使能信号和复位信号,两条行线用于为每一行光电感存单元写入2位权值;所述运算模块包括n个运算单元,每个运算单元的输入为每一列所有光电感存算模块输出的正向电流汇集点和负向电流汇集点;所述采样模块包括n个采样单元,每列采样单元的输入为每列运算单元的输出;A CMOS image sensing, storage and calculation integrated circuit integrating sampling and calculation, including a photoelectric storage and calculation module, an operation module and a sampling module; the photoelectric storage and calculation module is a matrix composed of n*n photoelectric storage units, each The photoelectric storage unit is connected to two column lines and two row lines, wherein the two column lines provide enable signals and reset signals for the storage weights of each column of photoelectric storage units, and the two row lines are used for each row of photoelectric storage units. The sensing unit writes 2 weights; the arithmetic module includes n arithmetic units, and the input of each arithmetic unit is the positive current collection point and the negative current collection point output by all photoelectric storage and calculation modules of each column; The sampling module includes n sampling units, and the input of each column of sampling units is the output of each column of computing units;

所述光电感存单元包括第一MOS管、第二MOS管、第三MOS管、第四MOS管、光电二极管、第一SRAM、第二SRAM;其中,第一MOS管的栅极接提供复位信号的列线,其漏极接电源,其源极接光电二极管的阴极和第二MOS管的栅极;光电二极管的阳极接地;第二MOS管的漏极接电源,其源极接第三MOS管的漏极和第四MOS管的漏极;第三MOS管的栅极接第一SRAM的输出,第三MOS管的源极输出正向电流;第四MOS管的栅极接第二SRAM的输出,第四MOS管的源极输出负向电流;第一SRAM和第二SRAM分别在使能信号控制下由两条行线写入权值;The photoelectric storage unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a photodiode, a first SRAM, and a second SRAM; wherein, the gate of the first MOS transistor is connected to provide reset The column line of the signal, its drain is connected to the power supply, its source is connected to the cathode of the photodiode and the grid of the second MOS tube; the anode of the photodiode is grounded; the drain of the second MOS tube is connected to the power supply, and its source is connected to the third The drain of the MOS transistor and the drain of the fourth MOS transistor; the gate of the third MOS transistor is connected to the output of the first SRAM, and the source of the third MOS transistor outputs a forward current; the gate of the fourth MOS transistor is connected to the second The output of the SRAM, the source of the fourth MOS transistor outputs a negative current; the first SRAM and the second SRAM are respectively written into the weight by two row lines under the control of the enable signal;

所述运算单元用于将输入的正向电流和负向电流转换为电压,最终执行减法运算;The operation unit is used to convert the input positive current and negative current into voltage, and finally perform the subtraction operation;

所述采样单元用于在输入端导通时采样输入电压并放大其驱动能力,在输入端断开时电荷保持在电容极板上,输出恒定电压。The sampling unit is used to sample the input voltage and amplify its driving capability when the input terminal is turned on, and to keep the charge on the capacitor plate when the input terminal is turned off, and output a constant voltage.

进一步的,所述运算单元包括第一运算放大器、第二运算放大器、第三运算放大器、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻,其中,第一运算放大器的负向输入端接正向电流汇集点Ips,其正向输入端接地,其输出端通过第一电阻连接其负向输入端;第二运算放大器的负向输入端接反向电流汇集点Ins,其正向输入端接地,其输出端通过第二电阻接其负向输入端;第三运算放大器的正向输入端通过第三电阻后接第一运算放大器的输出端,第三运算放大器的负向输入端通过第四电阻后接第二运算放大器的输出端,第三运算放大器的正向输入端还通过第五电阻后接地,第三运算放大器的输出端通过第六电阻后接其负向输入端;第三运算放大器的输出端为运算单元的输出端。Further, the operation unit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor, wherein the first The negative input terminal of an operational amplifier is connected to the positive current sink point Ips, its positive input terminal is grounded, and its output terminal is connected to its negative input terminal through the first resistor; the negative input terminal of the second operational amplifier is connected to the reverse current Converging point Ins, its positive input terminal is grounded, its output terminal is connected to its negative input terminal through the second resistor; the positive input terminal of the third operational amplifier is connected to the output terminal of the first operational amplifier after the third resistor, and the third operational amplifier The negative input terminal of the operational amplifier is connected to the output terminal of the second operational amplifier after passing through the fourth resistor, the positive input terminal of the third operational amplifier is grounded after passing through the fifth resistor, and the output terminal of the third operational amplifier is connected after passing through the sixth resistor. connected to its negative input; the output of the third operational amplifier is the output of the operational unit.

进一步的,所述采样单元包括第一开关、第二开关、第三开关、第四运算放大器、第五运算放大器、第六运算放大器、第七运算放大器、第一电容、第二电容、第三电容、第七电阻、第八电阻、第九电阻、第十电阻,其中,第一开关的一端接运算单元的输出端,另一端接第一电容的一端和第四运算放大器的正向输入端,第一电容的另一端接地;第四运算放大器的负向输入端接其输出端;第二开关的一端接第四运算放大器的输出端,第二开关的另一端接第二电容的一端和第五运算放大器的正向输入端,第二电容的另一端接地;第五运算放大器的负向输入端接其输出端;第三开关的一端接运算单元的输出端,另一端接第六运算放大器的正向输入端和第三电容的一端,第三电容的另一端接地;第六运算放大器的负向输入端接其输出端;第七运算放大器的正向输入端通过第七电阻后接第五运算放大器的输出端,第七运算放大器的负向输入端通过第八电阻后接第六运算放大器的输出端,第七运算放大器的正向输入端还通过第九电阻后接地,第七运算放大器的负向输入端还通过第十电阻后接其输出端;第七运算放大器的输出端为采样单元输出端。Further, the sampling unit includes a first switch, a second switch, a third switch, a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a seventh operational amplifier, a first capacitor, a second capacitor, a third capacitor, the seventh resistor, the eighth resistor, the ninth resistor, and the tenth resistor, wherein one end of the first switch is connected to the output end of the arithmetic unit, and the other end is connected to one end of the first capacitor and the positive input end of the fourth operational amplifier , the other end of the first capacitor is grounded; the negative input end of the fourth operational amplifier is connected to its output end; one end of the second switch is connected to the output end of the fourth operational amplifier, the other end of the second switch is connected to one end of the second capacitor and The positive input terminal of the fifth operational amplifier, the other end of the second capacitor is grounded; the negative input terminal of the fifth operational amplifier is connected to its output terminal; one terminal of the third switch is connected to the output terminal of the computing unit, and the other terminal is connected to the sixth operational amplifier The positive input terminal of the amplifier and one end of the third capacitor, the other end of the third capacitor is grounded; the negative input terminal of the sixth operational amplifier is connected to its output terminal; the positive input terminal of the seventh operational amplifier is connected after the seventh resistor The output terminal of the fifth operational amplifier, the negative input terminal of the seventh operational amplifier is connected to the output terminal of the sixth operational amplifier after passing through the eighth resistor, the positive input terminal of the seventh operational amplifier is grounded after passing through the ninth resistor, and the seventh The negative input terminal of the operational amplifier is also connected to its output terminal through the tenth resistor; the output terminal of the seventh operational amplifier is the output terminal of the sampling unit.

本发明的有益效果是:本发明提供了一种具有高精度光学传感,以及自动采样处理的权值运算电路,可以在单片上完成传感、存储、计算功能。该电路结构可以应用于图像识别和图像处理等领域,具有体积小、速度快、集成度高的特点。The beneficial effects of the present invention are: the present invention provides a weight calculation circuit with high-precision optical sensing and automatic sampling processing, which can complete sensing, storage and calculation functions on a single chip. The circuit structure can be applied to fields such as image recognition and image processing, and has the characteristics of small size, high speed and high integration.

附图说明Description of drawings

图1为本发明的逻辑结构示意图。Fig. 1 is a schematic diagram of the logical structure of the present invention.

图2是光电二极管的光照强度-反向电流大小的关系示意图。FIG. 2 is a schematic diagram of the relationship between the light intensity of the photodiode and the magnitude of the reverse current.

图3是CMOS感存算单元结构示意图。Fig. 3 is a schematic diagram of the structure of a CMOS sensing memory computing unit.

图4是所述CMOS感存算单元的各工作模式下的节点波形示意图。Fig. 4 is a schematic diagram of node waveforms in each working mode of the CMOS sensing memory computing unit.

图5是所述CMOS感存算单元在不同光照强度下的输出电流的波形示意图。FIG. 5 is a schematic diagram of the waveforms of the output current of the CMOS sensing, memory and computing unit under different light intensities.

图6是一种整合采样计算的CMOS图像感存算一体电路示意图。FIG. 6 is a schematic diagram of a CMOS image sensing, storage and calculation integrated circuit integrating sampling and calculation.

图7是图5中的运算模块结构示意图。FIG. 7 is a schematic structural diagram of the computing module in FIG. 5 .

图8是图5中的采样模块结构示意图。FIG. 8 is a schematic structural diagram of the sampling module in FIG. 5 .

图9是所述采样模块中时钟信号的电压波形示意图。Fig. 9 is a schematic diagram of the voltage waveform of the clock signal in the sampling module.

图10是所述采样模块输入与输出的电压波形示意图。Fig. 10 is a schematic diagram of the input and output voltage waveforms of the sampling module.

具体实施方式Detailed ways

下面结合附图,详细描述本发明的技术方案:Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

如图1所示,为本发明的总体结构示意图,包括光电感存算模块、运算模块与采样模块,光电感存算模块是由n*n个光电感存单元构成的矩阵,每个光电感存单元连接两条列线和两条行线,其中两条列线分别为每一列光电感存单元的存储权值提供使能信号和复位信号,两条行线用于为每一行光电感存单元写入2位权值;运算模块包括n个运算单元,每个运算单元的输入为两条列线的信号;采样模块包括n个采样单元,每列采样单元的输入为每列运算单元的输出。As shown in Figure 1, it is a schematic diagram of the overall structure of the present invention, including a photoelectric storage and calculation module, an operation module and a sampling module. The photoelectric storage and calculation module is a matrix composed of n*n photoelectric storage units. The storage unit is connected to two column lines and two row lines, wherein the two column lines provide enable signals and reset signals for the storage weights of each column of photoelectric storage units, and the two row lines are used for each row of photoelectric storage units. The unit writes 2-bit weights; the arithmetic module includes n arithmetic units, and the input of each arithmetic unit is the signal of two column lines; the sampling module includes n sampling units, and the input of each column of sampling units is the signal of each column of arithmetic units output.

如图2所示,是光电二极管的光照强度-反向电流大小的关系示意图。当光电二极管处于反向偏置时,入射光子进入PN结并激发电子-空穴对,产生的载流子在反向电压的影响下进行漂移运动,形成光电流,其反向电流大小受入射光强度的控制。在反向偏置电压一定的情况下,入射光的强度增加导致二极管电流的上升,在入射光强度的一定范围内两者呈线性关系。据此,光电二极管可作为将光强信号线性转换为电流信号的传感元件。As shown in Figure 2, it is a schematic diagram of the relationship between the light intensity of the photodiode and the size of the reverse current. When the photodiode is in reverse bias, the incident photons enter the PN junction and excite the electron-hole pairs, and the generated carriers drift under the influence of the reverse voltage to form a photocurrent, and the magnitude of the reverse current is affected by the incident light Intensity control. In the case of a certain reverse bias voltage, the increase of the intensity of the incident light leads to the rise of the diode current, and the two have a linear relationship within a certain range of the intensity of the incident light. Accordingly, the photodiode can be used as a sensing element that linearly converts the light intensity signal into a current signal.

如图3所示,是CMOS感存算单元结构示意图。当复位信号Vrst为高电平时,复位MOS管1被打开并对光电二极管7内的寄生电容充电,直至其接近电源电压Vdd。充电完毕后,通过置低Vrst使复位管1关断,此时感存算单元曝光在一定的光照强度下,从而流经光电二极管7的电流为光电流,该电流与入射光强度成正比,并使光电二极管内部寄生电容放电,导致二极管两端电压降低。由于跟随管2的作用,其源端的电压变化跟随二极管两端的电压,以信号V1(t)表示。图中5,6为SRAM单元,通过外部字线和位线提前在其中写入并存储1位数字值,当存储的bit为10时代表权值为1,01代表权值为-1,00代表权值为0,同时以高/低电平形式持续输出电压。单元5,6中存储的值B5,B6分别控制计算管3,4的通断,以SRAM单元5和计算管3为例,若5中存储的值B5为0,则单元5输出低电平,使3关断,没有电流流过;若B5为1即输出电源电压,则3处于深线性区,可以等效为一电阻Ron,由于3和4的源端被其他模块钳位至地电平,流经3的电流表达为V1(t)/Ron。综合两种情况分析,流经3的电流Ip1(t)是模拟量v1(t)/Ron与数字量B5的乘积,类似地,流经4的电流In1(t)是模拟量V1(t)/Ron与数字量B6的乘积。因此两管电流之差I1(t)=Ip1(t)-In1(t)=(B5-B6)·V1(t)/Ron,相当于以V1(t)/Ron为输入数据,(B5-B6)为权值的乘法操作。这里减法的实现将由后续的运算模块完成。As shown in FIG. 3 , it is a schematic diagram of the structure of a CMOS sensing memory computing unit. When the reset signal Vrst is at a high level, the reset MOS transistor 1 is turned on and charges the parasitic capacitance in the photodiode 7 until it is close to the power supply voltage Vdd. After the charging is completed, the reset tube 1 is turned off by setting Vrst low. At this time, the sensor-memory-computing unit is exposed to a certain light intensity, so that the current flowing through the photodiode 7 is a photocurrent, which is proportional to the incident light intensity. And discharge the internal parasitic capacitance of the photodiode, causing the voltage across the diode to drop. Due to the function of the follower tube 2, the voltage change at its source terminal follows the voltage at both ends of the diode, represented by the signal V1(t). 5 and 6 in the figure are SRAM cells, in which a digital value is written and stored in advance through the external word line and bit line. When the stored bit is 10, it means the weight value is 1, and 01 means the weight value is -1, 00. It means that the weight is 0, and at the same time, the output voltage is continuously output in the form of high/low level. The values B5 and B6 stored in units 5 and 6 respectively control the on-off of computing tubes 3 and 4. Taking SRAM unit 5 and computing tube 3 as an example, if the value B5 stored in 5 is 0, then unit 5 outputs a low level , so that 3 is turned off, and no current flows; if B5 is 1, that is, the output power supply voltage, then 3 is in the deep linear region, which can be equivalent to a resistance Ron, because the sources of 3 and 4 are clamped to the ground by other modules Flat, the current flowing through 3 is expressed as V1(t)/Ron. Based on the analysis of the two situations, the current Ip1(t) flowing through 3 is the product of the analog quantity v1(t)/Ron and the digital quantity B5, similarly, the current In1(t) flowing through 4 is the analog quantity V1(t) The product of /Ron and digital quantity B6. Therefore, the difference between the currents of the two tubes I1(t)=Ip1(t)-In1(t)=(B5-B6) V1(t)/Ron, which is equivalent to taking V1(t)/Ron as the input data, (B5- B6) is the multiplication operation of the weight. The realization of the subtraction here will be completed by the subsequent operation module.

如图4所示,是所述CMOS感存算单元在权值存储和感存算工作中的各节点波形示意图。在权值存储操作中,通过置高WL将BL上的目标权值输入SRAM,随后置低WL使权值锁存在SRAM中不受BL的影响,该权值以逻辑电平的形式从SRAM的输出端持续输出,控制计算管的栅极实现乘法功能。在感存算工作中,被存入权值1的SRAM控制的计算管导通电流随Vrst以一定的工作周期变化,被存入权值0的SRAM控制的计算管导通电流始终为0.图中示意了B5=1,B6=0时Ips和Ins的变化,其中Ips跟随光电二极管两端电压的变化,而Ins=0.As shown in FIG. 4 , it is a schematic diagram of the waveforms of each node of the CMOS sensing memory computing unit in the weight storage and sensing memory computing work. In the weight storage operation, the target weight on BL is input into SRAM by setting WL high, and then WL is set low so that the weight is locked in SRAM without being affected by BL. The output end continues to output, and the grid of the calculation tube is controlled to realize the multiplication function. In the sense-memory operation, the conduction current of the calculation tube controlled by the SRAM with a weight value of 1 changes with a certain duty cycle with Vrst, and the conduction current of the calculation tube controlled by an SRAM with a weight value of 0 is always 0. The figure shows the change of Ips and Ins when B5=1 and B6=0, where Ips follows the change of the voltage across the photodiode, and Ins=0.

如图5所示,是所述CMOS感存算单元在不同光照强度下的输出电流的波形示意图。此处B5-B6=1,因此电流为正,单元的工作周期为t0,分为长度为t1的充电复位阶段和(t0-t1)的放电工作阶段。根据图1中的关系,可以用放电的平均速度表示该周期中的光照强度,即I(t1+n·t0)-I(t0+n·t0)/t0=Cpd·Iin(n),其中Cpd为一由光电二极管工艺决定的常数,Iin(n)为第n个周期中探测到的光照强度,这一步计算将由后续的采样模块实现。图4表示了光照强度随时间逐渐增加时的输出电流曲线,可见每个周期的放电阶段,曲线平均斜率都比上一周期更大。权值B5-B6的改变将使输出电流曲线沿纵轴等比例放缩,若B5-B6=0,该曲线将恒等于0;若B5-B6=-1,曲线上每个点的电流将取负值,经后续采样模块计算后将得到相反结果。多个CMOS感存算单元的输出端连接可使输出电流的范围进一步扩大,用于表示多个数字权值与由光强信号转换的模拟电流乘积的加和运算结果。As shown in FIG. 5 , it is a schematic diagram of the waveform of the output current of the CMOS sensing memory and computing unit under different light intensities. Here B5-B6=1, so the current is positive, and the working cycle of the unit is t0, which is divided into a charging reset phase with a length of t1 and a discharging working phase of (t0-t1). According to the relationship in Figure 1, the average speed of discharge can be used to represent the light intensity in this period, that is, I(t1+n·t0)-I(t0+n·t0)/t0=Cpd·Iin(n), where Cpd is a constant determined by the photodiode process, Iin(n) is the light intensity detected in the nth cycle, and this step of calculation will be realized by the subsequent sampling module. Figure 4 shows the output current curve when the light intensity gradually increases with time. It can be seen that the average slope of the curve is larger than that of the previous cycle in the discharge phase of each cycle. The change of the weight value B5-B6 will make the output current curve scale proportionally along the vertical axis. If B5-B6=0, the curve will always be equal to 0; if B5-B6=-1, the current at each point on the curve will be Taking a negative value will result in the opposite result after being calculated by the subsequent sampling module. The output terminal connection of a plurality of CMOS sensing storage and calculation units can further expand the range of the output current, which is used to represent the summation result of the multiplication of a plurality of digital weights and the analog current converted from the light intensity signal.

如图6所示,是一种整合采样计算的CMOS图像感存算一体电路示意图。在n*n规模的电路中,同一列的所有感存算单元受同一复位信号控制工作,并将所有Ip和In分别由运算模块进行加和操作,然后将两者相减,完成加权求和的操作,最后通过采样模块计算加权求和后的光照强度信号。除电源线以外,在n*n规模的电路中共有n条列线WL控制各列存储权值的使能、2n条行线BL用于为所有感存算单元写入2位权值,以及n条列线Vrst提供复位信号。以n条列线正加和电流Ips和n条负加和电流Ins,后接n个运算模块和n个采样模块,输出相互独立的n个加权求和后的光照强度信号。当光照强度变化的频率小于感存算单元的工作频率时,CMOS图像感存算一体电路可以准确接收光强信号并执行按列的加权求和操作。As shown in FIG. 6 , it is a schematic diagram of a CMOS image sensing, storage and calculation integrated circuit integrating sampling and calculation. In an n*n-scale circuit, all sense-memory-calculation units in the same column are controlled by the same reset signal, and all Ip and In are summed by the arithmetic module, and then the two are subtracted to complete the weighted summation operation, and finally calculate the weighted and summed light intensity signal through the sampling module. In addition to the power line, there are n column lines WL in the circuit of n*n scale to control the enablement of the storage weights of each column, and 2n row lines BL are used to write 2-bit weights for all sense memory calculation units, and The n column lines Vrst provide reset signals. The positive summing current Ips of n column lines and the negative summing current Ins of n lines are followed by n computing modules and n sampling modules to output n mutually independent weighted and summed light intensity signals. When the frequency of light intensity changes is less than the operating frequency of the sensor-memory-computation unit, the CMOS image sensor-memory-computation integrated circuit can accurately receive the light intensity signal and perform a column-wise weighted summation operation.

如图7所示,所述运算电路模块由运算放大器8、9、10,以及负载电阻11、12,输入电阻13、14、16,反馈电阻15构成。其作用为将列线钳位,并将列线电流转换为电压,最终执行减法运算。其中R11=R12,R13=R14=R15=R16。所有运算放大器都具有很高的增益以实现“虚短”和“虚断”,从而电流输入端Ips,Ins被钳位至GND,使前级感存算单元中的运算管得以正常工作。在运算电路模块中,所有放大器均为双电源供电,从而能正常实现列线钳位功能,并可输出负电压。运算放大器8和负载电阻11将Ips转换为Vps=Ips·R11,类似地运算放大器9和负载电阻12将Ins转换为Vns=Ins·R12,由运算放大器10和电阻R13、R14、R15、R16组成电压减法器,输出Vo=Vps-Vns,完成加权求和的操作。As shown in FIG. 7 , the operational circuit module is composed of operational amplifiers 8 , 9 , 10 , load resistors 11 , 12 , input resistors 13 , 14 , 16 , and feedback resistor 15 . Its function is to clamp the column line, convert the column line current into a voltage, and finally perform the subtraction operation. Wherein R11=R12, R13=R14=R15=R16. All operational amplifiers have a very high gain to achieve "virtual short" and "virtual break", so that the current input terminals Ips and Ins are clamped to GND, so that the operational tube in the pre-sensing storage unit can work normally. In the operational circuit module, all amplifiers are powered by dual power supplies, so that the column line clamping function can be normally realized and negative voltage can be output. Operational amplifier 8 and load resistor 11 convert Ips to Vps=Ips R11, similarly operational amplifier 9 and load resistor 12 convert Ins to Vns=Ins R12, composed of operational amplifier 10 and resistors R13, R14, R15, R16 The voltage subtractor outputs Vo=Vps-Vns to complete the operation of weighted summation.

如图8所示,所述采样模块由运算放大器20、21、22、23,采样开关17、18、19,采样电容24、25、26,输入电阻27、28、29,反馈电阻30构成,其中R27=R28=R29=R30。由采样电容和运算放大器结合形成的电路,在输入端导通时采样输入电压并放大其驱动能力,在输入端断开时电荷保持在电容极板上,输出电压恒定,实现采样-保持-缓冲的功能,此处采样电容较小,以使采样开关导通期间电容可以迅速充电完成,准确记录采样电压。在该列全部感存算单元的放电阶段开始时,一个脉冲使采样开关17短暂打开,从而采样电容24记录此时的Vo。在放电阶段结束时,另一个脉冲使采样开关18和19同时打开,采样电容24上的电压经运算放大器20形成的缓冲电路被复制到采样电容26上,由于工作周期恒定,此时电容26和25之间的电压差值与加权求和的光照强度成正比,经过缓冲放大器和电压减法器输出该列最终图像识别结果Vout。As shown in Figure 8, the sampling module is composed of operational amplifiers 20, 21, 22, 23, sampling switches 17, 18, 19, sampling capacitors 24, 25, 26, input resistors 27, 28, 29, and feedback resistors 30. where R27=R28=R29=R30. The circuit formed by the combination of sampling capacitor and operational amplifier samples the input voltage and amplifies its driving ability when the input terminal is turned on, and the charge is kept on the capacitor plate when the input terminal is disconnected, and the output voltage is constant, realizing sample-hold-buffering The function of the sampling capacitor here is small, so that the capacitor can be charged quickly during the conduction of the sampling switch, and the sampling voltage can be accurately recorded. At the beginning of the discharge phase of all SRAM units in the column, a pulse briefly opens the sampling switch 17, so that the sampling capacitor 24 records Vo at this time. At the end of the discharge phase, another pulse makes the sampling switches 18 and 19 open simultaneously, and the voltage on the sampling capacitor 24 is copied to the sampling capacitor 26 through the buffer circuit formed by the operational amplifier 20. Since the duty cycle is constant, the capacitor 26 and The voltage difference between 25 is proportional to the light intensity of the weighted summation, and the final image recognition result Vout of the column is output through the buffer amplifier and the voltage subtractor.

如图9所示,是所述采样模块中时钟信号的电压波形示意图。每一个模拟开关由一对NMOS和PMOS组成,需要2个时钟信号控制,所述采样模块有两个独立的开关,共需要4个时钟信号。图中Vrst为控制传感器的复位信号,用于对照各信号的时序逻辑。图中Vn1和Vp1是控制图7中开关17的时钟信号,需要在Vrst的下降沿发射脉冲以使采样开关记录放电开始时的输出电压;Vn2和Vp2是控制图7中开关18和19的时钟信号,需要在Vrst的下一个上升沿到来前发射脉冲以使采样开关记录放电结束时的输出电压,同时使放电初电压导通至电压减法器输入端,进行采样结果计算。这些时钟信号都由复位信号Vrst决定,其脉冲长度很短,从而电容采样的时间里Vo基本不变。As shown in FIG. 9 , it is a schematic diagram of the voltage waveform of the clock signal in the sampling module. Each analog switch is composed of a pair of NMOS and PMOS, and needs to be controlled by two clock signals. The sampling module has two independent switches, and needs four clock signals in total. In the figure, Vrst is the reset signal of the control sensor, which is used to compare the timing logic of each signal. Vn1 and Vp1 in the figure are the clock signals controlling the switch 17 in Figure 7, and pulses need to be emitted on the falling edge of Vrst to make the sampling switch record the output voltage at the beginning of discharge; Vn2 and Vp2 are the clocks controlling the switches 18 and 19 in Figure 7 signal, it is necessary to emit a pulse before the next rising edge of Vrst to enable the sampling switch to record the output voltage at the end of discharge, and at the same time conduct the initial discharge voltage to the input terminal of the voltage subtractor to calculate the sampling result. These clock signals are all determined by the reset signal Vrst, and the pulse length is very short, so Vo basically does not change during the sampling time of the capacitor.

如图10所示,是所述采样模块输入Vo与输出Vout的电压波形示意图。由于传输门18和19的作用,采样模块输出Vout仅在感存算阵列工作周期的末尾改变电压值,输出本周期内光强的感存算结果。这种工作模式在波形上表现为在每一个周期内Vout总是恒定输出上一个周期的感存算结果,即读出时间窗口与感存算工作周期相等。图10示意了两个完整的工作周期和第三个周期的一部分,其中第二个工作周期中的加权光强高于第一个周期,结果是Vout在第三个周期中的输出电压高于第二个周期中的输出电压。As shown in FIG. 10 , it is a schematic diagram of voltage waveforms of input Vo and output Vout of the sampling module. Due to the function of the transmission gates 18 and 19, the output Vout of the sampling module only changes the voltage value at the end of the working cycle of the sensor-memory-calculation array, and outputs the sensor-memory-calculation result of the light intensity in this period. This working mode shows in the waveform that in each cycle, Vout always outputs the result of the sense-memory-calculation of the last cycle, that is, the readout time window is equal to the duty cycle of the sense-memory-calculation. Figure 10 illustrates two complete duty cycles and a portion of a third cycle in which the weighted light intensity in the second duty cycle is higher than in the first cycle, resulting in an output voltage of Vout in the third cycle that is higher than output voltage in the second cycle.

Claims (3)

1.一种整合采样计算的CMOS图像感存算一体电路,其特征在于,包括光电感存算模块、运算模块与采样模块;所述光电感存算模块是由n*n个光电感存单元构成的矩阵,每个光电感存单元连接两条列线和两条行线,其中两条列线分别为每一列光电感存单元的存储权值提供使能信号和复位信号,两条行线用于为每一行光电感存单元写入2位权值;所述运算模块包括n个运算单元,每个运算单元的输入为每一列所有光电感存算模块输出的正向电流汇集点和负向电流汇集点;所述采样模块包括n个采样单元,每列采样单元的输入为每列运算单元的输出;1. A CMOS image sense storage and calculation integrated circuit integrating sampling and calculation is characterized in that it includes a photoelectric storage and calculation module, an operation module and a sampling module; the photoelectric storage and calculation module is composed of n*n photoelectric storage units Each photoelectric storage unit is connected to two column lines and two row lines, and the two column lines respectively provide the enable signal and reset signal for the storage weight of each column photoelectric storage unit, and the two row lines It is used to write a 2-bit weight value for each row of photoelectric storage units; the operation module includes n operation units, and the input of each operation unit is the positive current sink point and negative current output of all photoelectric storage and calculation modules in each column. To the current collection point; the sampling module includes n sampling units, and the input of each column of sampling units is the output of each column of computing units; 所述光电感存单元包括第一MOS管、第二MOS管、第三MOS管、第四MOS管、光电二极管、第一SRAM、第二SRAM;其中,第一MOS管的栅极接提供复位信号的列线,其漏极接电源,其源极接光电二极管的阴极和第二MOS管的栅极;光电二极管的阳极接地;第二MOS管的漏极接电源,其源极接第三MOS管的漏极和第四MOS管的漏极;第三MOS管的栅极接第一SRAM的输出,第三MOS管的源极输出正向电流;第四MOS管的栅极接第二SRAM的输出,第四MOS管的源极输出负向电流;第一SRAM和第二SRAM分别在使能信号控制下由两条行线写入权值;The photoelectric storage unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a photodiode, a first SRAM, and a second SRAM; wherein, the gate of the first MOS transistor is connected to provide reset The column line of the signal, its drain is connected to the power supply, its source is connected to the cathode of the photodiode and the grid of the second MOS tube; the anode of the photodiode is grounded; the drain of the second MOS tube is connected to the power supply, and its source is connected to the third The drain of the MOS transistor and the drain of the fourth MOS transistor; the gate of the third MOS transistor is connected to the output of the first SRAM, and the source of the third MOS transistor outputs a forward current; the gate of the fourth MOS transistor is connected to the second The output of the SRAM, the source of the fourth MOS transistor outputs a negative current; the first SRAM and the second SRAM are respectively written into the weight by two row lines under the control of the enable signal; 所述运算单元用于将输入的正向电流和负向电流转换为电压,最终执行减法运算;The operation unit is used to convert the input positive current and negative current into voltage, and finally perform the subtraction operation; 所述采样单元用于在输入端导通时采样输入电压并放大其驱动能力,在输入端断开时电荷保持在电容极板上,输出恒定电压。The sampling unit is used to sample the input voltage and amplify its driving capability when the input terminal is turned on, and to keep the charge on the capacitor plate when the input terminal is turned off, and output a constant voltage. 2.根据权利要求1所述的一种整合采样计算的CMOS图像感存算一体电路,其特征在于,所述运算单元包括第一运算放大器、第二运算放大器、第三运算放大器、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻,其中,第一运算放大器的负向输入端接正向电流汇集点Ips,其正向输入端接地,其输出端通过第一电阻连接其负向输入端;第二运算放大器的负向输入端接反向电流汇集点Ins,其正向输入端接地,其输出端通过第二电阻接其负向输入端;第三运算放大器的正向输入端通过第三电阻后接第一运算放大器的输出端,第三运算放大器的负向输入端通过第四电阻后接第二运算放大器的输出端,第三运算放大器的正向输入端还通过第五电阻后接地,第三运算放大器的输出端通过第六电阻后接其负向输入端;第三运算放大器的输出端为运算单元的输出端。2. A kind of integrated sampling and computing integrated circuit of CMOS image sensing, storage and computing according to claim 1, characterized in that, said computing unit comprises a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor , the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor, wherein the negative input terminal of the first operational amplifier is connected to the positive current sink point Ips, its positive input terminal is grounded, and its output terminal Connect its negative input terminal through the first resistor; the negative input terminal of the second operational amplifier is connected to the reverse current sink point Ins, its positive input terminal is grounded, and its output terminal is connected to its negative input terminal through the second resistor; The positive input terminal of the three operational amplifiers is connected to the output terminal of the first operational amplifier after the third resistor, and the negative input terminal of the third operational amplifier is connected to the output terminal of the second operational amplifier after the fourth resistor, and the output terminal of the third operational amplifier The positive input terminal is grounded after passing through the fifth resistor, and the output terminal of the third operational amplifier is connected with the negative input terminal after passing through the sixth resistor; the output terminal of the third operational amplifier is the output terminal of the operation unit. 3.根据权利要求2所述的一种整合采样计算的CMOS图像感存算一体电路,其特征在于,所述采样单元包括第一开关、第二开关、第三开关、第四运算放大器、第五运算放大器、第六运算放大器、第七运算放大器、第一电容、第二电容、第三电容、第七电阻、第八电阻、第九电阻、第十电阻,其中,第一开关的一端接运算单元的输出端,另一端接第一电容的一端和第四运算放大器的正向输入端,第一电容的另一端接地;第四运算放大器的负向输入端接其输出端;第二开关的一端接第四运算放大器的输出端,第二开关的另一端接第二电容的一端和第五运算放大器的正向输入端,第二电容的另一端接地;第五运算放大器的负向输入端接其输出端;第三开关的一端接运算单元的输出端,另一端接第六运算放大器的正向输入端和第三电容的一端,第三电容的另一端接地;第六运算放大器的负向输入端接其输出端;第七运算放大器的正向输入端通过第七电阻后接第五运算放大器的输出端,第七运算放大器的负向输入端通过第八电阻后接第六运算放大器的输出端,第七运算放大器的正向输入端还通过第九电阻后接地,第七运算放大器的负向输入端还通过第十电阻后接其输出端;第七运算放大器的输出端为采样单元输出端。3. A kind of integrated sampling and computing integrated circuit of CMOS image sensing, storage and computing according to claim 2, characterized in that the sampling unit comprises a first switch, a second switch, a third switch, a fourth operational amplifier, a first Five operational amplifiers, sixth operational amplifiers, seventh operational amplifiers, first capacitors, second capacitors, third capacitors, seventh resistors, eighth resistors, ninth resistors, and tenth resistors, wherein one end of the first switch is connected to The output end of the operational unit, the other end is connected to one end of the first capacitor and the positive input end of the fourth operational amplifier, and the other end of the first capacitor is grounded; the negative input end of the fourth operational amplifier is connected to its output end; the second switch One end of the second switch is connected to the output end of the fourth operational amplifier, the other end of the second switch is connected to one end of the second capacitor and the positive input end of the fifth operational amplifier, and the other end of the second capacitor is grounded; the negative input of the fifth operational amplifier The end is connected to its output end; one end of the third switch is connected to the output end of the computing unit, the other end is connected to the positive input end of the sixth operational amplifier and one end of the third capacitor, and the other end of the third capacitor is grounded; the sixth operational amplifier The negative input terminal is connected to its output terminal; the positive input terminal of the seventh operational amplifier is connected to the output terminal of the fifth operational amplifier through the seventh resistor, and the negative input terminal of the seventh operational amplifier is connected to the sixth operational amplifier through the eighth resistor The output terminal of the amplifier, the positive input terminal of the seventh operational amplifier is also grounded after the ninth resistor, and the negative input terminal of the seventh operational amplifier is also connected to its output terminal after the tenth resistor; the output terminal of the seventh operational amplifier is Sampling unit output.
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