CN115988350A - CMOS image sensing, storing and calculating integrated circuit integrating sampling calculation - Google Patents
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Abstract
The invention discloses a CMOS image sensing and storing integrated circuit integrating sampling calculation, which belongs to the technical field of integrated circuits and comprises a light inductance storing module, an operation module and a sampling module; the photoelectric sensing storage module converts the light intensity signal into an electric signal and performs multiplication operation with the stored weight value to output current; the operation module is coupled to the output end of the optical inductor storage module, can realize voltage output and is used for realizing summation of input; the sampling module is coupled to the output end of the operation module and is used for carrying out sampling and subtraction operation on the voltage waveform in a fixed period to obtain weighted and summed light intensity information. The invention provides a weight calculation circuit with high-precision optical sensing and automatic sampling processing, which can complete sensing, storage and calculation functions on a single chip. The circuit structure can be applied to the fields of image recognition, image processing and the like, and has the characteristics of small volume, high speed and high integration level.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a CMOS image sensing and storing integrated circuit integrating sampling calculation.
Background
In recent years, with the rapid development of artificial neural network technology, image recognition based on a neural network has become a mature technology. Image recognition is widely used today, such as face recognition, satellite remote sensing, and even military reconnaissance. The essence of the neural network is a series of structured trainable parameters, and the final result is output by performing operations such as weighted summation and the like on the input tensor, so that the input tensor is processed, or data features are extracted in the process to perform operations such as classification, identification and the like. Broadly speaking, computer-implemented image recognition can be divided into three steps: the sensor converts the light intensity signal into an electric signal to realize image acquisition; the computer software stores and processes the collected image information; the artificial neural network carries out forward operation on the processed data and outputs certain characteristic values of image information to realize final identification of the image.
Because a large amount of running resources are needed for the neural network calculation by using a general computer, and the running speed is greatly limited by the speed mismatching of a CPU and a memory in the computer using the traditional architecture, a solution is to build a special system on a chip, so that the neural network calculation of a specific type can be efficiently completed. The sensing and storage integrated circuit is a circuit which structurally and tightly combines image acquisition, weight storage and neural network calculation.
At present, a circuit which can be completed by using a mature process and combines a sensing and storing integrated circuit and later-stage data sampling and sorting does not exist, and reading of a sensing and storing result usually depends on a complex off-chip reading circuit.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide a CMOS sensing and computing integrated circuit structure that integrates sampling computation, and the circuit can automatically implement sensing, storage, computation, and data sampling sorting on a chip.
The technical scheme of the invention is as follows:
a CMOS image sensing and computing integrated circuit integrating sampling computation comprises a light inductance computing module, an operation module and a sampling module; the photo-inductance storage module is a matrix formed by n x n photo-inductance storage units, each photo-inductance storage unit is connected with two row lines and two row lines, wherein the two row lines respectively provide an enabling signal and a resetting signal for the storage weight of each row of photo-inductance storage units, and the two row lines are used for writing 2-bit weight into each row of photo-inductance storage units; the operation module comprises n operation units, and the input of each operation unit is a positive current collection point and a negative current collection point output by all the optical inductor storage modules in each row; the sampling module comprises n sampling units, and the input of each row of sampling units is the output of each row of operation units;
the photoelectric sensing and storing unit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a photodiode, a first SRAM and a second SRAM; the grid of the first MOS tube is connected with a column line for providing a reset signal, the drain of the first MOS tube is connected with a power supply, and the source of the first MOS tube is connected with the cathode of the photodiode and the grid of the second MOS tube; the anode of the photodiode is grounded; the drain electrode of the second MOS tube is connected with a power supply, and the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube and the drain electrode of the fourth MOS tube; the grid electrode of the third MOS tube is connected with the output of the first SRAM, and the source electrode of the third MOS tube outputs forward current; the grid electrode of the fourth MOS tube is connected with the output of the second SRAM, and the source electrode of the fourth MOS tube outputs negative current; the first SRAM and the second SRAM are written with weight values by two row lines under the control of enable signals respectively;
the operation unit is used for converting the input positive current and negative current into voltage and finally executing subtraction operation;
the sampling unit is used for sampling input voltage and amplifying the driving capability of the input voltage when the input end is connected, and electric charge is kept on the capacitor plate when the input end is disconnected to output constant voltage.
Furthermore, the operational unit comprises a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein the negative input end of the first operational amplifier is connected with the positive current collection point Ips, the positive input end of the first operational amplifier is grounded, and the output end of the first operational amplifier is connected with the negative input end of the first operational amplifier through the first resistor; the negative input end of the second operational amplifier is connected with the reverse current collection point Ins, the positive input end of the second operational amplifier is grounded, and the output end of the second operational amplifier is connected with the negative input end of the second operational amplifier through a second resistor; the positive input end of the third operational amplifier is connected with the output end of the first operational amplifier through a third resistor, the negative input end of the third operational amplifier is connected with the output end of the second operational amplifier through a fourth resistor, the positive input end of the third operational amplifier is grounded through a fifth resistor, and the output end of the third operational amplifier is connected with the negative input end of the third operational amplifier through a sixth resistor; the output end of the third operational amplifier is the output end of the operational unit.
Furthermore, the sampling unit comprises a first switch, a second switch, a third switch, a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a seventh operational amplifier, a first capacitor, a second capacitor, a third capacitor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, wherein one end of the first switch is connected with the output end of the operational unit, the other end of the first switch is connected with one end of the first capacitor and the positive input end of the fourth operational amplifier, and the other end of the first capacitor is grounded; the negative input end of the fourth operational amplifier is connected with the output end of the fourth operational amplifier; one end of the second switch is connected with the output end of the fourth operational amplifier, the other end of the second switch is connected with one end of the second capacitor and the positive input end of the fifth operational amplifier, and the other end of the second capacitor is grounded; the negative input end of the fifth operational amplifier is connected with the output end of the fifth operational amplifier; one end of the third switch is connected with the output end of the operation unit, the other end of the third switch is connected with the positive input end of the sixth operational amplifier and one end of the third capacitor, and the other end of the third capacitor is grounded; the negative input end of the sixth operational amplifier is connected with the output end of the sixth operational amplifier; the positive input end of the seventh operational amplifier is connected with the output end of the fifth operational amplifier through a seventh resistor, the negative input end of the seventh operational amplifier is connected with the output end of the sixth operational amplifier through an eighth resistor, the positive input end of the seventh operational amplifier is grounded through a ninth resistor, and the negative input end of the seventh operational amplifier is connected with the output end of the seventh operational amplifier through a tenth resistor; the output end of the seventh operational amplifier is the output end of the sampling unit.
The invention has the beneficial effects that: the invention provides a weight calculation circuit with high-precision optical sensing and automatic sampling processing, which can complete sensing, storage and calculation functions on a single chip. The circuit structure can be applied to the fields of image identification, image processing and the like, and has the characteristics of small volume, high speed and high integration level.
Drawings
FIG. 1 is a schematic diagram of the logic structure of the present invention.
Fig. 2 is a graph showing the relationship between the intensity of light emitted from the photodiode and the magnitude of the reverse current.
Fig. 3 is a schematic diagram of a CMOS inductive computing cell structure.
Fig. 4 is a schematic node waveform diagram of the CMOS sensing unit in each operating mode.
Fig. 5 is a waveform diagram of the output current of the CMOS inductive computing unit under different illumination intensities.
Fig. 6 is a schematic diagram of a CMOS image sensing and computing integrated circuit incorporating sampling computation.
Fig. 7 is a schematic diagram of the structure of the operation module in fig. 5.
Fig. 8 is a schematic diagram of the structure of the sampling module in fig. 5.
Fig. 9 is a schematic of the voltage waveform of the clock signal in the sampling module.
Fig. 10 is a schematic of the voltage waveforms at the input and output of the sampling module.
Detailed Description
The technical scheme of the invention is described in detail in the following with the accompanying drawings:
as shown in fig. 1, the general structural diagram of the present invention includes a photo-inductance storage module, an operation module and a sampling module, where the photo-inductance storage module is a matrix formed by n × n photo-inductance storage units, each photo-inductance storage unit is connected to two column lines and two row lines, where the two column lines respectively provide an enable signal and a reset signal for the storage weight of each column of photo-inductance storage units, and the two row lines are used for writing a 2-bit weight into each row of photo-inductance storage units; the operation module comprises n operation units, and the input of each operation unit is signals of two column lines; the sampling module comprises n sampling units, and the input of each column of sampling units is the output of each column of operation units.
Fig. 2 is a schematic diagram showing the relationship between the illumination intensity of the photodiode and the magnitude of the reverse current. When the photodiode is in reverse bias, incident photons enter the PN junction and excite electron-hole pairs, generated carriers perform drift motion under the influence of reverse voltage to form photocurrent, and the magnitude of the reverse current is controlled by the intensity of the incident light. When the reverse bias voltage is constant, the intensity of the incident light increases to increase the diode current, and the intensity of the incident light is linearly related to the intensity of the diode current in a constant range. Accordingly, the photodiode can be used as a sensing element for linearly converting the light intensity signal into the current signal.
Fig. 3 is a schematic diagram of a CMOS inductive computing unit structure. When the reset signal Vrst is high, the reset MOS transistor 1 is turned on and charges the parasitic capacitance in the photodiode 7 until it approaches the power supply voltage Vdd. After the charging is finished, the reset tube 1 is turned off by setting the Vrst to be low, at the moment, the sensing and calculating unit is exposed under a certain illumination intensity, so that the current flowing through the photodiode 7 is photocurrent, the current is in direct proportion to the incident light intensity, and the parasitic capacitance in the photodiode is discharged, so that the voltage of two ends of the diode is reduced. Due to the effect of the follower tube 2, the voltage change at its source end follows the voltage across the diode, represented by signal V1 (t). In the figure, 5,6 is an SRAM cell, in which a 1-bit digital value is written and stored in advance by an external word line and a bit line, when a stored bit is 10, a weight is 1, 01 represents a weight of-1, and 00 represents a weight of 0, and a voltage is continuously output in a high/low level manner. The values B5 and B6 stored in the unit 5,6 respectively control the on-off of the computing tube 3,4, and taking the SRAM unit 5 and the computing tube 3 as an example, if the value B5 stored in the unit 5 is 0, the unit 5 outputs a low level, so that the unit 3 is turned off, and no current flows; if B5 is 1, i.e. the output power voltage, then 3 is in the deep linear region, which can be equivalent to a resistor Ron, and since the source terminals of 3 and 4 are clamped to the ground level by other modules, the current flowing through 3 is expressed as V1 (t)/Ron. Combining the two case analyses, the current Ip1 (t) flowing through 3 is the product of the analog quantity V1 (t)/Ron and the digital quantity B5, and similarly, the current In1 (t) flowing through 4 is the product of the analog quantity V1 (t)/Ron and the digital quantity B6. Therefore, the difference I1 (t) = Ip1 (t) -In1 (t) = (B5-B6) · V1 (t)/Ron between the two tube currents corresponds to a multiplication operation using V1 (t)/Ron as input data and (B5-B6) as a weight. Here the subtraction is performed by a subsequent arithmetic block.
Fig. 4 is a schematic diagram of waveforms of nodes of the CMOS sensing unit in weight storage and sensing operation. In the weight storage operation, a target weight on the BL is input into the SRAM by setting up the WL, then the WL is set down to enable the weight to be latched in the SRAM without being influenced by the BL, the weight is continuously output from the output end of the SRAM in the form of logic level, and the grid of the computing tube is controlled to realize the multiplication function. In the sensing calculation operation, the conduction current of the SRAM-controlled calculating tube stored with the weight value of 1 is changed with Vrst in a certain working period, and the conduction current of the SRAM-controlled calculating tube stored with the weight value of 0 is always 0. The figure shows the changes of Ips and Ins when B5=1 and B6=0, wherein Ips follows the change of the voltage at two ends of the photodiode, and Ins =0.
Fig. 5 is a schematic waveform diagram of the output current of the CMOS sensing and calculating unit under different illumination intensities. Here B5-B6=1, so the current is positive, the duty cycle of the cell is t0, and the operation is divided into a charge reset phase of length t1 and a discharge operation phase of (t 0-t 1). According to the relationship in fig. 1, the intensity of the light during the period can be represented by the average speed of the discharge, i.e. I (t 1+ n · t 0) -I (t 0+ n · t 0)/t 0= Cpd · Iin (n), where Cpd is a constant determined by the photodiode process and Iin (n) is the intensity of the light detected during the nth period, and this calculation is performed by the subsequent sampling module. Fig. 4 shows the output current curve with the illumination intensity increasing with time, and it can be seen that the average slope of the curve is larger than that of the previous period in the discharge period of each period. The change of the weights B5-B6 will make the output current curve scale along the vertical axis equally, if B5-B6=0, the curve will be equal to 0; if B5-B6= -1, the current of each point on the curve will take a negative value, and the opposite result will be obtained after calculation by the subsequent sampling module. The output ends of the plurality of CMOS sensing and computing units are connected to further expand the range of the output current and are used for representing the addition operation result of the products of the plurality of digital weights and the analog current converted by the light intensity signal.
Fig. 6 is a schematic diagram of a CMOS image sensing and computing integrated circuit integrating sampling computation. In the n-by-n scale circuit, all the sensing and calculating units In the same column are controlled by the same reset signal to work, all Ip and In are respectively added by the operation module, then the Ip and In are subtracted to complete the weighted summation operation, and finally the illumination intensity signal after weighted summation is calculated by the sampling module. In addition to the power supply lines, n column lines WL are shared in an n × n scale circuit to control the enabling of the memory weights of each column, 2n row lines BL are used to write 2-bit weights for all the sense cells, and n column lines Vrst provide reset signals. And the n arithmetic modules and the n sampling modules are connected after the positive summation current Ips and the n negative summation current Ins of the n column lines, and n independent illumination intensity signals after weighted summation are output. When the frequency of the change of the illumination intensity is less than the working frequency of the sensing and calculating unit, the CMOS image sensing and calculating integrated circuit can accurately receive the light intensity signal and carry out weighted summation operation according to columns.
As shown in fig. 7, the operational circuit block includes operational amplifiers 8, 9, and 10, load resistors 11 and 12, input resistors 13, 14, and 16, and a feedback resistor 15. Which acts to clamp the column line and convert the column line current to a voltage, eventually performing a subtraction operation. Wherein R11= R12, R13= R14= R15= R16. All operational amplifiers have very high gain to realize 'virtual short' and 'virtual break', so that the current input terminals Ips, ins are clamped to the GND, and the operational tubes in the preceding stage of the sensing and computing unit can work normally. In the operational circuit module, all amplifiers are powered by double power supplies, so that the column line clamping function can be normally realized, and negative voltage can be output. The operational amplifier 8 and the load resistor 11 convert Ips into Vps = Ips · R11, the operational amplifier 9 and the load resistor 12 similarly convert Ins into Vns = Ins · R12, a voltage subtractor is composed of the operational amplifier 10 and the resistors R13, R14, R15, R16, and Vo = Vps-Vns is output, and the operation of weighted summation is completed.
As shown in fig. 8, the sampling module is composed of operational amplifiers 20, 21, 22, and 23, sampling switches 17, 18, and 19, sampling capacitors 24, 25, and 26, input resistors 27, 28, and 29, and a feedback resistor 30, where R27= R28= R29= R30. The circuit formed by combining the sampling capacitor and the operational amplifier samples input voltage and amplifies the driving capability of the input voltage when the input end is switched on, the charge is kept on a capacitor polar plate when the input end is switched off, the output voltage is constant, and the sampling-holding-buffering function is realized. At the beginning of the discharge phase of the column of all sense cells, a pulse causes sampling switch 17 to briefly open, so that sampling capacitor 24 records Vo at that time. At the end of the discharge phase, another pulse causes sampling switches 18 and 19 to open simultaneously, the voltage on sampling capacitor 24 is copied to sampling capacitor 26 via a buffer circuit formed by op-amp 20, and since the duty cycle is constant, the voltage difference between capacitors 26 and 25 is now proportional to the weighted sum of the illumination intensities, and the column of final image recognition results Vout is output via the buffer amplifier and voltage subtractor.
Fig. 9 is a schematic voltage waveform of the clock signal in the sampling module. Each analog switch is composed of a pair of NMOS and PMOS, and needs 2 clock signals for control, and the sampling module has two independent switches, and needs 4 clock signals in total. In the figure, vrst is a reset signal for controlling the sensor, and is a timing logic for collating the respective signals. In the figure, vn1 and Vp1 are clock signals for controlling the switch 17 in fig. 7, and it is necessary to emit a pulse at the falling edge of Vrst in order for the sampling switch to record the output voltage at the beginning of the discharge; vn2 and Vp2 are clock signals for controlling switches 18 and 19 in fig. 7, and it is necessary to emit a pulse before the next rising edge of Vrst so that the sampling switch records the output voltage at the end of discharge, and at the same time, the initial discharge voltage is conducted to the input terminal of the voltage subtractor to perform sampling result calculation. These clock signals are determined by the reset signal Vrst, which has a short pulse length such that Vo is substantially constant during the time of capacitive sampling.
As shown in fig. 10, the voltage waveforms of the input Vo and the output Vout of the sampling module are shown schematically. Due to the functions of the transmission gates 18 and 19, the sampling module outputs Vout, the voltage value of which is changed only at the end of the work period of the sensing calculation array, and the sensing calculation result of the light intensity in the work period is output. This mode of operation appears in the waveform that Vout always constantly outputs the sensing result of the previous cycle in each cycle, i.e., the read time window is equal to the sensing duty cycle. Fig. 10 illustrates two complete duty cycles and a portion of a third cycle, wherein the weighted intensity is higher in the second duty cycle than in the first cycle, with the result that the output voltage of Vout is higher in the third cycle than in the second cycle.
Claims (3)
1. A CMOS image sensing, storing and calculating integrated circuit integrating sampling calculation is characterized by comprising a light inductance storing and calculating module, an operation module and a sampling module; the photo-inductance storage module is a matrix formed by n x n photo-inductance storage units, each photo-inductance storage unit is connected with two row lines and two row lines, wherein the two row lines respectively provide an enabling signal and a resetting signal for the storage weight of each row of photo-inductance storage units, and the two row lines are used for writing 2-bit weight into each row of photo-inductance storage units; the operation module comprises n operation units, and the input of each operation unit is a positive current collection point and a negative current collection point output by all the optical inductor storage modules in each row; the sampling module comprises n sampling units, and the input of each row of sampling units is the output of each row of operation units;
the photoelectric sensing storage unit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a photodiode, a first SRAM and a second SRAM; the grid electrode of the first MOS tube is connected with a column line for providing a reset signal, the drain electrode of the first MOS tube is connected with a power supply, and the source electrode of the first MOS tube is connected with the cathode of the photodiode and the grid electrode of the second MOS tube; the anode of the photodiode is grounded; the drain electrode of the second MOS tube is connected with a power supply, and the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube and the drain electrode of the fourth MOS tube; the grid electrode of the third MOS tube is connected with the output of the first SRAM, and the source electrode of the third MOS tube outputs forward current; the grid electrode of the fourth MOS tube is connected with the output of the second SRAM, and the source electrode of the fourth MOS tube outputs negative current; the first SRAM and the second SRAM are written with weight values by two row lines under the control of enable signals respectively;
the operation unit is used for converting the input positive current and negative current into voltage and finally executing subtraction operation;
the sampling unit is used for sampling input voltage and amplifying the driving capability of the input voltage when the input end is connected, and electric charge is kept on the capacitor plate when the input end is disconnected to output constant voltage.
2. The CMOS image sensing and computing integrated circuit integrating sampling calculation as claimed in claim 1, wherein the operational unit comprises a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein a negative input end of the first operational amplifier is connected to the positive current collection point Ips, a positive input end thereof is connected to the ground, and an output end thereof is connected to a negative input end thereof through the first resistor; the negative input end of the second operational amplifier is connected with the reverse current collection point Ins, the positive input end of the second operational amplifier is grounded, and the output end of the second operational amplifier is connected with the negative input end of the second operational amplifier through a second resistor; the positive input end of the third operational amplifier is connected with the output end of the first operational amplifier through a third resistor, the negative input end of the third operational amplifier is connected with the output end of the second operational amplifier through a fourth resistor, the positive input end of the third operational amplifier is grounded through a fifth resistor, and the output end of the third operational amplifier is connected with the negative input end of the third operational amplifier through a sixth resistor; the output end of the third operational amplifier is the output end of the operational unit.
3. The CMOS image sensing and storage integrated circuit integrating sampling calculation as claimed in claim 2, wherein the sampling unit comprises a first switch, a second switch, a third switch, a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a seventh operational amplifier, a first capacitor, a second capacitor, a third capacitor, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, wherein one end of the first switch is connected with the output end of the operation unit, the other end of the first switch is connected with one end of the first capacitor and the positive input end of the fourth operational amplifier, and the other end of the first capacitor is grounded; the negative input end of the fourth operational amplifier is connected with the output end of the fourth operational amplifier; one end of the second switch is connected with the output end of the fourth operational amplifier, the other end of the second switch is connected with one end of the second capacitor and the positive input end of the fifth operational amplifier, and the other end of the second capacitor is grounded; the negative input end of the fifth operational amplifier is connected with the output end of the fifth operational amplifier; one end of the third switch is connected with the output end of the operation unit, the other end of the third switch is connected with the positive input end of the sixth operational amplifier and one end of the third capacitor, and the other end of the third capacitor is grounded; the negative input end of the sixth operational amplifier is connected with the output end of the sixth operational amplifier; the positive input end of the seventh operational amplifier is connected with the output end of the fifth operational amplifier through a seventh resistor, the negative input end of the seventh operational amplifier is connected with the output end of the sixth operational amplifier through an eighth resistor, the positive input end of the seventh operational amplifier is grounded through a ninth resistor, and the negative input end of the seventh operational amplifier is connected with the output end of the seventh operational amplifier through a tenth resistor; the output end of the seventh operational amplifier is the output end of the sampling unit.
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