CN115968202A

CN115968202A - 3D memory device and method of manufacturing the same

Info

Publication number: CN115968202A
Application number: CN202310036887.9A
Authority: CN
Inventors: 刘沙沙
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2023-04-14
Also published as: CN111180452B; CN111180452A

Abstract

Disclosed are a 3D memory device and a method of manufacturing the same, the 3D memory device including: a substrate; a gate stack structure over the substrate, the gate stack structure including a plurality of interlayer insulating layers and a plurality of gate conductors alternately stacked; the channel column comprises a functional layer positioned on the side wall of the channel column, an oxidation layer positioned at the bottom of the channel column and a channel layer positioned on the functional layer and the oxidation layer; the channel layer is positioned above the epitaxial layer and is in contact with the epitaxial layer; the functional layer comprises a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer; the charge storage layer is isolated from the channel layer at corners of the functional layer. In the embodiment of the invention, the charge storage layer is isolated from the channel layer at the corner of the functional layer, so that the charge on the charge storage layer is prevented from leaking into the channel layer, and the stability of the threshold voltage of the bottom selection grid of the 3D memory is improved.

Description

3D memory device and method of manufacturing the same

The application is a divisional application of a Chinese patent application with the application date of 2019, 12 and 31, the application number of 201911421883.2 and the name of 3D memory device and a manufacturing method thereof.

Technical Field

The invention relates to the technical field of memories, in particular to a 3D memory device and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the aperture of a semiconductor manufacturing process becomes smaller, the memory density of a memory device becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

The formation process of existing 3D NAND memories generally includes: forming a stacked layer in which silicon nitride layers and silicon oxide layers are alternately stacked on a substrate; etching the stacked layer to form a channel hole in the stacked layer, etching the substrate at the bottom of the channel hole after the channel hole is formed, and forming a groove in the substrate; forming an Epitaxial silicon layer, also commonly referred to as SEG, in the recess at the bottom of the channel hole by Selective Epitaxial Growth (Selective Epitaxial Growth); forming a functional layer and a channel layer in sidewalls and a bottom of the channel hole, the channel layer being connected with an epitaxial silicon layer (SEG); and removing the silicon nitride layer, and forming gate metal at the position where the silicon nitride layer is removed.

The functional layers comprise a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer, and the selected materials can be a single-layer and/or multi-layer combined structure of oxide-nitride-oxide (ONO). The functional layer (ONO layer) may be of two opposite L-shapes in axial cross-section, the charge storage layer and the channel layer being in direct contact at the corners of the functional layer (L-Foot position) which may result in a High electrical resistivity. Due to the poor charge confinement capability of the Bottom Select Gate (BSG), the charge on the charge storage layer is easily leaked into the channel layer, which may cause a shift in the threshold voltage Vt of the bottom select gate BSG, affecting the performance of the 3D memory device, especially during erasing or reading/writing. After repeated erasing or reading/writing, a large amount of charge will accumulate at the corners, further shifting the threshold voltage Vt of the bottom select gate BSG.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a 3D memory device and a method of fabricating the same, which can improve stability of a threshold voltage of a bottom select gate of a 3D memory by isolating a charge storage layer from a channel layer at corners of a functional layer.

According to an aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming an insulating stack structure over a substrate, the insulating stack structure including a plurality of interlayer insulating layers and a plurality of sacrificial layers that are alternately stacked; forming a plurality of channel pillars through the insulating stack structure, the step of forming the channel pillars comprising: forming a plurality of channel holes through the insulating stack structure and a portion of the substrate; forming an epitaxial layer at the bottom of the channel hole, wherein the epitaxial layer is in contact with the semiconductor substrate; forming a functional layer on the side wall and the bottom of the channel hole, wherein the functional layer comprises a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer; removing the charge storage layer at the bottom of the channel hole; forming a channel layer on the functional layer, wherein the channel layer is positioned above the epitaxial layer and is in contact with the epitaxial layer; wherein the charge storage layer is isolated from the channel layer at corners of the functional layer.

Preferably, the step of forming the functional layer on the sidewall of the channel hole and removing the charge storage layer at the bottom of the channel hole includes: forming the functional layer on the sidewall and the bottom of the channel hole; etching the functional layer on the bottom of the channel hole to form a first opening exposing the epitaxial layer; removing the charge storage layer at the bottom of the channel hole to form a gap; and forming an oxide layer on the surface of the functional layer, in the gap and on the side wall and the bottom surface of the first opening.

Preferably, the step of forming the voids comprises: and when the charge storage layer at the bottom of the channel hole is removed, the charge storage layer has a high etching selection ratio relative to the gate oxide layer and the tunneling oxide layer.

Preferably, the ratio of the etching rate of the charge storage layer to the etching rate of the gate oxide layer and the etching rate of the tunneling oxide layer is at least greater than 30.

Preferably, the forming of the channel layer on the functional layer includes: forming a first channel layer on the functional layer and the oxide layer; etching the first channel layer and the oxide layer on the bottom of the first channel hole to form a second opening exposing the epitaxial layer; and forming a second channel layer on the surface of the first channel layer and the bottom and the surface of the side wall of the second opening.

Preferably, the method of manufacturing the 3D memory device further includes: forming a filling layer on the channel layer; and removing the filling layer at the top of the channel hole to form a groove, and forming a plug structure in the groove.

Preferably, the method of manufacturing a 3D memory device further includes: the plurality of sacrificial layers are replaced with a plurality of gate conductors to form a gate stack structure.

According to another aspect of the present invention, there is provided a 3D memory device including: a substrate; a gate stack structure over the substrate, the gate stack structure including a plurality of interlayer insulating layers and a plurality of gate conductors alternately stacked; the channel columns penetrate through the gate laminated structure and comprise a functional layer positioned on the side wall of the channel column, an oxidation layer positioned at the bottom of the channel column and a channel layer positioned on the functional layer and the oxidation layer; the channel layer is positioned above the epitaxial layer and is in contact with the epitaxial layer; the functional layer comprises a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer; the charge storage layer is isolated from the channel layer at corners of the functional layer.

Preferably, the charge storage layer has a high etch selectivity with respect to the gate oxide layer and the tunnel oxide layer.

Preferably, the 3D memory device further includes: a filler layer in the channel pillar, the filler layer in contact with the channel layer; and the plug structure is positioned on the filling layer.

The invention provides a 3D memory device and a manufacturing method thereof.A functional layer is formed on the side wall and the bottom of a channel hole, wherein the functional layer comprises a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer; removing the charge storage layer at the bottom of the channel hole; forming a channel layer on the functional layer; the charge storage layer is isolated from the channel layer at the corners of the functional layer, so that charges on the charge storage layer are prevented from leaking into the channel layer, and the stability of the threshold voltage of the bottom selection grid of the 3D memory is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show a circuit diagram and a schematic structural diagram, respectively, of a memory cell string of a 3D memory device;

FIG. 2 shows a perspective view of a 3D memory device;

fig. 3a to 3j show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The term "above" as used herein means above the plane of the substrate, and may refer to direct contact between materials or spaced apart.

In the present application, the term "semiconductor structure" refers to the generic term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory cells M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of the memory cells M1 to M4 are connected to corresponding ones of the word lines WL1 to WL4, respectively.

As shown in fig. 1b, the selection transistors Q1 and Q2 of the memory cell string 100 include a second conductor layer 122 and a third conductor layer 123, respectively, and the memory cells M1 to M4 include a first conductor layer 121, respectively. The first, second, and

third conductor layers

121, 122, and 123 are stacked in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent conductor layers are separated from each other by an insulating layer, thereby forming a gate stack structure.

Further, the memory cell string 100 includes a memory string 110. Memory string 110 is adjacent to or through the gate stack structure. In the middle portion of the memory string 110, the first conductor layer 121 and the channel layer 111 sandwich the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114, thereby forming memory cells M1 to M4. At both ends of the memory string 110, the gate oxide layer 114 is interposed between the

second conductor layers

122 and 123 and the channel layer 111, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

The channel layer 111 is composed of, for example, doped polysilicon, the tunnel oxide layer 112 and the gate oxide layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the first conductor layer 121, the second conductor layer 122 and the third conductor layer 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the memory string 110 is the channel layer 111, and the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114 form a stacked structure surrounding the core sidewall. In an alternative embodiment, the core of the memory string 110 is an additional insulating layer, and the channel layer 111, the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the first and second selection transistors Q1 and Q2, and the memory cells M1 to M4 use the common channel layer 111 and gate oxide layer 114. In the memory string 110, the channel layer 111 provides source-drain regions and channel layers of a plurality of transistors. In an alternative embodiment, the semiconductor layers and gate oxide layers of the first and second selection transistors Q1 and Q2 and the semiconductor layers and gate oxide layers of the memory cells M1 to M4, respectively, may be formed in steps independent of each other. In the memory string 110, semiconductor layers of the first and second selection transistors Q1 and Q2 and semiconductor layers of the memory cells M1 to M4 are electrically connected to each other.

In a write operation, memory cell string 100 writes data to selected ones of memory cells M1 through M4 using FN tunneling efficiency. Taking the memory cell M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts so that the second selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at a programming voltage VPG, e.g., about 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory cell M2 is higher than the tunneling voltage, electrons in the channel region of the memory cell M2 reach the charge storage layer 113 through the tunneling oxide layer 112, thereby converting data into charges and storing the charges in the charge storage layer 113 of the memory cell M2.

In a read operation, the memory cell string 100 determines the amount of charge in the functional layer according to the on-state of a selected one of the memory cells M1 to M4, thereby obtaining data indicative of the amount of charge. Taking cell M2 as an example, word line WL2 is biased at a read voltage VRD and the remaining word lines are biased at a high voltage VPS2. The on state of the memory cell M2 is related to its threshold voltage, i.e. to the amount of charge in the functional layer, so that the data value can be determined from the on state of the memory cell M2. The memory cells M1, M3, and M4 are always in the on state, and therefore, the on state of the memory cell string 100 depends on the on state of the memory cell M2. The control circuit judges the on state of the memory cell M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory cell M2.

Fig. 2 shows perspective views of the 3D memory devices, respectively. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device 200 shown in this embodiment includes 4 x 4 and a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 and a total of 64 memory cells. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device 200, the memory cell strings 100 respectively include the respective channel pillars 110, and the common first, second, and third conductor layers 121, 122, and 123. The first, second, and third conductor layers 121, 122, and 123 are stacked in accordance with the transistors in the memory cell string 100, and adjacent conductor layers are separated from each other by an insulating layer, thereby forming the gate stack structure 120. The insulating layer is not shown in the figure.

The internal structure of the memory string 110 is shown in FIG. 1b and will not be described in detail here. In the middle portion of the memory string 110, the first conductor layer 121 forms memory cells M1 to M4 together with the channel layer 111, the tunnel oxide layer 112, the charge storage layer 113, and the gate oxide layer 114 inside the memory string 110. At both ends of the memory string 110, the second and third conductor layers 122 and 123 form a first selection transistor Q1 and a second selection transistor Q2 together with the channel layer 111 and the gate oxide layer 114 inside the memory string 110.

The channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array, and the first ends of the plurality of memory strings 110 in the same column are commonly connected to the same bit line (i.e., one of BL1 to BL 4), the second ends are commonly connected to the substrate 101, and the second ends form a common source connection through the substrate 100.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 102. Gate lines of the plurality of channel pillars 110 of the same row are commonly connected to the same string selection line (i.e., one of string selection lines SSL1 through SSL 4).

The gate conductors 121 of the memory transistors M1 and M4 are integrally connected at different levels. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines of the same layer reach the interconnect layer 132 via respective conductive channels 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive channel 133.

The gate conductors of the ground select transistors Q2 are connected integrally. If the gate conductor 123 of the ground selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnect layer 132 via respective conductive channels 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via a conductive channel 133.

The method starts with a semiconductor structure in which a channel hole 102 and an epitaxial layer 103 have been formed, as shown in fig. 3 a.

In this step, an insulating stacked structure 150 formed by alternately stacking interlayer insulating layers 151 and sacrificial layers 152 on a substrate 101, a channel hole penetrating the insulating stacked structure 150, and an epitaxial Layer 103 at the bottom of the channel hole are formed using a Deposition process, such as Atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD). In this embodiment, the substrate 101 is, for example, a single crystal silicon substrate, the interlayer insulating layer 151 is, for example, composed of silicon oxide, and the sacrificial layer 152 is, for example, composed of silicon nitride. The sacrificial layer 152 will be replaced with a conductor layer in a subsequent gate formation process. The Epitaxial layer 103 may, for example, be a Selective Epitaxial Growth (SEG).

In the embodiment, the insulating stack structure shown includes 5 sacrificial layers 152, and the sacrificial layers 152 are set to other numbers according to different requirements of different 3D memory devices on the number of memory cells in the manufacturing process of a specific 3D memory device.

Further, functional layers are formed on the sidewalls of the channel holes 102, and the functional layers include a gate oxide layer 114, a charge storage layer 113 on the gate oxide layer, and a tunnel oxide layer 112 on the charge storage layer, as shown in fig. 3 b.

In this step, a gate oxide layer 114, a charge storage layer 113 and a tunnel oxide layer 112 (initial tunnel oxide layer) are formed in the trench hole along the sidewalls and bottom thereof, and the selected material may be a single-layer and/or multi-layer combination structure of oxide-nitride-oxide (ONO), but is not limited to the materials and combinations mentioned herein. In this embodiment, the gate oxide layer 114 and the tunnel oxide layer 112 are, for example, silicon oxide, and the charge storage layer 113 is, for example, silicon nitride. The gate oxide layer 114, the charge storage layer 113 and the tunnel oxide layer 112 are formed by a chemical vapor deposition process.

Further, the functional layer on the bottom of the channel hole 102 is etched to form a first opening 104 that is exposed or extends into the epitaxial layer 103, as shown in fig. 3 c.

In this step, an anisotropic dry etching process is used to etch the functional layer on the bottom of the trench hole. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a fluorocarbon-containing gas.

Further, the charge storage layer 113 on the bottom of the channel hole 102 is removed to form a void 105, as shown in fig. 3 d.

In this step, the charge storage layer 113 at the bottom of the channel hole is removed by dry etching, which is anisotropic plasma etching in one embodiment. When the charge storage layer 113 at the bottom of the channel hole is removed, the charge storage layer 113 has a high etching selectivity ratio relative to the gate oxide layer 114 and the tunneling oxide layer 112, and the etching rate ratio of the charge storage layer 113 relative to the gate oxide layer 114 and the tunneling oxide layer 112 is at least greater than 30. Since the charge storage layer 113 is a nitride layer and the gate oxide layer 114 and the tunnel oxide layer 112 are oxide layers, that is, the charge storage layer 113 at the bottom of the channel hole is removed by using an etching process with a High Etch selectivity (High Etch selectivity) for the nitride layer (e.g., silicon nitride, siN) and the oxide layer (e.g., silicon oxide), so that the gate oxide layer 114 and the tunnel oxide layer 112 on both sides of the first opening 104 are etched by a small amount.

Further, an oxide layer is formed on the surface of the functional layer, in the void 105, and on the sidewall and bottom surface of the first opening 104, as shown in fig. 3 e.

In this step, a tunnel oxide layer 112 is formed in the trench hole along the surface of the functional layer, in the void, and the sidewall and bottom surface of the first opening, so that the oxide layer at the bottom of the trench hole includes a gate oxide layer 114 and the tunnel oxide layer 112 on the gate oxide layer. In some embodiments, there is no distinct interface between the gate oxide layer 114 and the tunnel oxide layer 112.

Further, a first channel layer 111a is formed on the functional layer and the oxide layer, as shown in fig. 3 f.

In this embodiment, the material of the first channel layer 111a is polysilicon. Further, the channel, first channel layer 111a on the bottom of 102 and the oxide layer are etched to form a second opening 106 exposed or extending into the epitaxial layer, the oxide layer including a gate oxide layer 114 and a tunnel oxide layer 112 on the gate oxide layer, as shown in fig. 3 g.

In this step, the first channel layer 111a and the oxide layer on the bottom of the channel hole are etched using anisotropic dry etching. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a fluorocarbon-containing gas.

Further, a second channel layer 111b is formed on the surface of the first channel layer 111a and the bottom and sidewall surfaces of the second opening 106, as shown in fig. 3 h.

In this embodiment, the material of the second channel layer 111b is polysilicon, and the forming process is chemical vapor deposition. The second channel layer 111b and the first channel layer 111a together constitute the channel layer 111 of the NAND memory. At this time, the charge storage layer 113 is isolated from the channel layer 111.

Further, a filling layer 115 is formed on the channel layer 111 and the filling layer 115 on top of the channel hole 102 is removed to form a recess, in which a plug structure is formed, as shown in fig. 3 i.

In this embodiment, the material of the filling layer 115 is silicon oxide or other suitable materials. And depositing polycrystalline silicon in the groove to form a plug structure, wherein the plug structure is in contact with the channel layer.

Further, the plurality of sacrificial layers 152 are replaced with a plurality of gate conductors to form a gate stack structure 120, as shown in fig. 3j.

In this step, the sacrificial layer 152 is replaced with

gate conductors

121, 122 and 123, thereby forming a gate stack structure 120. The material of the

gate conductors

121, 122 and 123 may be metal or other conductive material (e.g., polysilicon, etc.). In this embodiment, the conductive material is a metal, and the metal is one or more of W, al, cu, ti, ag, au, pt, and Ni. Wherein the epitaxial layer 103 and the gate conductor 121 form a first select transistor; the channel layer 111 and gate conductor 122 form a plurality of memory transistors; the channel layer 111 and the gate conductor 123 form a second selection transistor.

The invention provides a 3D memory device and a method for fabricating the same,

forming a functional layer on the side wall and the bottom of the channel hole, wherein the functional layer comprises a gate oxide layer, a charge storage layer positioned on the gate oxide layer and a tunneling oxide layer positioned on the charge storage layer; removing the charge storage layer at the bottom of the channel hole; forming a channel layer on the functional layer; the charge storage layer is isolated from the channel layer at the corners of the functional layer, so that charges on the charge storage layer are prevented from leaking into the channel layer, and the stability of the threshold voltage of the bottom selection grid of the 3D memory is improved.

Other details of the 3D memory device, such as the structure of the memory array, the peripheral interconnections, etc., are not important to the present invention and will not be described herein.

In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D nand flash memory.

Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes. For example, certain steps are not required and thus may be omitted or replaced with other steps.

The semiconductor structure formed by the above embodiments may be processed by the following conventional steps to obtain a three-dimensional memory device.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A 3D memory device, comprising:

a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate conductors alternately stacked; and

a plurality of channel pillars penetrating the gate stack structure; the channel column comprises a channel layer, a tunneling oxide layer, a charge storage layer and a gate oxide layer which are sequentially arranged along the radial direction of the channel column; wherein the gate oxide layer is connected with the tunneling oxide layer at least at the bottom of the charge storage layer.

2. The 3D memory device of claim 1, wherein the charge storage layer is surrounded at a bottom by the gate oxide layer and the tunnel oxide layer, the charge storage layer being isolated from the channel layer.

3. The 3D memory device of claim 1, wherein a height difference between a lowest surface of a bottom of the gate oxide layer and a bottom of the charge storage layer is greater than a thickness of a top of the gate oxide layer in a radial direction of the channel pillar.

4. The 3D memory device of claim 1, wherein an axial cross-section of the gate oxide layer comprises an L-shape and an axial cross-section of the tunneling oxide layer over the gate oxide layer comprises an L-shape.

5. The 3D memory device of claim 4, wherein an L-shaped axial cross-section of the gate oxide is disposed opposite an L-shaped axial cross-section of the tunnel oxide over the gate oxide on a same side of the channel pillar.

6. The 3D memory device of claim 1, wherein the channel layer includes a second channel layer and a first channel layer surrounding the second channel layer.

7. The 3D memory device of claim 1, wherein the 3D memory device further comprises:

and the epitaxial layer is positioned below the channel column and is in contact with the channel layer.

8. The 3D memory device of claim 1, wherein the charge storage layer has a high etch selectivity ratio with respect to the gate oxide layer and the tunnel oxide layer.

9. The 3D memory device of claim 8, wherein an etch rate ratio of the charge storage layer to the gate oxide layer and the tunnel oxide layer is at least greater than 30.

10. The 3D memory device of claim 1, wherein the 3D memory device further comprises:

a filler layer in the channel pillar, the filler layer in contact with the channel layer;

and the plug structure is positioned on the filling layer.

11. A method of fabricating a 3D memory device, comprising:

forming an insulating stacked structure including a plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked;

forming a plurality of channel pillars through the insulating stack structure, the step of forming the channel pillars comprising:

forming a plurality of channel holes through the insulating stack structure;

sequentially forming a gate oxide layer, a charge storage layer, a tunneling oxide layer and a channel layer on the side wall and the bottom of the channel hole along the radial direction of the channel hole; wherein the gate oxide layer is connected with the tunneling oxide layer at least at the bottom of the charge storage layer.

12. The method of manufacturing of claim 11, wherein the bottom of the charge storage layer is surrounded by the gate oxide layer and the tunnel oxide layer, the charge storage layer being isolated from the channel layer.

13. The method of manufacturing of claim 11 wherein the difference in height between the lowest surface of the bottom of said gate oxide layer and the bottom of said charge storage layer is greater than the thickness of the top of said gate oxide layer in the radial direction of said channel pillar.

14. The manufacturing method according to claim 11, further comprising:

before forming the gate oxide layer, forming an epitaxial layer at the bottom of the channel hole; the formed gate oxide layer is positioned above the epitaxial layer; the channel layer is formed in contact with the epitaxial layer.

15. The manufacturing method according to claim 14, wherein the sequentially forming a gate oxide layer, a charge storage layer, a tunneling oxide layer and a channel layer along a radial direction of the channel hole on the sidewall and the bottom of the channel hole comprises:

sequentially forming a gate oxide layer, a charge storage layer and an initial tunneling oxide layer on the side wall and the bottom of the channel hole along the radial direction of the channel hole;

etching the initial tunneling oxide layer, the charge storage layer and the gate oxide layer on the bottom of the channel hole to form a first opening exposing the epitaxial layer;

removing the charge storage layer at the bottom of the channel hole to form a gap;

forming oxide layers on the surface of the initial tunneling oxide layer, in the gap and on the side wall and the bottom surface of the first opening; wherein the remaining initial tunnel oxide layer and the oxide layer in the void are used to form the tunnel oxide layer;

and forming a channel layer on the tunneling oxide layer, wherein the channel layer is positioned above the epitaxial layer and is in contact with the epitaxial layer.

16. The method of manufacturing of claim 15, wherein the step of forming the void comprises:

and when the charge storage layer at the bottom of the channel hole is removed, the charge storage layer has a high etching selection ratio relative to the gate oxide layer and the tunneling oxide layer.

17. The method of manufacturing of claim 16, wherein the ratio of the etch rate of the charge storage layer to the gate oxide and the tunnel oxide is at least greater than 30.

18. The manufacturing method according to claim 15, wherein the step of forming the channel layer includes:

forming a first channel layer on the tunneling oxide layer and the oxide layer;

etching the first channel layer and the oxide layer on the bottom of the channel hole to form a second opening exposing the epitaxial layer;

and forming a second channel layer on the surface of the first channel layer and the bottom and the side wall surface of the second opening.

19. The manufacturing method according to claim 11, further comprising:

forming a filling layer on the channel layer;

and removing the filling layer at the top of the channel hole to form a groove, and forming a plug structure in the groove.

20. The manufacturing method according to claim 11, characterized by further comprising:

the plurality of sacrificial layers are replaced with a plurality of gate conductors to form a gate stack structure.