CN115968112A - Circuit board preparation method and circuit board - Google Patents
Circuit board preparation method and circuit board Download PDFInfo
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- CN115968112A CN115968112A CN202111175083.4A CN202111175083A CN115968112A CN 115968112 A CN115968112 A CN 115968112A CN 202111175083 A CN202111175083 A CN 202111175083A CN 115968112 A CN115968112 A CN 115968112A
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Abstract
The application discloses a circuit board preparation method and a circuit board, wherein the preparation method comprises the following steps: obtaining a plate to be processed, wherein the plate to be processed comprises a first insulating medium layer and a second insulating medium layer which are arranged in a stacked mode; performing surface treatment on a first preset position on the first insulating medium layer to remove the first insulating medium layer at the first preset position; carrying out whole-board electroplating on the first insulating medium layer to form a first conductive circuit at a first preset position; forming a third insulating medium layer on the first insulating medium layer and the first conductive line; performing surface treatment on a second preset position on the third insulating medium layer to remove the third insulating medium layer at the second preset position; and carrying out whole-plate electroplating on the third insulating medium layer to form a second conductive circuit at a second preset position. This application is through setting up the conducting wire inside insulating medium layer, and the circuit floats when having greatly reduced the conducting wire and leaves or pull the possibility of taking off.
Description
Technical Field
The application relates to the technical field of circuit board processing, in particular to a circuit board preparation method and a circuit board.
Background
With the development of the 5G technology, electronic products have more and more comprehensive functions and smaller volumes, so that the requirements on circuit boards are higher and higher, and the PCB industry is driven to develop towards high density, high integration and multilayering.
In the prior art, tenting processes and MSAP (modified semi-addition process) are commonly used to prepare high density circuits.
However, the conductive lines formed by the Tenting and MSAP processes are on the substrate, and the problem of line floating or pulling off is easily caused when external force is applied, so that the reliability of the lines is low.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a circuit board and a manufacturing method thereof, which can solve the problem of low circuit reliability caused by the fact that a conductive circuit is formed on a substrate.
In order to solve the above technical problem, one technical solution adopted by the present application is to provide a method for manufacturing a circuit board, including: obtaining a plate to be processed, wherein the plate to be processed comprises a first insulating medium layer and a second insulating medium layer which are arranged in a stacked mode; performing surface treatment on a first preset position on the first insulating medium layer to remove the first insulating medium layer at the first preset position; carrying out whole-board electroplating on the first insulating medium layer to form a first conductive circuit at a first preset position; forming a third insulating medium layer on the first insulating medium layer and the first conductive line; performing surface treatment on a second preset position on the third insulating medium layer to remove the third insulating medium layer at the second preset position; and carrying out whole-plate electroplating on the third insulating medium layer to form a second conductive circuit at a second preset position.
Wherein, carry out whole board electroplating to first insulating medium layer to in the step of first conducting wire is formed to first default position, specifically include: carrying out hole treatment on the plate to be treated after surface treatment so as to form a conductor film on the first insulating medium layer, the first preset position and the second insulating medium layer; respectively attaching anti-plating photosensitive films to the surfaces of one sides, far away from the first insulating medium layer, of the first insulating medium layer and the second insulating medium layer; and carrying out whole-plate electroplating on the plate to be processed attached with the plating-resistant photosensitive film so as to form a first conductive circuit at a first preset position.
Wherein the hole treatment comprises copper deposition treatment, black hole treatment or shadow treatment.
Wherein, carry out whole board electroplating to the pending panel that is attached to have the anti-sensitization membrane of plating to behind the step of first conducting wire of position formation in first default, still include: and removing the plating-resistant photosensitive film.
Wherein, carry out whole board electroplating to the third insulating medium layer to after the step of forming the second conducting wire in second preset position, further include: repeating the layer adding steps until the required number of layers is obtained, attaching the anti-plating photosensitive film to the preset position of the plate to be processed after the layers are added for many times, carrying out pattern transfer on the plate to be processed after the layers are added for many times, forming a conductive circuit on the plate to be processed after the layers are added for many times, and removing the anti-plating photosensitive film to obtain the circuit board.
Wherein, carry out whole board electroplating to the third insulating medium layer to after the step of forming the second conducting wire in second preset position, still include: performing surface treatment on a third preset position on the second insulating medium layer to remove the second insulating medium layer at the third preset position; and carrying out whole-board electroplating on the second insulating medium layer to form a third conductive circuit at a third preset position so as to obtain the circuit board.
The step of forming a third insulating dielectric layer on the first insulating dielectric layer and the first conductive line specifically includes: and pressing an insulating material on the first insulating medium layer and the first conductive circuit to form a third insulating medium layer.
The insulating material used for forming the first insulating medium layer, the second insulating medium layer and the third insulating medium layer comprises one or more of epoxy resin, phenolic resin, polyimide, BT, ABF and ceramic.
Wherein, carry out surface treatment to the first preset position on the first insulating dielectric layer to get rid of the first insulating dielectric layer of first preset position step still includes: and carrying out surface treatment on the first preset position on the first insulating medium layer in one or more modes of laser ablation, laser cutting, ion cutting and water jet to remove the first insulating medium layer at the first preset position.
In order to solve the technical problem, another technical scheme adopted by the application is to provide a circuit board, wherein the circuit board is manufactured by the circuit board manufacturing method.
The beneficial effect of this application is: different from the prior art, the circuit board manufacturing method and the circuit board provided by the application have the advantages that the conducting circuit is arranged in the insulating medium layer, so that the possibility that the circuit floats or is pulled off when the conducting circuit is subjected to external force is greatly reduced, and the reliability of the conducting circuit is improved. Furthermore, as the conductive circuit is arranged in the substrate, a thick copper layer is not needed to be used and the thick copper layer is not needed to be corroded, the consistency of the circuit can be improved, and the thickness of the whole printed circuit board can be reduced. In addition, because the ultra-thin copper foil is not needed when the layer is added, the preparation efficiency can be improved, and the preparation cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart of one embodiment of a method for manufacturing a circuit board according to the present application;
fig. 2 is a schematic structural diagram of an embodiment of the plate to be processed obtained in step S11;
FIG. 3 is a schematic structural diagram of an embodiment of the plate to be processed after the surface treatment in step S12;
FIG. 4 is a top view of one embodiment of the sheet to be treated of FIG. 3;
FIG. 5 is a flowchart illustrating one embodiment of step S13;
fig. 6 is a schematic structural diagram of an embodiment of the board to be processed after the plating resist photosensitive film is attached in step S132;
fig. 7 is a schematic structural diagram of an embodiment of the plate to be processed after the whole plate is electroplated in step S133;
FIG. 8 is a schematic structural diagram of an embodiment of the board to be processed after layer addition in step S14;
FIG. 9 is a schematic structural diagram of an embodiment of the board to be processed after the surface treatment in step S15;
FIG. 10 is a schematic structural diagram of an embodiment of the board to be processed after the whole board is electroplated in step S16;
FIG. 11 is a schematic structural diagram of a first embodiment of the wiring board of the present application;
fig. 12 is a schematic structural diagram of a second embodiment of the wiring board of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" typically includes at least two, but does not exclude the presence of at least one.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
With the development of 5G technology and microelectronic technology, the PCB panel is gradually miniaturized and has high density, the size of the chip is smaller and smaller, but the operation speed is faster and faster, and accordingly, the heat generation of the chip is larger and larger. The normal operation of any chip needs to satisfy a working range, if the normal working range of the chip is to be maintained, the heat generated by the chip needs to be rapidly conducted, otherwise the performance of the chip is restricted.
In the prior art, tenting processes and MSAP (modified semi-addition process) are commonly used to prepare high density circuits. However, the conductive lines formed by the tentting and MSAP processes are both on the substrate, and the problem of line floating or pull-off is easily caused when external force is applied, so that the reliability of the lines is low.
Based on the above situation, the application provides a circuit board manufacturing method and a circuit board, which can solve the problem of low circuit reliability caused by the conductive circuit formed on the substrate.
The present application will be described in detail below with reference to the drawings and embodiments.
Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a method for manufacturing a circuit board according to the present application. As shown in fig. 1, in the present embodiment, the method includes:
s11: and obtaining the plate to be processed, wherein the plate to be processed comprises a first insulating medium layer and a second insulating medium layer which are arranged in a stacked mode.
In this embodiment, the insulating material used for forming the first insulating medium layer and the second insulating medium layer includes one or more of epoxy resins, phenol resins, polyimides, BT, ABF, and ceramic base.
In this embodiment, the second insulating dielectric layer is laminated and cured before being pre-laminated, and the first insulating dielectric layer is not laminated and cured before being pre-laminated because the first insulating dielectric layer is subjected to surface treatment to remove part of the dielectric layer and to ensure the filling force and flow force of the copper layer during electroplating.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the board to be processed obtained in step S11. As shown in fig. 2, the plate material 100 to be processed includes a first insulating medium layer 10 and a second insulating medium layer 20 which are stacked.
S12: and carrying out surface treatment on a first preset position on the first insulating medium layer to remove the first insulating medium layer at the first preset position.
In this embodiment, the first predetermined position is a position on the first insulating medium layer where a circuit pattern needs to be formed.
In this embodiment, the first preset position on the first insulating medium layer is subjected to surface treatment by one or more of laser ablation, laser cutting, ion cutting and water jet to remove the first insulating medium layer at the first preset position.
It can be understood that the surface treatment method adopted by the embodiment does not include chemical etching, is not limited by the thickness of the material, does not need to use a thick copper layer and corrode the thick copper layer, and can avoid the problem of data nonuniformity in etching, thereby improving the consistency of the circuit and reducing the thickness of the whole printed circuit board.
Further, different from the prior art that high-precision circuit etching equipment needs to be matched, the configuration cost required by the surface treatment mode adopted by the embodiment is low, and the preparation cost of high-density circuits can be reduced.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the board to be processed after the surface treatment in step S12. As shown in fig. 3, the plate material to be processed 200 includes a first insulating medium layer 10 and a second insulating medium layer 20 which are stacked, and the first insulating medium layer 10 includes a first predetermined position 101. The first predetermined position 101 is a position on the first insulating dielectric layer 10 where a circuit pattern needs to be formed.
Further, referring to fig. 4, fig. 4 is a top view of one embodiment of the board to be processed in fig. 3. As shown in fig. 4, the first insulating medium layer 10 on the first predetermined position 101 is removed for forming a conductive trace later.
S13: and carrying out whole-board electroplating on the first insulating medium layer to form a first conductive circuit at a first preset position.
Specifically, referring to fig. 5, fig. 5 is a flowchart illustrating an embodiment of step S13. As shown in fig. 5, in this embodiment, the step of performing full-board electroplating on the first insulating medium layer to form the first conductive trace at the first preset position specifically includes:
s131: and carrying out hole treatment on the plate to be treated after surface treatment so as to form a conductor film on the first insulating medium layer, the first preset position and the second insulating medium layer.
In this embodiment, the hole formation process includes a copper deposition process, a black hole process, or a shadow process.
Specifically, through carrying out the porose processing to the panel of treating, can cover a layer of electrically conductive material in first preset position department, be convenient for follow-up carry out the pore-filling electroplating to it. The black hole treatment is to dip-coat fine graphite or carbon black paint (black hole solution) on the hole wall and/or hole bottom of the hole to form a conductive layer. The shadow treatment refers to that the shadow solution containing the unique additive and the conductive colloidal substance is coated on the hole wall or/and the hole bottom of the hole in a dipping way, so that a conductive layer is formed on the hole wall or/and the hole bottom; the copper deposition treatment is to deposit a thin layer of chemical copper on the hole wall and/or the hole bottom of the hole by a chemical method to serve as a substrate for electroplating.
S132: and attaching anti-plating photosensitive films to the surfaces of the first insulating medium layer and the second insulating medium layer, which are far away from the first insulating medium layer, respectively.
The plating-resistant photosensitive film is a high molecular compound, and can generate a polymerization reaction after being irradiated by a specific light source to form a stable substance attached to the surface of the plate, so that the function of blocking electroplating is achieved. Among them, the polymerization is a reaction process for synthesizing a polymer from monomers.
Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of the board to be processed after the plating resist photosensitive film is attached in step S132. As shown in fig. 6, the board 300 to be processed includes a stacked anti-plating photosensitive film 102 attached to the first insulating medium layer 10, the second insulating medium layer 20, and an anti-plating photosensitive film 202 attached to the second insulating medium layer 20, where the first insulating medium layer 10 includes a first predetermined position 101. The first predetermined position 101 is a position on the first insulating dielectric layer 10 where a circuit pattern needs to be formed.
S133: and carrying out whole-plate electroplating on the plate to be processed attached with the plating-resistant photosensitive film so as to form a first conductive circuit at a first preset position.
The whole board electroplating is carried out on the board to be processed attached with the anti-plating photosensitive film, the groove at the first preset position is metalized and a conductor copper layer is formed, and therefore the first conducting circuit is formed.
It can be understood that, since the first conductive trace is disposed in the groove of the first insulating medium layer, rather than being formed above the first insulating medium layer, the first conductive trace is disposed inside the first insulating medium layer, so that the possibility that the first conductive trace is lifted or pulled off due to an external force is greatly reduced, and the reliability of the first conductive trace is further improved.
Further, after the plating resistance of the whole plate is finished, the plating resistance photosensitive film is removed.
Specifically, referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of the board to be processed after the whole board is electroplated in step S133. As shown in fig. 7, the plate material 400 to be processed includes a first insulating medium layer 10 and a second insulating medium layer 20 stacked together, and a first conductive circuit 110 is formed on the first insulating medium layer 10.
S14: and forming a third insulating medium layer on the first insulating medium layer and the first conductive line.
In this embodiment, an insulating material is pressed on the first insulating dielectric layer and the first conductive line to form a third insulating dielectric layer.
Wherein the insulating material used to form the third insulating dielectric layer includes one or more of epoxy resins, phenolic resins, polyimides, BT, ABF and ceramic based materials.
Specifically, please refer to fig. 8, wherein fig. 8 is a schematic structural diagram of an embodiment of the plate to be processed after the layer is added in the step S14. As shown in fig. 8, the plate material 500 to be processed includes a third insulating medium layer 30, a first insulating medium layer 10 and a second insulating medium layer 20 which are stacked, and a first conductive circuit 110 is formed on the first insulating medium layer 10.
S15: and carrying out surface treatment on a second preset position on the third insulating medium layer to remove the third insulating medium layer at the second preset position.
In this embodiment, the second predetermined position is a position on the third insulating medium layer where a circuit pattern needs to be formed.
In this embodiment, the second preset position on the third insulating medium layer is subjected to surface treatment by one or more of laser ablation, laser cutting, ion cutting and water jet to remove the third insulating medium layer at the second preset position.
Specifically, referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of the board to be processed after the surface treatment in step S15. As shown in fig. 9, the plate material 600 to be processed includes a third insulating medium layer 30, a first insulating medium layer 10 and a second insulating medium layer 20, which are stacked, the first conductive circuit 110 is formed on the first insulating medium layer 10, and the third insulating medium layer 30 includes a second preset position 301. The second predetermined position 301 refers to a position on the third insulating dielectric layer 30 where a circuit pattern needs to be formed.
S16: and carrying out whole-plate electroplating on the third insulating medium layer to form a second conductive circuit at a second preset position.
For a specific whole plate electroplating process, please refer to steps S131 to S133, which are not described herein again.
It can be understood that, in the embodiment, since the insulating medium layer is added and the conductive circuit is formed in the groove of the insulating medium layer to realize layer addition, an ultra-thin copper foil is not required to be used, and the preparation cost of the high-density circuit can be further reduced.
It can be understood that, since the second conductive traces are disposed in the grooves of the third insulating medium layer, rather than being formed above the third insulating medium layer, the possibility that the traces of the second conductive traces are lifted or pulled off due to external force is greatly reduced, and thus the reliability of the second conductive traces is improved.
Specifically, referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of the plate to be processed after the whole plate is electroplated in step S16. As shown in fig. 10, the board 700 to be processed includes a third insulating medium layer 30, a first insulating medium layer 10 and a second insulating medium layer 20, which are stacked, a first conductive circuit 110 is formed on the first insulating medium layer 10, and a second conductive circuit 310 is formed on the third insulating medium layer 30.
In this embodiment, if the layer addition does not need to be continued, the third preset position on the second insulating medium layer is subjected to surface treatment to remove the second insulating medium layer at the third preset position, and the second insulating medium layer is subjected to whole-board electroplating to form a third conductive circuit at the third preset position, so as to obtain the circuit board.
Specifically, please refer to fig. 11, wherein fig. 11 is a schematic structural diagram of a first embodiment of the circuit board of the present application. As shown in fig. 11, the circuit board 800 includes a third insulating medium layer 30, a first insulating medium layer 10, and a second insulating medium layer 20, which are stacked, wherein a second conductive circuit 310 is formed on the third insulating medium layer 30, a first conductive circuit 110 is formed on the first insulating medium layer 10, and a third conductive trace 210 is formed on the second insulating medium layer 20.
In this embodiment, if layer addition is required, the above layer addition steps (steps S14 to S16 and steps S131 to S133) are repeated until the required number of layers is obtained, and then the plating-resistant photosensitive film is attached to the preset position of the board to be processed after multiple layer addition, and the board to be processed after multiple layer addition is subjected to pattern transfer, so as to form a conductive circuit on the board to be processed after multiple layer addition, and remove the plating-resistant photosensitive film, so as to obtain the circuit board.
The preset position comprises the last layer of insulating medium layer and a position on the second insulating medium layer where a conducting circuit is required to be formed.
Here, the formation of a four-layer wiring board is described as an example. Specifically, please refer to fig. 12, wherein fig. 12 is a schematic structural diagram of a second embodiment of the circuit board of the present application. As shown in fig. 12, the circuit board 900 includes a fourth insulating medium layer 40, a third insulating medium layer 30, a first insulating medium layer 10, and a second insulating medium layer 20, which are stacked, a fourth conductive circuit 410 is formed on the fourth insulating medium layer 40, a second conductive circuit 310 is formed on the third insulating medium layer 30, a first conductive circuit 110 is formed on the first insulating medium layer 10, and a third conductive circuit 210 is formed on the second insulating medium layer 20.
The difference and prior art, this application is through setting up the conducting wire inside insulating medium layer, has greatly reduced the conducting wire and has received the possibility that external force appears that the circuit floats to leave or pull off to the reliability of conducting wire has been promoted. Furthermore, as the conductive circuit is arranged in the base material, a thick copper layer is not needed to be used and corroded, the consistency of the circuit can be improved, and the thickness of the whole printed circuit board can be reduced. In addition, because the ultra-thin copper foil is not needed when the layer is added, the preparation efficiency can be improved, and the preparation cost can be reduced.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method for manufacturing a circuit board, comprising:
obtaining a plate to be processed, wherein the plate to be processed comprises a first insulating medium layer and a second insulating medium layer which are arranged in a stacked mode;
performing surface treatment on a first preset position on the first insulating medium layer to remove the first insulating medium layer at the first preset position;
carrying out whole-board electroplating on the first insulating medium layer to form a first conductive circuit at the first preset position;
forming a third insulating dielectric layer on the first insulating dielectric layer and the first conductive line;
performing surface treatment on a second preset position on the third insulating medium layer to remove the third insulating medium layer at the second preset position;
and carrying out whole-plate electroplating on the third insulating medium layer to form a second conductive circuit at the second preset position.
2. The method for manufacturing a circuit board according to claim 1, wherein the step of performing full-board electroplating on the first insulating medium layer to form the first conductive traces at the first preset position specifically includes:
carrying out hole treatment on the plate to be treated after surface treatment so as to form conductor films on the first insulating medium layer, the first preset position and the second insulating medium layer;
respectively attaching anti-plating photosensitive films to the surfaces of one sides, far away from the first insulating medium layer, of the first insulating medium layer and the second insulating medium layer;
and carrying out whole-plate electroplating on the plate to be processed attached with the plating-resistant photosensitive film so as to form the first conductive circuit at the first preset position.
3. The method for manufacturing a wiring board according to claim 2, wherein the hole formation treatment includes a copper deposition treatment, a black hole treatment, or a shadow treatment.
4. The method for manufacturing a circuit board according to claim 2, wherein after the step of performing whole-board electroplating on the board to be processed to which the plating-resistant photosensitive film is attached to form the first conductive traces at the first predetermined position, the method further comprises:
and removing the plating-resistant photosensitive film.
5. The method for manufacturing a circuit board according to claim 4, wherein after the step of performing full-board electroplating on the third insulating medium layer to form the second conductive traces at the second preset position, the method further comprises:
repeating the layer adding steps until the required number of layers is obtained, attaching the anti-plating photosensitive film to the preset position of the board to be processed after the layers are added for many times, carrying out pattern transfer on the board to be processed after the layers are added for many times, forming a conductive circuit on the board to be processed after the layers are added for many times, and removing the anti-plating photosensitive film to obtain the circuit board.
6. The method for manufacturing a circuit board according to claim 1, wherein after the step of performing full-board electroplating on the third insulating medium layer to form the second conductive traces at the second preset position, the method further comprises:
performing surface treatment on a third preset position on the second insulating medium layer to remove the second insulating medium layer at the third preset position;
and carrying out whole-board electroplating on the second insulating medium layer to form a third conductive circuit at the third preset position so as to obtain the circuit board.
7. The method for manufacturing a circuit board according to claim 1, wherein the step of forming a third insulating dielectric layer on the first insulating dielectric layer and the first conductive line specifically includes:
and pressing an insulating material on the first insulating medium layer and the first conducting circuit to form the third insulating medium layer.
8. The method of manufacturing a wiring board according to claim 7, wherein the insulating material used for forming the first insulating dielectric layer, the second insulating dielectric layer, and the third insulating dielectric layer includes one or more of epoxy resins, phenolic resins, polyimides, BT resins, ABF resins, and ceramic resins.
9. The method for manufacturing a circuit board according to claim 1, wherein the step of performing surface treatment on the first preset position on the first insulating dielectric layer to remove the first insulating dielectric layer at the first preset position further comprises:
and carrying out surface treatment on the first preset position on the first insulating medium layer in one or more modes of laser ablation, laser cutting, ion cutting and water jet to remove the first insulating medium layer at the first preset position.
10. A wiring board characterized by being produced by the wiring board production method according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111175083.4A CN115968112A (en) | 2021-10-09 | 2021-10-09 | Circuit board preparation method and circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111175083.4A CN115968112A (en) | 2021-10-09 | 2021-10-09 | Circuit board preparation method and circuit board |
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| Publication Number | Publication Date |
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| CN115968112A true CN115968112A (en) | 2023-04-14 |
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| CN202111175083.4A Pending CN115968112A (en) | 2021-10-09 | 2021-10-09 | Circuit board preparation method and circuit board |
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| CN (1) | CN115968112A (en) |
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2021
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