CN115966478A - 半导体器件和封装的方法 - Google Patents
半导体器件和封装的方法 Download PDFInfo
- Publication number
- CN115966478A CN115966478A CN202111184282.1A CN202111184282A CN115966478A CN 115966478 A CN115966478 A CN 115966478A CN 202111184282 A CN202111184282 A CN 202111184282A CN 115966478 A CN115966478 A CN 115966478A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- bond
- hole
- bonding
- shielding layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05547—Structure comprising a core and a coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
- H01L2224/05691—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48507—Material at the bonding interface comprising an intermetallic compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/4852—Bonding interface between the connecting portion and the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
- H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48817—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48824—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
- H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
- H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8534—Bonding interfaces of the connector
- H01L2224/85345—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8534—Bonding interfaces of the connector
- H01L2224/85359—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
- H01L2224/85365—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
- H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
- H01L2224/85379—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
- H01L2224/85801—Soldering or alloying
- H01L2224/8581—Soldering or alloying involving forming an intermetallic compound at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8593—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
- H01L2224/85947—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by mechanical means, e.g. "pull-and-cut", pressing, stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
- H01L2924/35121—Peeling or delaminating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/36—Material effects
- H01L2924/365—Metallurgical effects
- H01L2924/3651—Formation of intermetallics
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
一种用于封装半导体器件的方法包括:将接合线的端头的球在半导体器件的遮蔽层的孔中接合到半导体器件管芯的接合垫;其中遮蔽层的孔包括侧墙,及配置为暴露接合垫的一部分,以及遮蔽层配置为覆盖接合垫的其余部分;以及通过使接合线的球变形以遮蔽层的孔来封住由遮蔽层的孔所暴露的接合垫的一部分,以使遮蔽层的孔由接合线的球完全填充,从而使遮蔽层的侧墙变形。
Description
技术领域
本发明涉及一种半导体器件和用于封装半导体器件的方法。
背景技术
封装半导体器件典型地包括将引线接合到半导体器件管芯上的接合垫。经接合的引线使信号能够传输到半导体器件管芯和自半导体器件管芯传出。在器件管芯上的接合垫和引线通常由不同材料制成,所述接合利用了由不同材料所形成的合金。在接合之后,封装工艺使用模封化合物将经接合的组合体包封。由于元电池效应,特定的组分例如氯离子与合金发生反应,可能导致腐蚀,这给经接合的互连的可靠性带来挑战。
发明内容
本发明内容被提供以介绍以下具体实施方式部分详述的概念中经选择的简化部分。本发明内容并不意欲确定权利要求中内容的关键或必要特征,亦不意欲使其限制权利要求的范围。
根据一种实施方式,一种用于封装半导体器件的方法包括:
将接合线的端头的球在半导体器件的遮蔽层的孔中接合到半导体器件管芯的接合垫;其中遮蔽层的孔包括侧墙,及配置为暴露接合垫的一部分,以及遮蔽层配置为覆盖接合垫的其余部分;以及
通过使接合线的球变形以遮蔽层的孔来封住由遮蔽层的孔所暴露的接合垫的一部分,以使遮蔽层的孔由接合线的球完全填充,从而使遮蔽层的侧墙变形。
在一个或多个实施方式中,接合垫包括铝,以及合线包括铜,以及其中将接合线的球接合到半导体器件管芯的接合垫包括形成铝铜合金。
在一个或多个实施方式中,遮蔽层包括聚合物或有机硅树脂。
在一个或多个实施方式中:遮蔽层包括聚酰亚胺和甲基硅氧烷之一。
在一个或多个实施方式中,接合线的球为具有在20μm至40μm的范围中的直径的半球,以及其中所述孔为具有小于45μm的直径的圆形;以及其中将接合线的球接合到半导体器件管芯的接合垫包括将接合线的球的尺寸扩展到至少45μm,以接触孔的侧墙。
在一个或多个实施方式中,使遮蔽层的侧墙变形包括接合线的球将孔的侧墙横向地后推。
根据另一实施方式,一种半导体器件包括:
包括接合垫的器件管芯,以及覆盖接合垫的一部分的遮蔽层,遮蔽层具有在接合垫的其余部分之上的孔;
连接物,具有电性地和机械地在孔中连接到接合垫的端头,其中连接物的端头接触孔的侧墙;以及
模封化合物,配置为包封器件管芯和连接物的端头,其中模封化合物与接合垫分离。
在一个或多个实施方式中,接合垫包括铝。
在一个或多个实施方式中:遮蔽层包括聚合物或有机硅树脂。
在一个或多个实施方式中:遮蔽层包括聚酰亚胺或甲基硅氧烷。
在一个或多个实施方式中:遮蔽层的孔为具有40-45μm的直径的圆形。
在一个或多个实施方式中:接合垫的尺寸大于孔的直径。
在一个或多个实施方式中:接合垫的尺寸为45μm。
在一个或多个实施方式中:连接物的端头配置为完全填充遮蔽层的孔,以使模封化合物通过接触连接物的端头而不接触接合垫来包封。
根据另一种实施方式,一种半导体器件包括:
具有表面的基底;
在基底的表面上的至少一个接合垫;以及
在表面上的遮蔽层,其中遮蔽层包括孔,以暴露接合垫的一部分,以及遮蔽层配置为覆盖接合垫的其余部分;以及其中
遮蔽层可变形,以使孔能够扩展以接收接合线的端头来接合到接合垫。
在一个或多个实施方式中:接合垫包括铝。
在一个或多个实施方式中:遮蔽层包括聚合物和有机硅树脂之一。
在一个或多个实施方式中:遮蔽层包括聚酰亚胺。
在一个或多个实施方式中:遮蔽层包括甲基硅氧烷。
在一个或多个实施方式中:孔为圆形。
附图说明
为使本发明前述内容可以更具体的方式得以理解,本发明的进一步详细的描述可以参考实施方式而得到,其中部分由所附的图例而展示。所附图例仅展示本发明的典型实施方式,且因本发明可以具有其他相同地有效实施方式,所附图例不应理解为限制本发明的范围。附图是为便于理解而非测量本发明而绘制。对于本领域的技术人员而言,在阅读了本描述并结合所附图例,所要求的发明主题的益处将易于理解。在附图中,相似的标记数字被用来指示相似的元件,以及:
图1是一种半导体器件管芯的顶部视图;
图2是根据一种实施方式的半导体器件的顶部视图;
图3是根据一种实施方式的封装的半导体器件的剖面视图;
图4是根据一种实施方式的用于封装半导体器件的方法的流程图;以及
图5和图6是根据一种实施方式的用于封装半导体器件的方法的步骤中半导体器件的剖面视图。
具体实施方式
图1是一种半导体器件的顶部视图。图1中部分示出的该半导体器件100特别地具有在基底的表面上的接合垫102。图1的视图可以是半导体器件100的放大视图,例如通过使用扫描电子显微镜(Scanning Electron Microscope,SEM)。半导体器件100可以是通过晶圆工艺制造的半导体器件管芯。典型地由铝材料形成的接合垫102被提供来通过其与例如接合线或凸块等连接物的电性连接而承载进出半导体器件100的信号和能量,该连接后续将进一步详细描述。半导体器件100进一步包括钝化层104,钝化层104设置在接合垫102之上,并被图案化以暴露接合垫102。如图1所示的,钝化层104被图案化以暴露接合垫102的全部,以及形成环绕接合垫102的环。该环大体如图1所示可见的为方形,但亦可为其他形状,例如长方形或圆形。
半导体器件100包括设置于其表面之上的遮蔽层106。遮蔽层亦被图案化以暴露接合线102的全部。钝化层104和遮蔽层106设置为保护其下的半导体器件100的例如有源区的部分免于例如周遭的湿气、灰尘、或者其他化学污染物等外来物(Foreign Material,FM)。然而,图1所示的接合垫102在与例如铜线的连接物通过形成铝铜合金接头而接合之后,既不被钝化层104、又不被遮蔽层106所覆盖。环绕接合垫102的环亦是如此。不完全的覆盖留出了暴露的缝隙,通过该缝隙,特定的物质例如如上所述的氯离子可以入侵,从而由于例如在氯离子的情况下的元电池效应而与合金发生反应。这将导致互连的腐蚀。
图2所示是根据一种实施方式的半导体器件的顶部视图。该半导体器件200与图1的半导体器件100类似,包括基底202、在基底202的表面上的至少一个接合垫204、以及也在基底202的表面上的遮蔽层206。基底202包括在例如硅的半导体材料圆片之上和之中形成的多个层以及互连。基底202的多个层和互连形成半导体元胞或器件,例如晶体管。尽管图2示出了仅一个接合垫204,在其他实施方式中,半导体器件200可以是一个或多个半导体器件管芯,以及每个器件管芯可以包括一个或多个接合垫204。该实施方式的遮蔽层206在图2中示出为“透视的”或半透明的,以揭示接合垫204,以利于理解。在各种实施方式中,遮蔽层206可以是透明的或不透明的,这取决于它的材料。该实施方式的遮蔽层206暴露接合垫204的一部分,以及覆盖接合垫204的其余部分。然而,如图2中可见的,遮蔽层206覆盖钝化层(图2中未标示)的全部。
遮蔽层206配置为具有在接合垫204之上的孔208。孔208使接合垫204的一部分暴露。在所示的实施方式中,孔208是圆形的,具有小于45μm的直径,例如40-45μm,以及接合垫204的开口尺寸(接合垫开口,Bond Pad Opening,BPO,典型地通过将钝化层图案化以暴露接合垫204而形成)可以典型地是大体方形,具有52μm的长度和宽度,其比孔208的直径大,从而该接合垫204的部分被遮蔽层206所覆盖,而接合垫204的其他一部分则从孔208暴露。根据实施方式的遮蔽层206由聚合物(polymer)或有机硅树脂(organic silicon resin)形成。更具体地,遮蔽层206由聚酰亚胺(polyimide)或甲基硅氧烷(methyl silicone)通过在半导体器件基底202的制造中的旋涂(spin coating)工艺而形成。具体地,可溶性聚酰亚胺(polyimide)前体,例如3,3’,4,4’-二苯酮四酸二酐(3,3’,4,4’-benzophenonetetracarboxylic dianhydride,BTDA)、二氨基二苯醚(oxydianiline,ODA)、或间苯二胺(meta-phenylenediamine,MPD)的酰胺共聚物(amide copolymer),被旋涂到基底202的表面上。经旋涂的基底202随后被施加负像掩膜(negative mask),其后送经热固化和/或紫外辐照工艺下的曝光,以被固化和/或交联(cross-link)。在固化过程后,涂布材料的掩膜和未固化区域,例如孔208的区域,通过喷雾溶剂、离子刻蚀、或反应离子刻蚀(reactive ionetching,RIE)而去除,从而接合垫204的所述部分由孔208处暴露。在实施方式中,遮蔽层206具有在2μm到7μm的厚度,优选地2-5μm,并可以具有4μm的厚度。
应可理解的是,孔208进一步允许例如接合线的连接物被电性地和机械地连接到接合垫204的暴露部分,这将在后续进一步详细描述。如前所述地,根据一个或多个实施方式,接合垫204可由铝材料制成,将要连接的接合线典型地由铜制成。在接合垫204和连接物之间的电性和机械连接通过使用接合垫204的铝材料和连接物的铜材料来形成金属间化合物(intermetallic compound,IMC,在铜线和铝接合垫的情况下为铝铜合金)作为界面区域来实现。通过形成合金界面区域(具体地为IMC),连接物的端头(亦称接合球,ball-bond或bonded ball)在孔208之内被接合到接合垫204。根据本实施方式的遮蔽层206,特别是其侧墙,是可变形的,以允许孔208在容纳将连接到接合垫204的暴露部分的连接物时被横向扩展。典型地,遮蔽层206和接合垫204之间的接合或连接本身不受该变形的影响:任何可能使遮蔽层206从孔208的周缘脱离的压力将由来自位于连接物的端头的相对致密的接合球的向下的力所平衡。孔208的直径小于连接物的端头(接合球)的直径,从而孔208由接合球和/或所形成的IMC完全填充,而在接合球的侧边和接合垫204的“斑块”之间不为后续的模封化合物留出空间。“斑块”意为接合垫204的一个区域,其为所形成的合金界面区域或其周边区域,在铝质接合垫的情况下,“斑块”也可称为“铝斑”。换言之,在接合时,即在传统的键合中,接合线发生变形,然而遮蔽层206中的孔208的有限尺寸限制了形成接合球和填充孔208时接合线的横向延展,从而提供了阻挡湿气或其他不良物质入侵的有效封闭。由于模封化合物不与接合垫204或铝铜合金接头(IMC)相接触,亦即模封化合物完全地与接合垫204相分离,连接物与接合垫204之间的连接可以被保护免受腐蚀。
现在转向图3,其示出了根据一种实施方式的半导体器件300的剖面视图。该半导体器件300是使用了图2的半导体器件管芯200的封装的器件,其中图2的标记亦包括在图3中。器件管芯200包括:在其中如前所述地制造有半导体器件的基底202、接合垫204、以及覆盖接合垫204的至少一部分的遮蔽层206。封装的半导体器件300进一步地包括连接物302,或称接合线,其具有端头304,端头304电性地和机械地连接到接合垫204。连接物302的端头304在遮蔽层206的孔208中连接到接合垫204。封装的半导体器件300包括模封化合物306,其包封器件管芯200和至少连接物302的端头304。
所示的实施方式中的接合线302由铜制成,以及在铜质端头304与铝质接合垫204之间的接合界面处形成铝铜合金界面区域。端头304和所形成的铝铜合金完全地填充遮蔽层206的孔208,而接合垫204的其余部分由遮蔽层206覆盖,不为模封化合物306的入侵留出空间。遮蔽层206的孔208具有侧墙210,侧墙210与接合线302的端头304接触。换言之,在后续的包封过程中引入半导体器件300的模制化合物306不能到达接近在接合垫204和端头304之间的界面。具有铝铜合金的接合垫204和端头304从而被保护不受腐蚀。
图4所示的是用于封装半导体器件的方法的流程图。该方法适用于封装图2的半导体器件200而成为如图3所示的封装的半导体器件300,该方法将进一步参照图5和图6的在该封装的方法中的半导体器件的剖面视图而描述。该方法始自步骤402,其中连接物302的端头304接合到半导体器件200的接合垫204。连接物302被导引到半导体器件200的遮蔽层206的孔208中。参照图5所示,例如为铜接合线的连接物302被置于例如键合机的接合机构的劈刀(capillary)402中,并对准接合垫204的暴露部分。在该实施方式中,接合线302的直径H是23μm。接合线302的端头304是半球形,在该实施方式中亦称为自由端球(烧球,FreeAir Ball,FAB)、或者接合线302的球304,具有30μm的直径。在可选的实施方式中当施加具有相同或不同的直径的接合线302时,FAB的直径可以在20-40μm的范围中。端头304可以通过在孔208中接合之前向铜线302的自由端施加电弧而形成。通过所施加的电弧,铜材料熔化在产生熔滴,其为图5中标记304所示的半球形。
图4的方法随后有步骤404,其中暴露在遮蔽层206的孔208中的接合垫204的至少一部分被与遮蔽层206在孔208的周缘相接触的端头304所封闭。参考图6,劈刀402向接合垫204移动,连接物302的端头304在接触到接合垫204时被施加另一高能量,例如超声脉冲,以焊接到接合垫204。经施加超声波脉冲、并经劈刀402将线302推动与接合垫204相抵,接合球304发生形变,并横向扩展到具有等于或大于45μm的直径(球直径,Ball Diameter,BD),该球直径BD大于孔208的直径,其中半球形的球304的高度(球高度,Ball Height,BH)减小到12μm。现在,球304的直径大于遮蔽层206的孔208的直径,球304接触孔208的侧墙210。实施方式的遮蔽层206至少在接合垫204与连接物302的接合连接时是弹性的,随着接合球304的横向扩展,孔208发生形变,遮蔽层206由接合球304横向地后推,并被挤出从而孔208完全地由端头304所填充,且由孔208所暴露的接合垫204的部分由球状端球304所封闭。在遮蔽层由聚酰亚胺形成的实施方式中,遮蔽层的杨氏模量是3GPa。在其他实施方式中,它也可以优选地具有更大的弹性,因此可以改用不同的材料。平衡弹性与遮蔽层材料与接合垫材料之间的粘合性可能是必要的,以允许形变并避免剥落。例如,在遮蔽层由甲基硅氧烷形成时,杨氏模量是0.75MPa,其使遮蔽层206具有足够的弹性而在被端头304接触时便利地产生形变。然而,由于端头304是半球状的,以及孔208是圆形的,即使遮蔽层206具有其他弹性相对较高的材料,仍可能所述接触与低弹性遮蔽层206的接触一样无缝。可以理解的是,铝铜合金接头在高功率脉冲施加时形成,以将接合线302与接合垫204电学地和机械地相连接。如所述的,接合线302的直径在一种实施方式中是23μm,并且其他尺寸,例如所述的BPO、FAB、BD、BH也是根据接合线302的示例尺寸的例子。在可选的实施方式中,接合线的直径可以具有不同的值,例如20μm、25μm、33μm、38μm、50μm等,并且该等其他尺寸也可以在不同实施方式中有所变化。例如,如果接合线的直径是23μm,端头球304(自由端球,Free Air Ball,FAB)的直径在28-35μm的范围内,经延伸的球直径(Ball Diameter,BD)在40-50μm的范围内,以及球高度(Ball Height,BH)在10-15μm的范围内。然而,接合线的直径是依据接合垫204的尺寸(接合垫开口,Bond Pad Opening,BPO)而选择的,据此FAB、BD、以及BH的尺寸也可变化。
步骤406,经连接的器件管芯200和连接物302被用模封化合物306包封起来,以产生封装的半导体器件300。如所理解的,由于在遮蔽层206、接合垫204、以及端头304之间没有缝隙,在包封中模封化合物306不会流动到与接合垫204和球状端头304的接头界面处的铝铜合金或者与铝质接合垫204相接触,而是与接合垫204或合金的界面区域相分离。所提供的模封化合物306与合金及接合垫204的隔离阻碍了前述的由于元电池效应导致的腐蚀。
在此参考了特定的所示的例子对于各种示例的实施方式进行了描述。所述示例的例子被选择为辅助本领域的技术人员来形成对于各实施方式的清晰理解并得实施。然而,可以构建为包括一个或多个实施方式的系统、结构和器件的范围,以及根据一个或多个实施方式实施的方法的范围,并不为所展示的示例性例子所限制。相反地,所属技术领域的技术人员基于本说明书可以理解:可以根据各实施方式来实施出很多其他的配置、结构和方法。
应当理解的是,就于本发明在前描述中所使用的各种位置指示来说,例如顶、底、上、下,彼等指示仅是参考了相应的附图而给出,并且当器件的朝向在制造或工作中发生变化时,可以代替地具有其他位置关系。如上所述,那些位置关系只是为清楚起见而描述,并非限制。
本说明的前述描述是参考特定的实施方式和特定的附图,但本发明不应当限制于此,而应当由权利要求书所给出。所描述的各附图都是示例性的而非限制性的。在附图中,为示例的目的,各元件的尺寸可能被放大,且可能没有绘制为特定的比例尺。本说明也应当包括各元件、工作方式在容限和属性上的不连续的变换。还应当包括本发明的各种弱化实施。
本说明及权利要求书中所使用的词汇“包括”并不排除其他元件或步骤。除非特别指出,在使用单数形式如“一”、“一个”指代确定或不确定的元件时,应当包括该元件的复数。从而,词汇“包括”不应当被理解为限于在其后所列出的条目,不应当理解为不包括其他元件或步骤;描述“器件包括项目A和B”的范围不应当限制为只包括元件A和B的器件。该描述表示,就于本说明而言,只有器件的元件A和B是相关的。尽管耦合通常包括电感性的连接、连接通常意为通过例如电线的连接,然而此处所述“连接”、“耦接”、“耦合”均表示在相耦接或相连接的元件之间存在电学的联系,且不意味着其间没有中间元件。在描述晶体管及其连接时,词语栅、漏、和源与栅极、漏极、源极以及栅极端、漏极端、源极端是可互换的。
对于所属领域的技术人员而言,在不背离本发明的权利要求的范畴内可以作出多种具体变化。
Claims (10)
1.一种用于封装半导体器件的方法,其特征在于,包括:
将接合线的端头的球在半导体器件的遮蔽层的孔中接合到半导体器件管芯的接合垫;其中遮蔽层的孔包括侧墙,及配置为暴露接合垫的一部分,以及遮蔽层配置为覆盖接合垫的其余部分;以及
通过使接合线的球变形以遮蔽层的孔来封住由遮蔽层的孔所暴露的接合垫的一部分,以使遮蔽层的孔由接合线的球完全填充,从而使遮蔽层的侧墙变形。
2.根据权利要求1所述的方法,其特征在于,接合线的球为具有在20μm至40μm的范围中的直径的半球,以及其中所述孔为具有小于45μm的直径的圆形;以及其中将接合线的球接合到半导体器件管芯的接合垫包括将接合线的球的尺寸扩展到至少45μm,以接触孔的侧墙。
3.根据权利要求1所述的方法,其特征在于,使遮蔽层的侧墙变形包括接合线的球将孔的侧墙横向地后推。
4.一种半导体器件,其特征在于,包括:
包括接合垫的器件管芯,以及覆盖接合垫的一部分的遮蔽层,遮蔽层具有在接合垫的其余部分之上的孔;
连接物,具有电性地和机械地在孔中连接到接合垫的端头,其中连接物的端头接触孔的侧墙;以及
模封化合物,配置为包封器件管芯和连接物的端头,其中模封化合物与接合垫分离。
5.根据权利要求4所述的半导体器件,其特征在于:遮蔽层的孔为具有40-45μm的直径的圆形。
6.根据权利要求5所述的半导体器件,其特征在于:接合垫的尺寸大于孔的直径。
7.根据权利要求4所述的半导体器件,其特征在于:连接物的端头配置为完全填充遮蔽层的孔,以使模封化合物通过接触连接物的端头而不接触接合垫来包封。
8.一种半导体器件,其特征在于,包括:
具有表面的基底;
在基底的表面上的至少一个接合垫;以及
在表面上的遮蔽层,其中遮蔽层包括孔,以暴露接合垫的一部分,以及遮蔽层配置为覆盖接合垫的其余部分;以及其中
遮蔽层可变形,以使孔能够扩展以接收接合线的端头来接合到接合垫。
9.根据权利要求8所述的半导体器件,其特征在于:接合垫包括铝。
10.根据权利要求8所述的半导体器件,其特征在于:孔为圆形。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111184282.1A CN115966478A (zh) | 2021-10-11 | 2021-10-11 | 半导体器件和封装的方法 |
EP22198870.2A EP4163966A1 (en) | 2021-10-11 | 2022-09-29 | Wire bonded semiconductor device and method of manufacturing the same |
US17/938,471 US20230110402A1 (en) | 2021-10-11 | 2022-10-06 | Semiconductor device and method for packaging |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111184282.1A CN115966478A (zh) | 2021-10-11 | 2021-10-11 | 半导体器件和封装的方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115966478A true CN115966478A (zh) | 2023-04-14 |
Family
ID=83508882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111184282.1A Pending CN115966478A (zh) | 2021-10-11 | 2021-10-11 | 半导体器件和封装的方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20230110402A1 (zh) |
EP (1) | EP4163966A1 (zh) |
CN (1) | CN115966478A (zh) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5716493B2 (zh) * | 1973-11-16 | 1982-04-05 | ||
JPS60223149A (ja) * | 1984-04-19 | 1985-11-07 | Hitachi Ltd | 半導体装置 |
JPH0794639A (ja) * | 1993-06-14 | 1995-04-07 | Toshiba Corp | 半導体装置及び製造方法 |
-
2021
- 2021-10-11 CN CN202111184282.1A patent/CN115966478A/zh active Pending
-
2022
- 2022-09-29 EP EP22198870.2A patent/EP4163966A1/en active Pending
- 2022-10-06 US US17/938,471 patent/US20230110402A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20230110402A1 (en) | 2023-04-13 |
EP4163966A1 (en) | 2023-04-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7109055B2 (en) | Methods and apparatus having wafer level chip scale package for sensing elements | |
US5682065A (en) | Hermetic chip and method of manufacture | |
US7495179B2 (en) | Components with posts and pads | |
US7011989B2 (en) | Method for producing encapsulated chips | |
JP4528100B2 (ja) | 半導体装置及びその製造方法 | |
US7202113B2 (en) | Wafer level bumpless method of making a flip chip mounted semiconductor device package | |
CN105225967A (zh) | 封装半导体器件的方法和封装的半导体器件 | |
US7939379B2 (en) | Hybrid carrier and a method for making the same | |
US7911043B2 (en) | Wafer level device package with sealing line having electroconductive pattern and method of packaging the same | |
US7629688B2 (en) | Bonded structure and bonding method | |
CN115966478A (zh) | 半导体器件和封装的方法 | |
US7951644B2 (en) | Semiconductor device and method for fabricating the same | |
US20080006940A1 (en) | Lead frames, microelectronic devices with lead frames, and methods for manufacturing lead frames and microelectronic devices with lead frames | |
CN212151613U (zh) | 芯片封装结构 | |
JP3715861B2 (ja) | 半導体装置の組立方法 | |
US9437457B2 (en) | Chip package having a patterned conducting plate and method for forming the same | |
US20040256719A1 (en) | MEMS micro-cap wafer level chip scale package | |
US10074581B2 (en) | Chip package having a patterned conducting plate and a conducting pad with a recess | |
TW202416465A (zh) | 晶片封裝體及其製造方法 | |
JPH11150144A (ja) | 半導体装置及びその製造方法 | |
TWI441310B (zh) | 半導體封裝件及其製造方法 | |
CN113526449A (zh) | 芯片封装结构及其制法 | |
KR20020049721A (ko) | 돌출형 볼 패드들이 구비된 캐리어 필름 및 그를 이용한칩 스케일 패키지 | |
JPH04237133A (ja) | 電子チップ部品の金属バンプ形成方法 | |
KR20110107122A (ko) | 반도체 패키지 및 이의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication |