CN115940907A - Power-on reset circuit and system on chip - Google Patents
Power-on reset circuit and system on chip Download PDFInfo
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- CN115940907A CN115940907A CN202211680317.5A CN202211680317A CN115940907A CN 115940907 A CN115940907 A CN 115940907A CN 202211680317 A CN202211680317 A CN 202211680317A CN 115940907 A CN115940907 A CN 115940907A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a power-on reset circuit and a system on a chip, wherein the power-on reset circuit comprises: a voltage comparison unit and a comparison voltage generation unit; the output of the comparison voltage generation unit is electrically connected with the input of the voltage comparison unit; the comparison voltage generating unit is used for generating comparison voltage and inputting the comparison voltage into the voltage comparing unit; and the voltage comparison unit is used for receiving the comparison voltage and outputting a low level or a high level so as to complete power-on reset. In order to reduce the influence of process and temperature deviation on threshold voltage, the power-on reset circuit adopts an improved band-gap reference source structure; meanwhile, a double-threshold voltage detection circuit with a hysteresis function is designed, so that the interference of power supply noise on circuit output is reduced, and the reliability of the reset circuit is improved, thereby improving the accuracy and reliability of power-on reset and reducing the dispersion of the power-on reset of the system on chip.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a power-on reset circuit and a system on a chip.
Background
In the design of Soc (system On chip), a Power-On Reset (POR) circuit is an indispensable module. Powering on the systemIn the process, in order to ensure that the system can be started correctly, the power-on reset circuit needs to provide an internal reset signal to initialize the logic circuit until the power supply voltage is stabilized to the normal working voltage specified by the system, and then the reset signal is cancelled, and the corresponding power supply voltage value, namely the power-on threshold voltage is marked as U POR . In the power-down process, when the power supply voltage is lower than the minimum working voltage of the chip, the main part of the chip stops working, and the voltage is U PDR 。
The first architecture of the conventional POR circuit is shown in fig. 4, and the circuit utilizes the principle that the voltage on the capacitor cannot change abruptly to generate a reset signal through RC charging, wherein the diode functions to quickly discharge the charge accumulated on the capacitor at the moment of power-off so as to generate an effective reset signal at the next power-on. The reset circuit with the simple structure has the advantages that the threshold voltage is greatly influenced by temperature and process angle, and certain requirements are imposed on the power-on and power-off speeds of a power supply. In most system designs, a low voltage protection function is also required, that is, during the normal operation of the system, if the power supply voltage is too low, an automatic reset signal is still required to be provided, which takes into account the noise of the power supply, and PDR is generally required to be smaller than POR in order to avoid the generation of some unnecessary reset signals. Another architecture divides the power supply voltage with resistors and compares the divided voltage with a reference voltage to output a signal, which is released through a delay portion, as shown in fig. 5. The circuit utilizes the resistor string to carry out voltage division sampling on the power voltage, and compares the voltage comparison unit with the voltage reference source to output a reset signal, because the threshold is generated compared with the reference, the dispersion of POR is relatively good, but because the circuit is compared with the reference voltage, the circuit function is relatively independent and is easy to be influenced, and in addition, the reliability of the POR circuit is ensured, and the level of tens of us is generally selected.
Disclosure of Invention
The invention aims to overcome the defects of low accuracy, low reliability and high dispersion of a power-on reset circuit provided by the prior art, and provides the power-on reset circuit and a system on a chip.
The invention solves the technical problems through the following technical scheme:
the invention provides a power-on reset circuit, which comprises:
a voltage comparison unit and a comparison voltage generation unit;
the output of the comparison voltage generation unit is electrically connected with the input of the voltage comparison unit;
the comparison voltage generating unit is used for generating comparison voltage and inputting the comparison voltage into the voltage comparing unit;
and the voltage comparison unit is used for receiving the comparison voltage and outputting a low level or a high level so as to complete power-on reset.
Preferably, the comparison voltage generating circuit includes a first NMOS transistor, N first diodes, M second diodes, a first resistor, a second resistor, a third resistor, a fifth resistor, and a sixth resistor;
one end of the fifth resistor is connected with a power supply, and the other end of the fifth resistor is electrically connected with one end of the second resistor and one end of the third resistor;
the other end of the second resistor is electrically connected with one end of the first resistor and the drain electrode of the first NMOS tube respectively;
n first diodes are connected in parallel;
the other end of the first resistor is electrically connected with a source electrode of the first NMOS tube;
one end of each first diode is electrically connected with the other end of the first resistor and the source electrode of the first NMOS tube;
the other end of each first diode and the third resistor are grounded;
m second diodes are connected in parallel;
one end of the sixth resistor is connected with a power supply, and the other end of the sixth resistor is electrically connected with one end of each second diode respectively;
the other end of each second diode is grounded;
the sixth resistor and the fifth resistor have the same resistance value;
the first diode and the second diode have the same parameters;
n is more than M and more than 0, and both N and M are integers.
Preferably, the comparison voltage generating circuit includes a first NMOS transistor, N first triodes, M second triodes, a first resistor, a second resistor, a third resistor, a fifth resistor, and a sixth resistor;
one end of the fifth resistor is connected with a power supply, and the other end of the fifth resistor is electrically connected with one end of the second resistor and one end of the third resistor;
the other end of the second resistor is electrically connected with one end of the first resistor and the drain electrode of the first NMOS tube respectively;
the N first triodes are connected in parallel;
the other end of the first resistor is electrically connected with a source electrode of the first NMOS tube;
an emitting electrode of each first triode is electrically connected with the other end of the first resistor and a source electrode of the first NMOS tube;
the base electrode and the collector electrode of each first triode and the third resistor are grounded;
the M second triodes are connected in parallel;
one end of the sixth resistor is connected with a power supply, and the other end of the sixth resistor is electrically connected with the emitting electrode of each second triode respectively;
the base electrode and the collector electrode of each second triode are grounded;
the sixth resistor and the fifth resistor have the same resistance value;
the parameters of the first triode and the second triode are the same;
n is more than M and more than 0, and both N and M are integers.
Preferably, the comparison voltage generation circuit further comprises a fourth resistor;
one end of the fourth resistor is electrically connected with the other end of the sixth resistor; the other end of the fourth resistor is grounded.
Preferably, the voltage comparison circuit comprises a first PMOS transistor, a second NMOS transistor, a third NMOS transistor and a seventh resistor;
the source electrode of the first PMOS tube is connected with a power supply;
the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the second PMOS tube;
the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the second NMOS tube;
the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the third NMOS tube;
the source electrode of the second PMOS tube and the source electrode of the third NMOS tube are both electrically connected with one end of the seventh resistor;
the other end of the seventh resistor is grounded.
Preferably, the power-on reset circuit further comprises a waveform shaping circuit.
Preferably, the waveform shaping circuit comprises an inverter.
The invention also provides a system on chip, which comprises the power-on reset circuit.
The positive progress effects of the invention are as follows:
the embodiment discloses a power-on reset circuit, which adopts an improved band-gap reference source structure in order to reduce the influence of process and temperature deviation on threshold voltage; meanwhile, a double-threshold voltage detection circuit with a hysteresis function is designed, so that the interference of power supply noise on circuit output is reduced, and the reliability of the reset circuit is improved, thereby improving the accuracy and reliability of power-on reset and reducing the dispersion of the power-on reset of the system on chip.
Drawings
Fig. 1 is a schematic diagram of a power-on reset circuit according to embodiment 1 of the present invention.
Fig. 2 is a transient simulation diagram of the power-on reset circuit according to embodiment 1 of the present invention.
Fig. 3 is a schematic diagram of simulation data in embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of a first common power-on reset circuit according to embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of a second common power-on reset circuit according to embodiment 1 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, this embodiment 1 discloses a power-on reset circuit, which includes:
a voltage comparison unit and a comparison voltage generation unit;
the output of the comparison voltage generation unit is electrically connected with the input of the voltage comparison unit;
the comparison voltage generating unit is used for generating comparison voltage and inputting the comparison voltage into the voltage comparing unit;
and the voltage comparison unit is used for receiving the comparison voltage and outputting a low level or a high level so as to complete power-on reset.
Specifically, the comparison voltage generation circuit may employ the following two circuits: the comparison voltage generating circuit comprises an Nmos tube, N first diodes, M second diodes, a first resistor, a second resistor, a third resistor, a fifth resistor and a sixth resistor;
one end of the fifth resistor is connected with a power supply, and the other end of the fifth resistor is electrically connected with one end of the second resistor and one end of the third resistor;
the other end of the second resistor is electrically connected with one end of the first resistor and the drain electrode of the first NMOS tube respectively;
n first diodes are connected in parallel;
the other end of the first resistor is electrically connected with a source electrode of the first NMOS tube;
one end of each first diode is electrically connected with the other end of the first resistor and the source electrode of the first NMOS tube;
the other end of each first diode and the third resistor are grounded;
m second diodes are connected in parallel;
one end of the sixth resistor is connected with a power supply, and the other end of the sixth resistor is electrically connected with one end of each second diode respectively;
the other end of each second diode is grounded;
the sixth resistor and the fifth resistor have the same resistance value;
the first diode and the second diode have the same parameters;
n is more than M and more than 0, and both N and M are integers.
As shown in fig. 1, in the second circuit, the comparison voltage generating circuit includes a first NMOS transistor NM1 and N first transistors Q 1 M second triodes Q 2 A first resistor R 1 A second resistor R 2 A third resistor R 3 A fifth resistor R 5 And a sixth resistor R 6 ；
The fifth resistor R 5 One end of which is connected with a power supply V DD Said fifth resistor R 5 And the other end of the second resistor R 2 And a third resistor R 3 Is electrically connected with one end of the first connecting rod;
the second resistor R 2 Respectively connected with the first resistor R 1 Is electrically connected to the drain of the first NMOS transistor NM 1;
n first triodes Q 1 Connecting in parallel;
the first resistor R 1 The other end of the first NMOS tube NM1 is electrically connected with the source electrode of the first NMOS tube NM 1;
each first triode Q 1 And the first resistor R 1 The other end of the first NMOS tube NM1 is electrically connected with the source electrode of the first NMOS tube NM 1;
each of the first triodes Q 1 And the base and collector of (2) and the third resistor R 3 Are all grounded;
m second triodes Q 2 Parallel connection;
the sixth resistor R 6 Is connected to a power supply, the sixth resistor R 6 In addition toOne end of each of the second triodes Q 2 Is electrically connected with the emitter;
each of the second triodes Q 2 The base electrode and the collector electrode are both grounded;
the sixth resistor R 6 And said fifth resistance R 5 The resistance values are the same;
the first triode Q 1 And the second triode Q 2 The parameters are the same;
n is more than M and more than 0, and both N and M are integers.
According to the scheme, the compatibility of the power-on reset circuit is improved by adopting the triode.
The two comparison voltage generation circuits may further include a fourth resistor R 4 ；
The fourth resistor R 4 And the sixth resistor R 6 The other end of the first and second electrodes is electrically connected; the fourth resistor R 4 And the other end of the same is grounded.
Adding a fourth resistor R in the power-on reset circuit 4 The reliability of the electrical reset circuit can be improved.
Specifically, the voltage comparison circuit may include a first PMOS transistor PM1, a second PMOS transistor PM2, a second NMOS transistor NM1, a third NMOS transistor NM1, and a seventh resistor R 7 ；
The source electrode of the first PMOS pipe PM1 is connected with a power supply;
the grid electrode of the first PMOS tube PM1 is electrically connected with the grid electrode of the second PMOS tube PM 2;
the drain electrode of the first PMOS pipe PM1 is electrically connected with the drain electrode of the second NMOS pipe NM 2;
the drain electrode of the second PMOS tube PM2 is electrically connected with the drain electrode of the third NMOS tube NM 3;
the source electrode of the second PMOS tube PM2 and the source electrode of the third NMOS tube NM3 are both electrically connected with one end of the seventh resistor R7;
the other end of the seventh resistor R7 is grounded.
In one implementation, the power-on reset circuit further includes a waveform shaping circuit.
In particular, the waveform shaping circuit includes an inverter.
In this scheme, if the first transistor Q starts to rise from 0V when the power supply voltage rises 1 A second triode Q 2 And when the power supply is in an off state, outputting low voltage. When the power supply voltage rises to exceed Q 1 、Q 2 After the threshold voltage of (3), the triode Q 1 And Q 2 The starting of the device is carried out,
q in the present scheme 1 And Q 2 When the ratio n of (a) to (b) is 8, Q is obtained in the process of starting power-on 2 Current on branch I 2 Less than Q 1 Current on branch I 1 . Since the fifth resistance (R) is equal to the sixth resistance R 5 ＝R 6 Thus, R 6 Is less than R 5 So that the voltage at the inverting input of the comparison unit is greater than the voltage at the non-inverting input, i.e. V N >V P The output voltage is low, and simultaneously NM1 is in a conducting state, R 1 Is short-circuited. As the supply voltage rises further, due to I 2 <I 1 And R is 6 <R 5 +R 2 Then, as the power supply voltage rises, the transistor Q 2 The voltage variation of the base electrode and the emitting electrode is larger than that of the triode Q 1 Of (a), i.e. Δ V be2 |>|△V be1 Which directly leads to an increase in current Δ I 2 >ΔI 1 Thereby reducing the voltage across the voltage comparison unit until the power supply voltage reaches the POR power-on threshold, V N ＝V P ＝V be2 At this time, the power-on threshold of POR is denoted as Vries, because the voltages at two ends of the voltage comparison unit are equal, R 5 ＝R 6 So as to flow through R 5 Is equal to the current flowing through R 6 At this time I 2 ＝I 1 . At this time I 1 Current equal to Q 1 And Q 2 At a resistor R 2 The current generated in the upper part is added with the positive terminal voltage of the voltage comparison unit, namely V be2 At the resistance R 3 The current generated. Therefore, the power supply voltage at this time can be obtained from the comparison voltage generation unit part in the circuit, and is equal to V be2 Plus I 1 *R 5 The following formula:
both sides are divided by V simultaneously be2 The front coefficients have
Because at room temperature,
to the temperature of formula (3) and let
The temperature coefficient voltage with Vise of zero can be obtained as follows:
from this, it is understood that a zero temperature coefficient voltage larger than 1.25V is obtained, and the amplification ratio depends on the resistance R 3 And a resistance R 5 The circuit realizes the function of the power-on reset circuit, and the power-on reset circuit also has the characteristic of low dispersion.
When the supply voltage exceeds Vries, V N <V P The output of the voltage comparison unit jumps from a low level to a high level,and completing the power-on reset process. The low voltage protection reset is a reverse process of the power-on reset, except that during the low voltage protection reset, s a The initial state of the output is high, so NM1 is off, so resistor R 1 The switched-in circuit resets and outputs a turnover threshold value PDR from high level to low level, and the voltage is recorded as V fall . Similarly, another threshold value can be obtained, which is R in the formula (2) 2 Is replaced by (R) 1 +R 2 ) The reference voltage value obtained later can obtain PDR<POR。
As can be seen from the above equation, the temperature coefficient of the threshold voltage depends on V T The coefficient of the proportional resistance coefficient, which changes when power is turned on or off. Generally, the accuracy of the power-down threshold, i.e., the PDR, is more important, so that the accuracy of the temperature coefficient of the threshold needs to be ensured when the power is down. I.e. determined by a zero temperature coefficient
After the proportion is determined, the hysteresis of the power-on reset circuit of the scheme is changed by changing R 1 The resistance value of (2) is changed, and can be specifically adjusted according to actual needs.
The embodiment discloses a power-on reset circuit, which adopts an improved Kuijk band-gap reference source structure in order to reduce the influence of process and temperature deviation on threshold voltage; meanwhile, a dual-threshold voltage detection circuit with a hysteresis function is designed, so that the interference of power supply noise on circuit output is reduced, and the reliability of a reset circuit is improved, thereby improving the accuracy and reliability of power-on reset and reducing the power-on reset dispersion of a system on a chip.
To further illustrate the effect of the power-on reset circuit of the present embodiment, the circuit is built and verified by simulation. The simulation results obtained by different combinations of 3 process corners of mos transistors, such as TT, SS, FF, SF and FS,3 process corners of polysilicon resistors, such as res _ TT, res _ SS and res _ FF, and 3 BJT process corners, such as bip _ TT, bip _ SS and bip _ FF, are shown in figure 2, the power-on reset circuit has a good reset function, and the design realizes stable and reliable power-on reset and low-level protection functions. As can be seen from FIG. 3, the power-down threshold is between 2.145V and 2.226V, the power-down threshold under TT comer is 2.193, the PDR dispersion is less than 3%, and the design requirements are met.
Example 2
The system on chip includes the power-on reset circuit as in embodiment 1.
The system on chip of the invention is provided with the power-on reset circuit of the embodiment 1, and the power-on reset circuit adopts an improved Kuijk band gap reference source structure in order to reduce the influence of the threshold voltage by the process and the temperature deviation; meanwhile, a dual-threshold voltage detection circuit with a hysteresis function is designed, so that the interference of power supply noise to circuit output is reduced, the reliability of the reset circuit is improved, the accuracy and the reliability of power-on reset of the system on chip are improved, and the dispersion of the power-on reset of the system on chip is reduced.
While specific embodiments of the invention have been described above, it will be understood by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (8)
1. A power-on-reset circuit, comprising:
a voltage comparison unit and a comparison voltage generation unit;
the output of the comparison voltage generation unit is electrically connected with the input of the voltage comparison unit;
the comparison voltage generating unit is used for generating comparison voltage and inputting the comparison voltage into the voltage comparing unit;
and the voltage comparison unit is used for receiving the comparison voltage and outputting a low level or a high level so as to complete power-on reset.
2. The power-on reset circuit of claim 1, wherein the comparison voltage generating circuit comprises a first NMOS transistor, N first diodes, M second diodes, a first resistor, a second resistor, a third resistor, a fifth resistor, and a sixth resistor;
one end of the fifth resistor is connected with a power supply, and the other end of the fifth resistor is electrically connected with one end of the second resistor and one end of the third resistor;
the other end of the second resistor is electrically connected with one end of the first resistor and the drain electrode of the first NMOS tube respectively;
n first diodes are connected in parallel;
the other end of the first resistor is electrically connected with a source electrode of the first NMOS tube;
one end of each first diode is electrically connected with the other end of the first resistor and the source electrode of the first NMOS tube;
the other end of each first diode and the third resistor are grounded;
m second diodes are connected in parallel;
one end of the sixth resistor is connected with a power supply, and the other end of the sixth resistor is electrically connected with one end of each second diode respectively;
the other end of each second diode is grounded;
the sixth resistor and the fifth resistor have the same resistance value;
the first diode and the second diode have the same parameters;
n is more than M and more than 0, and both N and M are integers.
3. The power-on reset circuit according to claim 1, wherein the comparison voltage generating circuit comprises a first NMOS transistor, N first transistors, M second transistors, a first resistor, a second resistor, a third resistor, a fifth resistor, and a sixth resistor;
one end of the fifth resistor is connected with a power supply, and the other end of the fifth resistor is electrically connected with one end of the second resistor and one end of the third resistor;
the other end of the second resistor is electrically connected with one end of the first resistor and the drain electrode of the first NMOS tube respectively;
the N first triodes are connected in parallel;
the other end of the first resistor is electrically connected with a source electrode of the first NMOS tube;
an emitting electrode of each first triode is electrically connected with the other end of the first resistor and a source electrode of the first NMOS tube;
the base electrode and the collector electrode of each first triode and the third resistor are grounded;
the M second triodes are connected in parallel;
one end of the sixth resistor is connected with a power supply, and the other end of the sixth resistor is electrically connected with the emitting electrode of each second triode respectively;
the base electrode and the collector electrode of each second triode are grounded;
the sixth resistor and the fifth resistor are the same in resistance;
the parameters of the first triode and the second triode are the same;
n is more than M and more than 0, and both N and M are integers.
4. A power-on-reset circuit as claimed in claim 2 or 3, wherein the comparison voltage generating circuit further comprises a fourth resistor;
one end of the fourth resistor is electrically connected with the other end of the sixth resistor; the other end of the fourth resistor is grounded.
5. The power-on reset circuit according to claim 4, wherein the voltage comparison circuit comprises a first PMOS transistor, a second NMOS transistor, a third NMOS transistor and a seventh resistor;
the source electrode of the first PMOS tube is connected with a power supply;
the grid electrode of the first PMOS tube is electrically connected with the grid electrode of the second PMOS tube;
the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the second NMOS tube;
the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the third NMOS tube;
the source electrode of the second PMOS tube and the source electrode of the third NMOS tube are both electrically connected with one end of the seventh resistor;
the other end of the seventh resistor is grounded.
6. The power-on-reset circuit of claim 1, further comprising a waveform shaping circuit.
7. The power-on-reset circuit of claim 6, wherein the waveform shaping circuit comprises an inverter.
8. A system on chip comprising the power-on-reset circuit of any of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211680317.5A CN115940907A (en) | 2022-12-26 | 2022-12-26 | Power-on reset circuit and system on chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211680317.5A CN115940907A (en) | 2022-12-26 | 2022-12-26 | Power-on reset circuit and system on chip |
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| Publication Number | Publication Date |
|---|---|
| CN115940907A true CN115940907A (en) | 2023-04-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211680317.5A Pending CN115940907A (en) | 2022-12-26 | 2022-12-26 | Power-on reset circuit and system on chip |
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| Country | Link |
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| CN (1) | CN115940907A (en) |
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- 2022-12-26 CN CN202211680317.5A patent/CN115940907A/en active Pending
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