CN212726971U

CN212726971U - Current comparison circuit for overvoltage protection

Info

Publication number: CN212726971U
Application number: CN202021119940.XU
Authority: CN
Inventors: 陈功; 练悦星; 肖楠; 李�浩; 张涛; 魏华; 许祎; 李蠡; 董倩宇
Original assignee: Chengdu University of Information Technology
Current assignee: Chengdu University of Information Technology
Priority date: 2020-06-16
Filing date: 2020-06-16
Publication date: 2021-03-16
Anticipated expiration: 2030-06-16

Abstract

The utility model discloses a current comparison circuit for overvoltage protection relates to IC chip technical field. The device comprises a current comparator, a reference current comparator and a voltage comparator, wherein the current comparator is used for converting a voltage input signal into a current signal, comparing the current signal with a reference current signal and outputting an initial comparison result signal; a zero temperature coefficient current source coupled to a positive input side of the current comparator for generating a reference current signal; and a hysteresis comparator for comparing the initial comparison result signal with a reference voltage signal and outputting a final comparison result signal. The reference voltage of the hysteresis comparator used by the circuit is provided by a reference voltage source and is insensitive to the process and the working temperature, so that the change of an overvoltage protection threshold value of the hysteresis comparator at different working temperatures or the influence of a process corner in the chip manufacturing process can be avoided, and the reliability of an overvoltage protection function is improved; the adoption of the hysteresis comparator can enhance the anti-interference capability, and can set an overvoltage reference voltage and restore the reference voltage.

Description

Current comparison circuit for overvoltage protection

Technical Field

The utility model relates to a IC chip technical field particularly, relates to a current comparison circuit for overvoltage protection.

Background

With the development of computer technology, multimedia technology, signal processing technology and microelectronic technology, the popularity of IC chips is increasing, which has led to great changes in the requirements of technology, structure, performance and reliability of IC chips, and has developed towards high speed, low power consumption, small volume and on-chip integration.

In the aspect of chip reliability design, the addition of an overvoltage protection module is the most important thing, once the input voltage exceeds the internal voltage limit condition of the chip, the chip is irreversibly damaged, and the service life of the chip is greatly influenced. The design of overvoltage protection modules is therefore becoming an integral part of all chips.

In a traditional comparison circuit for overvoltage protection, a Schmitt trigger is adopted in an output stage, the upper threshold voltage and the lower threshold voltage of the Schmitt trigger are determined by the threshold voltage of an MOS (metal oxide semiconductor) tube, and the threshold voltage is influenced by factors such as process temperature and the like, so that the change of the threshold voltage of the Schmitt trigger is large, and the reliability is low; in a traditional comparison circuit for overvoltage protection, a reference current generation circuit of an input stage of the comparison circuit needs to be additionally biased, the circuit is complex, and the overvoltage protection threshold value changes at different working temperatures, so that the reliability of an overvoltage protection function is low.

SUMMERY OF THE UTILITY MODEL

The utility model provides a current comparison circuit for overvoltage protection, it can alleviate above-mentioned problem.

In order to alleviate the above-mentioned problem, the utility model discloses the technical scheme who takes as follows:

a current comparison circuit for overvoltage protection, comprising:

the current comparator is used for converting the voltage input signal into a current signal, comparing the current signal with a reference current signal and outputting an initial comparison result signal;

a zero temperature coefficient current source coupled to a positive input side of the current comparator for generating a reference current signal;

and a hysteresis comparator for comparing the initial comparison result signal with a reference voltage signal and outputting a final comparison result signal.

Further, the hysteresis comparator is provided with reference voltage signal terminals Vref1, Vref2, and a final comparison result signal terminal Vout 3; the current comparator is provided with a voltage input signal terminal Vin.

Furthermore, the zero temperature coefficient current source, the current comparator and the hysteresis comparator are electrically connected to a power supply terminal VDD and a ground terminal GND.

Furthermore, the zero temperature coefficient current source comprises NMOS tubes NM 1-NM 7, PMOS tubes PM 1-PM 10, resistors R1-R5, triodes Q1-Q2 and a capacitor C1;

one end of the resistor R1, an emitter of the triode Q1, a gate of the PMOS transistor PM3 and a drain of the PMOS transistor PM1 are electrically connected; the other end of the resistor R1, the collector and the base of the triode Q1, the sources of NMOS transistors NM 1-NM 5 and NM7, the collector and the base of the triode Q2, and one ends of the resistors R4 and R5 are all connected with a ground end GND; the source electrodes of the PMOS tubes PM1, PM2, PM 5-PM 8 and PM10 are all electrically connected with a power supply end VDD; the grid electrodes of the PMOS tubes PM1, PM2, PM 5-PM 7 and PM10, the drain electrode of the PMOS tube PM5, one end of the capacitor C1 and the drain electrodes of the NMOS tubes NM3 and NM5 are electrically connected and are used as bias voltage ends of the zero temperature coefficient current source; the drain electrode of the PMOS pipe PM2, the source electrode of the PM3 and the source electrode of the PM4 are electrically connected; the drain electrode of the PMOS pipe PM3, the grid electrode of the NMOS pipe NM2 and the drain electrode and the grid electrode of the NMOS pipe NM1 are electrically connected; the drain electrode of the PMOS tube PM4, the drain electrode of the NMOS tube NM2, one end of the resistor R2 and the gate electrode of the NMOS tube NM3 are electrically connected; the other end of the resistor R2 is electrically connected to the other end of the capacitor C1; the grid electrode of the PMOS pipe PM4, the drain electrode of the PMOS pipe PM6, one end of the resistor R3 and the other end of the resistor R4 are electrically connected; the other end of the resistor R5, the drain of the PMOS tube PM7 and the gate of the NMOS tube NM4 are electrically connected; the source electrode of the PMOS pipe PM9 is electrically connected with the grid electrode and the drain electrode of the PMOS pipe PM 8; the grid and the drain of the PMOS tube PM9, the drain of the NMOS tube NM4 and the grid of the NMOS tube NM5 are electrically connected; the drain electrode of the PMOS pipe PM10 is electrically connected with the drain electrode and the grid electrode of the NMOS pipe NM6 and is used as a first reference current signal end of the zero temperature coefficient current source; the source of the NMOS transistor NM6 is electrically connected to the drain and the gate of the NMOS transistor NM7, and serves as a second reference current signal terminal of the zero temperature coefficient current source.

Further, the current comparator comprises a PMOS transistor PM11, an NMOS transistor NM8, an NMOS transistor NM9, and a capacitor C2;

the grid electrode of the PMOS pipe PM11 is electrically connected with a voltage input signal end Vin; the source electrode of the PMOS pipe PM11 is electrically connected with a power supply end VDD; the grid electrode of the NMOS tube NM8 is used as a first positive input end of the current comparator and is electrically connected with a first reference current signal end of the zero temperature coefficient current source; the grid electrode of the NMOS tube NM9 is used as a second positive input end of the current comparator and is electrically connected with a second reference current signal end of the zero temperature coefficient current source; the source electrode of the NMOS tube NM8 is electrically connected with the drain electrode of the NMOS tube NM 9; the source of the NMOS transistor NM9 and one end of the capacitor C2 are both connected to the ground GND; the drain of the PMOS transistor PM11 is electrically connected to the drain of the NMOS transistor NM8 and the other end of the capacitor C2, and serves as an initial comparison result signal terminal Vout1 of the current comparator.

Furthermore, the hysteresis comparator comprises PMOS tubes PM 12-PM 17, NMOS tubes NM 10-NM 16, a resistor R6 and a capacitor C3;

the source electrodes of the PMOS tubes PM12 and PM 15-PM 17 are electrically connected with a power supply end VDD; the gates of the PMOS tubes PM12 and PM15 are electrically connected with a bias voltage end of the zero temperature coefficient current source; the drain electrode of the PMOS pipe PM12, the source electrode of the PMOS pipe PM13 and the source electrode of the PMOS pipe PM14 are electrically connected; the grid electrode of the PMOS pipe PM13 is electrically connected with an initial comparison result signal end Vout1 of the current comparator; the drain electrode of the PMOS pipe PM13, the grid electrode of the NMOS pipe NM11 and the drain electrode and the grid electrode of the NMOS pipe NM10 are electrically connected; the sources of the NMOS tubes NM10, NM11, NM14, NM15 and NM16 are all connected with a ground terminal GND; the drain of the NMOS transistor NM11, the gate of the NMOS transistor NM14, one end of the resistor R6 and the drain of the PMOS transistor PM14 are electrically connected; the grid electrode of the PMOS pipe PM14 and the drain electrodes of the NMOS pipes NM13 and NM12 are electrically connected; the other end of the resistor R6 is electrically connected to one end of the capacitor C3; the other end of the capacitor C3, the drain of the NMOS transistor NM14, the drain of the PMOS transistor PM15, the gate of the PMOS transistor PM16 and the gate of the NMOS transistor NM15 are electrically connected; the drain electrode of the NMOS tube NM15, the drain electrode of the PMOS tube PM16, the gate electrode of the NMOS tube NM12, the gate electrode of the PMOS tube PM17 and the gate electrode of the NMOS tube NM16 are electrically connected; the sources of the NMOS transistors NM12 and NM13 are respectively used as a first reference voltage signal terminal Vref1 and a second reference voltage signal terminal Vref 2; the gate of the NMOS transistor NM13, the drain of the PMOS transistor PM17, and the drain of the NMOS transistor NM16 are electrically connected and serve as a final comparison result signal terminal Vout3 of the hysteresis comparator.

Furthermore, the substrates of the PMOS transistors PM1 to PM17 are all electrically connected to a power supply terminal VDD, and the substrates of the NMOS transistors NM1 to NM16 are all electrically connected to a ground terminal GND.

Furthermore, the PMOS transistors PM 1-PM 17 and the NMOS transistors NM 1-NM 16 both adopt transistors with 3.3V standard threshold values; the resistors R1-R6 are all high-resistance polysilicon resistors; the capacitors C1-C3 are all metal capacitors; the triodes Q1-Q2 all adopt a 3.3V standard PNP triode.

Further, resistors R1 and R4 are equal in resistance, and transistors Q1 and Q2 each select a 5 × 5 emitter size.

Compared with the prior art, the beneficial effects of the utility model reside in that:

1) the reference voltage of the hysteresis comparator used by the output stage is provided by a reference voltage source and is insensitive to the process and the working temperature, so that the change of an overvoltage protection threshold value of the hysteresis comparator at different working temperatures or the influence of a process corner in the chip manufacturing process can be avoided, and the reliability of the overvoltage protection function is improved;

2) the output stage adopts a hysteresis comparator, so that the anti-interference capability can be enhanced, and overvoltage reference voltage and recovery reference voltage can be set, so that the utility model can identify the working state of the system in real time and has a self-recovery function;

3) the zero-temperature-coefficient current source adopted by the input stage is of a self-biasing structure, does not need additional biasing, can provide bias voltage and current for the current comparator module and the hysteresis comparator module, realizes function multiplexing, reduces design complexity and can prevent a circuit from entering a degenerate state;

4) the comparison current input and referenced by the adopted current comparator is provided by a zero-temperature coefficient current source, and the zero-temperature coefficient current source can generate the zero-temperature coefficient current, so that the change of an overvoltage protection threshold value of the current comparator at different working temperatures can be avoided, and the reliability of an overvoltage protection function is improved;

5) the current comparison circuit adopts a PMOS tube as an input end, so that the module can be closed when the system is judged to be in an overvoltage state, and the power consumption is reduced.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a block diagram of a current comparison circuit according to an embodiment of the present invention;

fig. 2 is a specific structure diagram of a current comparison circuit according to an embodiment of the present invention;

fig. 3 is a graph showing a zero temperature coefficient current simulation curve provided by an embodiment of the present invention;

fig. 4 is a simulation graph of input voltage and output voltage of the current comparator according to the embodiment of the present invention;

fig. 5 is a schematic diagram illustrating an operation process of a current comparison circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1 and 2, an embodiment of the present invention provides a current comparison circuit for overvoltage protection, including a zero temperature coefficient current source, a current comparator, and a hysteresis comparator.

The zero temperature coefficient current source is coupled to the positive input side of the current comparator and used for generating a reference current signal. The zero temperature coefficient current source comprises NMOS transistors NM 1-NM 7, PMOS transistors PM 1-PM 10, resistors R1-R5, triodes Q1-Q2 and a capacitor C1.

One end of the resistor R1, an emitter of the triode Q1, a gate of the PMOS transistor PM3 and a drain of the PMOS transistor PM1 are electrically connected; the other end of the resistor R1, the collector and the base of the triode Q1, the sources of NMOS transistors NM 1-NM 5 and NM7, the collector and the base of the triode Q2, and one ends of the resistors R4 and R5 are all connected with a ground end GND; the source electrodes of the PMOS tubes PM1, PM2, PM 5-PM 8 and PM10 are all electrically connected with a power supply end VDD; the grid electrodes of the PMOS tubes PM1, PM2, PM 5-PM 7 and PM10, the drain electrode of the PMOS tube PM5, one end of the capacitor C1 and the drain electrodes of the NMOS tubes NM3 and NM5 are electrically connected and are used as bias voltage ends of a zero temperature coefficient current source; the drain electrode of the PMOS pipe PM2, the source electrode of the PM3 and the source electrode of the PM4 are electrically connected; the drain electrode of the PMOS pipe PM3, the grid electrode of the NMOS pipe NM2 and the drain electrode and the grid electrode of the NMOS pipe NM1 are electrically connected; the drain electrode of the PMOS tube PM4, the drain electrode of the NMOS tube NM2, one end of the resistor R2 and the gate electrode of the NMOS tube NM3 are electrically connected; the other end of the resistor R2 is electrically connected to the other end of the capacitor C1; the grid electrode of the PMOS pipe PM4, the drain electrode of the PMOS pipe PM6, one end of the resistor R3 and the other end of the resistor R4 are electrically connected; the other end of the resistor R5, the drain of the PMOS tube PM7 and the gate of the NMOS tube NM4 are electrically connected; the source electrode of the PMOS pipe PM9 is electrically connected with the grid electrode and the drain electrode of the PMOS pipe PM 8; the grid and the drain of the PMOS tube PM9, the drain of the NMOS tube NM4 and the grid of the NMOS tube NM5 are electrically connected; the drain electrode of the PMOS pipe PM10 is electrically connected with the drain electrode and the grid electrode of the NMOS pipe NM6 and is used as a first reference current signal end of the zero temperature coefficient current source; the source of the NMOS transistor NM6 is electrically connected to the drain and the gate of the NMOS transistor NM7, and serves as a second reference current signal terminal of the zero temperature coefficient current source.

The current comparator is used for converting the voltage input signal into a current signal, comparing the current signal with a reference current signal and outputting an initial comparison result signal. The current comparator comprises a PMOS tube PM11, an NMOS tube NM8, an NMOS tube NM9 and a capacitor C2.

The hysteresis comparator is used for comparing the initial comparison result signal with the reference voltage signal and outputting a final comparison result signal. The hysteresis comparator comprises PMOS tubes PM 12-PM 17, NMOS tubes NM 10-NM 16, a resistor R6 and a capacitor C3;

the source electrodes of the PMOS tubes PM12 and PM 15-PM 17 are electrically connected with a power supply end VDD; the gates of the PMOS tubes PM12 and PM15 are electrically connected with a bias voltage end of a zero temperature coefficient current source; the drain electrode of the PMOS pipe PM12, the source electrode of the PMOS pipe PM13 and the source electrode of the PMOS pipe PM14 are electrically connected; the gate of the PMOS transistor PM13 is electrically connected with the initial comparison result signal terminal Vout1 of the current comparator; the drain electrode of the PMOS pipe PM13, the grid electrode of the NMOS pipe NM11 and the drain electrode and the grid electrode of the NMOS pipe NM10 are electrically connected; the sources of the NMOS tubes NM10, NM11, NM14, NM15 and NM16 are all connected with a ground terminal GND; the drain of the NMOS transistor NM11, the gate of the NMOS transistor NM14, one end of the resistor R6 and the drain of the PMOS transistor PM14 are electrically connected; the grid electrode of the PMOS pipe PM14 and the drain electrodes of the NMOS pipes NM13 and NM12 are electrically connected; the other end of the resistor R6 is electrically connected to one end of the capacitor C3; the other end of the capacitor C3, the drain of the NMOS transistor NM14, the drain of the PMOS transistor PM15, the gate of the PMOS transistor PM16 and the gate of the NMOS transistor NM15 are electrically connected; the drain electrode of the NMOS tube NM15, the drain electrode of the PMOS tube PM16, the gate electrode of the NMOS tube NM12, the gate electrode of the PMOS tube PM17 and the gate electrode of the NMOS tube NM16 are electrically connected; the sources of the NMOS transistors NM12 and NM13 are respectively used as a first reference voltage signal terminal Vref1 and a second reference voltage signal terminal Vref 2; the gate of the NMOS transistor NM13, the drain of the PMOS transistor PM17, and the drain of the NMOS transistor NM16 are electrically connected and serve as the final comparison result signal terminal Vout3 of the hysteresis comparator.

In the embodiment, the substrates of the PMOS transistors PM1 to PM17 are all electrically connected to the power supply terminal VDD, and the substrates of the NMOS transistors NM1 to NM16 are all electrically connected to the ground terminal GND.

In this embodiment, the MOS transistors are designed by adopting an SMIC 0.13um CMOS process, the designed PMOS transistors PM1 to PM17 all adopt 3.3V standard threshold PMOS transistors of the process, the NMOS transistors NM1 to NM16 all adopt 3.3V standard threshold NMOS transistors, the resistors R1 to R6 all adopt high-resistance polysilicon resistors, the capacitors C1 to C3 all adopt metal capacitors, and the triodes Q1 to Q2 all adopt 3.3V standard PNP triodes. The resistors R1 and R4 have the same resistance value, so that current can be accurately copied by a current source, the ratio of the number of the triodes Q1 to Q2 is 1:8 (note: the triode Q2 is formed by connecting 8 identical PNP triodes in parallel), so that positive temperature coefficient voltage can be obtained, layout matching design is facilitated, and the sizes of emitting electrodes of the triodes Q1 and Q2 are 5 multiplied by 5, so that base emitting electrode voltage V and emitting electrode voltage V with proper negative temperature coefficient can be obtained_be。

The embodiment of the utility model provides a current comparison circuit's theory of operation as follows:

the zero temperature coefficient current generation principle is as follows:

as shown in FIG. 3, PMOS transistors PM 2-PM 5 and NMOS transistors NM 1-NM 3 constitute a two-stage amplifier, and NMOS transistors NM1 and NM2 are two input ends of the amplifier, so that there are

V_in1＝V_in2

And due to the fact that

V_in1＝V_be1

V_in2＝I₂×R₃+V_be2

The current I2 can be obtained as follows, since the quantity ratio of Q1 to Q2 is 1:8

The current I3 has the relationship:

therefore, the current I1 flowing through the PMOS transistor PM6 is:

due to DeltaV_beHaving a positive temperature coefficient, of_beHas a negative temperature coefficient, and if a zero temperature coefficient current is to be obtained, the following relation is required:

therefore, the resistance values of the resistors R3 and R4 are properly adjusted to enable the positive temperature coefficient and the negative temperature coefficient to mutually offset, and the current I1 with the zero temperature coefficient is obtained.

The circuit start principle is as follows:

when the zero temperature coefficient current source is in a degenerate state, namely an EN signal is 0, the grid voltage of an NMOS tube NM4 is zero, an NMOS tube NM4 is in an off state, the drain of the NMOS tube NM4 is pulled up to a power supply voltage VDD, the drain of the NMOS tube NM4 is connected with the grid of an NMOS tube NM5, the NMOS tube NM5 is in an on state, the grids of PMOS tubes PM 1-PM 7 are pulled down to the ground end, the PMOS tubes PM 1-PM 7 are in a working state, the bias of an amplifier, namely the PMOS tube PM2 starts working, and finally the system exits the degenerate state.

When the PMOS transistors PM1 to PM7 are in the operating state, the current of the PMOS transistor PM7 gradually rises along with the gradual establishment of the operating state, and the voltage drop generated across the resistor R5 gradually increases, so that the gate voltage of the NMOS transistor NM4 gradually rises. When the gate voltage of the NMOS transistor NM4 is greater than its turn-on threshold, the NMOS transistor NM4 is in a turn-on state, and eventually the gate voltage of the NMOS transistor NM5 is dropped to zero, so that the NMOS transistor NM5 is in a turn-off state, and the start-up circuit is turned off.

The current comparator works according to the following principle:

as shown in fig. 2, NMOS transistors NM6, NM7, NM8, and NM9 are a set of cascode current mirrors, the width-to-length ratio of NMOS transistors NM7 and NM9 is N:1, and when the input fixed bias current is I5:

since the input voltage is connected with the gate of the PMOS transistor PM11, the current of the I4 decreases with the increase of the input voltage, when the difference between the input voltage and the power voltage VDD is smaller than the threshold of the PMOS transistor PM11, the PMOS transistor PM11 is turned off, and at this time, the power supply to the ground of the current comparator is turned off, and the working current is almost zero.

Therefore, the maximum current of the current comparator structure during working is I4, and the working current is gradually reduced until the current is finally turned off along with the increase of the input voltage, so that the working current of the current comparator can be adjusted by adjusting the width-to-length ratio of the current mirror, and the power consumption can be effectively reduced.

When the current comparator is in a normal working state:

I7＝I4-I6

since the bias current I5 is a fixed value, the mirror current I6 is also a fixed magnitude current. Therefore, the magnitude of the current I7 changes with the change of the current I4.

The capacitor C2 mainly has charge storage and discharge functions, the capacitor can compare and convert current into a voltage signal, the voltage signal is identified and shaped by the hysteresis comparator, and finally a judgment signal of an overvoltage state is output.

The dynamic comparison principle of the current comparator is as follows:

when the current I4 is greater than I6 (Vin is much smaller than VDD at this time, Vin is in a normal state), the current I7 is positive, that is, the current flowing into the PMOS transistor PM11 is shunted by the branch of the NMOS transistor NM8 and the branch of the capacitor C2, the input current exists in the capacitor C2, so that the capacitor C2 starts to charge and the voltage across the capacitor C2 starts to rise, and finally the voltage across the capacitor C2 is equal to the power voltage VDD.

When the current I4 is less than I6 (at this time, the difference between Vin and VDD is close to or smaller than the turn-on threshold of the PMOS transistor PM11, Vin is in an overvoltage state), the current I7 is negative, that is, the current flowing into the PMOS transistor PM11 is completely injected into the branch of the NMOS transistor NM8, but the current required by the branch of the NMOS transistor NM8 is still not satisfied, so the capacitor C2 starts to discharge, the current flows from the capacitor C2 to the NMOS transistor NM8, the voltage across the capacitor C2 starts to drop, and finally the voltage across the capacitor C2 is zero.

When the current I4 is equal to I6 (at this time, the corresponding Vin value is an overvoltage determination condition), the current I7 is 0, the current provided by the PMOS transistor PM11 just meets the current required by the branch where the NMOS transistor NM8 is located, the capacitor C2 has neither input current nor output current, and the voltage across the capacitor C2 remains unchanged at this time.

Namely:

I4＝I6

at this time, the critical condition that Vin is determined as overvoltage is recorded as V_OVPWhen the input voltage is greater than V_OVPAnd when the voltage is over-voltage, the judgment circuit is in an over-voltage state.

Therefore, the overvoltage judgment voltage V can be set through the width-length ratio of the PMOS transistor PM11, the width-length ratio of the NMOS transistors NM7 and NM9 and the magnitude of the input current I5_OVP。

When an input signal is very close to a critical point of overvoltage judgment, the digital signal comparator is easy to generate misjudgment, and in order to increase the detection accuracy and avoid the cyclic jump of a system output signal caused by the fact that the system is in an overvoltage critical state, a hysteresis comparator is introduced. The size of a hysteresis window of the hysteresis comparator can be adjusted through the reference voltages Vref1 and Vref2, so that misjudgment of overvoltage detection at a critical point is avoided, and the anti-interference capability of the structure is improved.

The specific principle is as follows: the initial state of the input voltage is zero, the PMOS transistor PM11 is in a fully on state, the voltage across the capacitor C2 is equal to the power supply voltage VDD, that is, the negative input terminal of the initial hysteresis comparator is the power supply voltage VDD, Vout1 outputs a high level, Vout2 outputs a high level, Vout3 outputs a low level, and at this time, the NMOS transistor NM12 is in an on state NM13, that is, the initial state is Vout1 and Vref1 for comparison.

When Vin gradually rises, the output Vout1 of the current comparator falls to a low level, Vout2 outputs a low level, Vout3 outputs a high level, and at this time, the NMOS transistor NM12 is in an off state NM13 is in an on state, i.e., Vout1 and Vref2 are initially compared. Therefore, the hysteresis comparison function is realized by using the reference voltages Vref1 and Vref2 as the upper and lower thresholds of the output of the current comparator.

On the other hand, the utility model discloses a reference voltage of hysteresis comparator upper and lower threshold is provided by reference voltage source, compares in traditional schmitt trigger, and is lower to temperature sensitivity, can guarantee the stability of threshold value under different operating temperature, makes this structure have higher reliability.

Meanwhile, the hysteresis window can be introduced to bring the self-recovery function into the structure when the input voltage is reduced to V_NOVPWhen the voltage is lower than the voltage, the system can judge that the overvoltage state is relieved, the system can restore the normal working state without additionally adding a special structure, and the complexity of the design is reduced to a great extent.

The principle analysis of the working process of the current comparator is carried out in combination with the figure 5:

according to the time and voltage curve of the input voltage Vin, when Vin gradually rises, the gate voltage of the PMOS transistor PM11 in the current comparator gradually rises, and the conduction capability thereof gradually falls, so that the voltage Vout1 continuously falls; when Vin rises to V_OVPWhen the voltage of Vout1 drops to Vref1, the hysteretic comparator output signal Vout3 flips and outputs a high level (VDD), which determines that the system is in an overvoltage state.

When Vin drops again, the voltage of the gate of the PMOS transistor PM11 in the current comparator gradually decreases, and the PMOS transistor PM11 is turned onThe capability is gradually enhanced, resulting in the voltage Vout1 continuously rising, when Vin falls to V_NOVPAt this time, Vout1 rises to Vref2, at which time the hysteresis comparator output signal Vout3 flips and outputs a low level (0), at which time the system is determined to exit the overvoltage state.

The embodiment of the utility model provides an adopt SMIC 0.13um CMOS technology to design and emulation current comparison circuit's precision, figure 3 shows zero temperature coefficient current source output current simulation graph, I5 electric current in the corresponding current comparator structure chart of output current in the picture, can see, in-20 ℃ -125 ℃ operating temperature, output current variation range is 3.98652uA ~ 4.037884uA, the temperature coefficient only has 176ppm, and traditional current comparator input reference current does not carry out temperature compensation, the temperature coefficient is usually more than 2000 ppm. Fig. 4 is a waveform diagram of the input voltage Vin and the voltage at the output terminal Vout3 at-20 ℃, 27 ℃ and 125 ℃, respectively, and the simulation result shows that after the input reference current is compared by using a zero-temperature coefficient current source, the maximum difference of the overvoltage comparison threshold at different working temperatures is 78.4466mV, and the maximum difference of the overvoltage protection threshold at the exit is 55.83mV, whereas the comparison threshold difference of the traditional current comparator at different working temperatures is usually more than 400mV, and the simulation result shows that the above measures improve the accuracy and reliability effectiveness of the current comparator.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A current comparison circuit for overvoltage protection, comprising:

2. The over-voltage protection current comparison circuit according to claim 1, wherein the hysteresis comparator is provided with reference voltage signal terminals Vref1, Vref2, and a final comparison result signal terminal Vout 3; the current comparator is provided with a voltage input signal terminal Vin.

3. The current comparison circuit for overvoltage protection according to claim 2, wherein the zero temperature coefficient current source, the current comparator and the hysteresis comparator are electrically connected to a power supply terminal VDD and a ground terminal GND.

4. The overvoltage protection current comparison circuit according to claim 3, wherein the zero temperature coefficient current source includes NMOS transistors NM 1-NM 7, PMOS transistors PM 1-PM 10, resistors R1-R5, triodes Q1-Q2, and a capacitor C1;

5. The overvoltage protection current comparison circuit according to claim 4, wherein the current comparator includes a PMOS transistor PM11, an NMOS transistor NM8, an NMOS transistor NM9, and a capacitor C2;

6. The current comparison circuit for overvoltage protection according to claim 5, wherein the hysteresis comparator includes PMOS transistors PM12 to PM17, NMOS transistors NM10 to NM16, a resistor R6, and a capacitor C3;

7. The over-voltage protection current comparison circuit according to claim 6, wherein the substrates of the PMOS transistors PM1 to PM17 are electrically connected to a power supply terminal VDD, and the substrates of the NMOS transistors NM1 to NM16 are electrically connected to a ground terminal GND.

8. The current comparison circuit for overvoltage protection according to claim 7, wherein the PMOS transistors PM1 to PM17 and the NMOS transistors NM1 to NM16 each employ a transistor of 3.3V standard threshold; the resistors R1-R6 are all high-resistance polysilicon resistors; the capacitors C1-C3 are all metal capacitors; the triodes Q1-Q2 all adopt a 3.3V standard PNP triode.