CN116301173A - Low-temperature drift voltage reference circuit - Google Patents

Abstract

The invention discloses a low-temperature drift voltage reference circuit, which comprises: the power supply comprises a starting circuit, a voltage bias circuit, a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit and a zero temperature coefficient voltage generating circuit; the starting circuit is used for starting the low-temperature drift voltage reference circuit; the voltage bias circuit is used for generating a bias voltage; the positive temperature coefficient current generating circuit is used for generating positive temperature current; the negative temperature coefficient current generating circuit is used for generating a negative temperature current; the zero temperature coefficient voltage generating circuit is used for generating zero temperature voltage; the starting circuit, the voltage bias circuit, the positive temperature coefficient current generating circuit, the negative temperature coefficient current generating circuit and the zero temperature coefficient voltage generating circuit are sequentially connected. The low-temperature drift voltage reference circuit provided by the invention has the advantages of high precision and high stability, and is not influenced by temperature and power supply voltage.

Description

Low-temperature drift voltage reference circuit

Technical Field

The invention belongs to the field of semiconductor integrated circuit design, and particularly relates to a low-temperature drift voltage reference circuit.

Background

Existing power supply type chips or analog-to-digital converter chips and clock chips, voltage references are susceptible to environmental effects such as temperature and supply voltage. The traditional voltage reference circuit only has first-order compensation, and only uses a standard current source in the process of mirror current, so that the generated reference voltage has larger interference with temperature and fluctuation of a power supply.

Disclosure of Invention

The invention provides a low-temperature drift voltage reference circuit which solves the technical problems and adopts the following technical scheme:

a low temperature drift voltage reference circuit, comprising: the power supply comprises a starting circuit, a voltage bias circuit, a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit and a zero temperature coefficient voltage generating circuit;

the starting circuit is used for starting the low-temperature drift voltage reference circuit;

the voltage bias circuit is used for generating a bias voltage;

the positive temperature coefficient current generating circuit is used for generating positive temperature current;

the negative temperature coefficient current generating circuit is used for generating negative temperature current;

the zero temperature coefficient voltage generation circuit is used for generating zero temperature voltage;

the starting circuit, the voltage bias circuit, the positive temperature coefficient current generation circuit, the negative temperature coefficient current generation circuit and the zero temperature coefficient voltage generation circuit are sequentially connected.

Further, the starting circuit comprises a resistor R1, an N-type MOS tube NM1, a P-type MOS tube PM1, an N-type MOS tube NM2 and a P-type MOS tube PM16;

the upper port of the resistor R1 is connected with a power supply, the lower port of the resistor R1 is connected with the drain electrode of the N-type MOS tube NM1, the source electrode of the N-type MOS tube NM1 is connected with the ground, the grid electrode is connected with the output voltage VREF, the source electrode of the P-type MOS tube PM1 is connected with the power supply, the drain electrode is connected with the drain electrode of the N-type MOS tube NM2 and the grid electrode of the P-type MOS tube PM16, the grid electrode is connected with the grid electrode of the N-type MOS tube NM2 and the drain electrode of the N-type MOS tube NM1, the source electrode of the N-type MOS tube NM2 is connected with the ground, and the source electrode of the P-type MOS tube PM16 is connected with the power supply.

Further, the voltage bias circuit includes: p-type MOS tube PM2, P-type MOS tube PM3, P-type MOS tube PM4, P-type MOS tube PM5, N-type MOS tube NM3, N-type MOS tube NM4, PNP-type triode Q1 and PNP-type triode Q2;

the source electrode and the power supply of P type MOS pipe PM2 are connected, the drain electrode with the source electrode of P type MOS pipe PM3 is connected, the grid electrode with the drain electrode of P type MOS pipe PM3 with the drain electrode of N type MOS pipe NM3 is connected, the grid electrode of P type MOS pipe PM3 with the grid electrode of P type MOS pipe PM4 and the grid electrode of P type MOS pipe PM5 are connected, the source electrode and the power supply of P type MOS pipe PM4 are connected, the drain electrode of P type MOS pipe PM5 with the drain electrode of N type MOS pipe NM4 is connected, the source electrode of N type MOS pipe NM3 with the emitter electrode of PNP type triode NM4 is connected, the source electrode and the emitter electrode of PNP type triode Q2 are connected, the base electrode and the collector electrode of PNP type MOS pipe Q1 are connected with the ground, the base electrode and the collector electrode of PNP type MOS pipe Q2 are connected with the ground, the drain electrode of N type MOS pipe NM3 and the drain electrode of N type MOS pipe NM4 are connected with the drain electrode of P type MOS pipe NM 4.

Further, the positive temperature coefficient current generating circuit comprises a P-type MOS tube PM6, a P-type MOS tube PM7, a P-type MOS tube PM8, a P-type MOS tube PM9, an N-type MOS tube NM5, an N-type MOS tube NM6, a resistor R2, a PNP-type triode Q3 and a PNP-type triode Q4;

the source and the power supply of P type MOS pipe PM6 are connected, the drain electrode with the source of P type MOS pipe PM7 is connected, the source and the power supply of P type MOS pipe PM8 are connected, the drain electrode with the source of P type MOS pipe PM9 is connected, the drain electrode of P type MOS pipe PM7 with the drain electrode of N type MOS pipe NM5 is connected, the drain electrode of P type MOS pipe PM9 with N type MOS pipe NM5 grid electrode, N type MOS pipe NM6 grid electrode and drain electrode, N type MOS pipe NM 5's source electrode with PNP type triode Q3's projecting electrode is connected, N type MOS pipe NM 6's source electrode with resistance R2's upper end is connected, PNP type triode Q3's base and collector are connected with ground, resistance R2's lower extreme with PNP type triode Q4's projecting electrode is connected, P type MOS pipe PM6 grid electrode with P type MOS pipe PM8 grid electrode with P type MOS pipe PM2 grid electrode and P type MOS pipe PM3 grid electrode is connected with P type MOS pipe PM3 grid electrode and P type MOS pipe PM 3.

Further, the negative temperature coefficient current generating circuit comprises a P-type MOS tube PM10, a P-type MOS tube PM11, an N-type MOS tube NM7 and a resistor R3;

the source electrode and the power supply of P type MOS pipe PM10 are connected, the drain electrode with the drain electrode of P type MOS pipe PM11 and the drain electrode of N type MOS pipe NM7 are connected, the drain electrode of P type MOS pipe PM11 with the drain electrode of N type MOS pipe NM7 is connected, the source electrode of N type MOS pipe NM7 with the upper end of resistance R3 is connected, the lower extreme of resistance R3 is connected with ground, the grid of N type MOS pipe NM7 with the drain electrode of P type MOS pipe PM9 is connected, the grid of P type MOS pipe PM11 with the grid of P type MOS pipe PM3 is connected.

Further, the zero temperature coefficient voltage generating circuit comprises a P-type MOS tube PM12, a P-type MOS tube PM13, a P-type MOS tube PM14, a P-type MOS tube PM15, a resistor R4 and a PNP triode Q5;

the source electrode and the power supply of P type MOS pipe PM12 are connected, the drain electrode is connected with the source electrode of P type MOS pipe PM13, the drain electrode of P type MOS pipe PM13 with the drain electrode of P type MOS pipe PM15 with the upper end of resistance R4 and the grid of N type MOS pipe NM1 is connected, the source electrode of P type MOS pipe PM14 is connected with the power supply, the drain electrode is connected with the source electrode of P type MOS pipe PM15, the source electrode of P type MOS pipe PM15 is connected with the drain electrode of P type MOS pipe PM14, the lower extreme of resistance R4 with the emitter of PNP type triode Q5 is connected, the base and collector of PNP type triode Q4 are connected with ground, the grid of P type MOS pipe PM14 is connected with the grid of P type MOS pipe PM2, the grid of P type MOS pipe PM13 with the grid of P type MOS pipe PM15 is connected with the grid of P type MOS pipe PM 3.

The low-temperature drift voltage reference circuit has the advantages of being high in precision and stability and free from being influenced by temperature and power supply voltage.

The low-temperature drift voltage reference circuit provided by the invention has the advantages that the P-type MOS tube PM6, the P-type MOS tube PM7, the P-type MOS tube PM8 and the P-type MOS tube PM9 are all co-source and co-gate current sources, compared with the traditional current sources, the influence of a power supply on drain voltages of the N-type MOS tube NM5 and the N-type MOS tube NM6 can be effectively reduced, and more accurate positive temperature current can be obtained.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a schematic diagram of a low temperature drift voltage reference circuit according to the present invention.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present application and are not to be construed as limiting the present application.

In the description of the present application, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

In this application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

The application discloses low temperature drift voltage reference circuit mainly contains: the power supply comprises a starting circuit, a voltage bias circuit, a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit and a zero temperature coefficient voltage generating circuit. The starting circuit is used for starting the low-temperature drift voltage reference circuit. The voltage bias circuit is used for generating a bias voltage. The positive temperature coefficient current generating circuit is used for generating positive temperature current. The negative temperature coefficient current generating circuit is used for generating a negative temperature current. The zero temperature coefficient voltage generating circuit is used for generating zero temperature voltage. The starting circuit, the voltage bias circuit, the positive temperature coefficient current generating circuit, the negative temperature coefficient current generating circuit and the zero temperature coefficient voltage generating circuit are sequentially connected. The low temperature drift voltage reference circuit of the present application is specifically described below with reference to fig. 1.

As shown in fig. 1, as a preferred embodiment, the start-up circuit includes a resistor R1, an N-type MOS transistor NM1, a P-type MOS transistor PM1, an N-type MOS transistor NM2, and a P-type MOS transistor PM16.

The upper port of the resistor R1 is connected with a power supply, the lower port is connected with the drain electrode of the N-type MOS tube NM1, the source electrode of the N-type MOS tube NM1 is connected with the ground, the grid electrode is connected with the output voltage VREF, the source electrode of the P-type MOS tube PM1 is connected with the power supply, the drain electrode of the N-type MOS tube NM2 and the grid electrode of the P-type MOS tube PM16 are connected, the grid electrode is connected with the grid electrode of the N-type MOS tube NM2 and the drain electrode of the N-type MOS tube NM1, the source electrode of the N-type MOS tube NM2 is connected with the ground, and the source electrode of the P-type MOS tube PM16 is connected with the power supply.

The power supply voltage charges the grid capacitors of the P-type MOS tube PM1 and the N-type MOS tube NM2 through the resistor R1 until the N-type MOS tube NM2 is turned on and the P-type MOS tube PM1 is turned off, and the grid end voltage of the P-type MOS tube PM16 is 0V. P-type MOS tube PM16 is turned on to inject leakage current into gate ends of N-type MOS tube NM3 and N-type MOS tube NM4 until VREF output voltage is 1.25V reference voltage, and VREF output voltage is connected with gate electrodes of N-type MOS tube NM 1. The 1.25V voltage is applied to the grid electrode of the N-type MOS tube NM1, at the moment, the N-type MOS tube NM1 is started to generate leakage current to charge the grid electrode capacitors of the P-type MOS tube PM1 and the N-type MOS tube NM2 until the N-type MOS tube NM2 is turned off, the P-type MOS tube PM1 is turned on, at the moment, the grid end voltage of the P-type MOS tube PM6 is 3.3V, and the P-type MOS tube PM6 is turned off without leakage current.

As a preferred embodiment, the voltage bias circuit includes: p-type MOS tube PM2, P-type MOS tube PM3, P-type MOS tube PM4, P-type MOS tube PM5, N-type MOS tube NM3, N-type MOS tube NM4, PNP-type triode Q1 and PNP-type triode Q2.

The source electrode and the power supply of the P-type MOS tube PM2 are connected, the drain electrode and the source electrode of the P-type MOS tube PM3 are connected, the drain electrode of the grid electrode and the P-type MOS tube PM3 are connected with the drain electrode of the N-type MOS tube NM3, the grid electrode of the P-type MOS tube PM3 is connected with the grid electrode of the P-type MOS tube PM4 and the grid electrode of the P-type MOS tube PM5, the source electrode of the P-type MOS tube PM4 is connected with the source electrode of the P-type MOS tube PM5, the drain electrode of the P-type MOS tube PM5 is connected with the drain electrode of the N-type MOS tube NM4, the source electrode of the N-type MOS tube NM3 is connected with the emitter electrode of the PNP-type transistor Q1, the base electrode and the collector electrode of the PNP-type MOS tube Q1 are connected with the ground, the base electrode and the collector electrode of the PNP-type MOS tube Q2 are connected with the ground, and the grid electrode of the N-type MOS tube NM3 and the grid electrode of the N-type MOS tube NM4 are connected with the drain electrode of the P-type MOS tube PM16.

After the circuit is started, the connection relation of the P-type MOS tube PM4 and the P-type MOS tube PM5 is that the diode connection can be equivalent to resistance. Bias voltage V2 is generated by utilizing the partial pressure among the power supply voltage P-type MOS tube PM4, the P-type MOS tube PM5, the N-type MOS tube NM4 and the PNP-type triode Q2, bias voltage V1 is generated by utilizing the partial pressure among the power supply voltage P-type MOS tube PM2, the P-type MOS tube PM3, the N-type MOS tube NM3 and the PNP-type triode Q1, and bias point voltage is drain voltage among the P-type MOS tube PM3 and the N-type MOS tube NM 2.

As a preferred embodiment, the ptc-current generating circuit comprises a P-type MOS transistor PM6, a P-type MOS transistor PM7, a P-type MOS transistor PM8, a P-type MOS transistor PM9, an N-type MOS transistor NM5, an N-type MOS transistor NM6, a resistor R2, a PNP transistor Q3, and a PNP transistor Q4.

The source electrode and the power supply of the P-type MOS tube PM6 are connected, the drain electrode is connected with the source electrode of the P-type MOS tube PM7, the source electrode and the power supply of the P-type MOS tube PM8 are connected, the drain electrode of the P-type MOS tube PM7 is connected with the drain electrode of the N-type MOS tube NM5, the drain electrode of the P-type MOS tube PM9 is connected with the grid electrode of the N-type MOS tube NM5, the grid electrode and the drain electrode of the N-type MOS tube NM6, the source electrode of the N-type MOS tube NM5 is connected with the emitter electrode of the PNP-type triode Q3, the base electrode and the collector electrode of the PNP-type triode Q3 are connected with the ground, the lower end of the resistor R2 is connected with the emitter electrode of the PNP-type triode Q4, the base electrode and the collector electrode of the PNP-type MOS tube PM4 are connected with the ground, the grid electrode of the P-type MOS tube PM6 and the grid electrode of the P-type MOS tube PM8 are connected with the grid electrode of the P-type MOS tube PM2, and the grid electrode of the P-type MOS tube PM7 and the grid electrode of the P-type MOS tube PM9 are connected with the grid electrode of the P-type MOS tube PM 3.

The P-type MOS tube PM6 and the P-type MOS tube PM7 form a cascode current mirror, and output impedance is increased. On one hand, the current can be accurately copied, and on the other hand, the influence of power supply fluctuation on the drain voltage of the N-type MOS tube NM5 can be effectively counteracted. The P-type MOS tube PM8 and the P-type MOS tube PM9 also form a common-source common-gate current mirror, and the action is consistent with that of the P-type MOS tube PM6 and the P-type MOS tube PM7, so that the grid voltage of the drain electrode N-type MOS tube NM7 of the N-type MOS tube NM6 cannot be influenced by the power supply voltage. The generation mechanism of the positive temperature current is as follows:

the gates of the N-type MOS transistor NM5 and the N-type MOS transistor NM6 are connected, and the P-type MOS transistor PM6 and the P-type MOS transistor PM7 and the P-type MOS transistor PM8 and the P-type MOS transistor PM9 are connected in a common-source common-gate manner, so that the drain voltages of the N-type MOS transistor NM5 and the N-type MOS transistor NM6 are almost equal. P-type MOS tube PM 8P-type MOS tube PM9 is a current mirror, and the positive temperature current is mirrored.

As a preferred embodiment, the negative temperature coefficient current generating circuit includes a P-type MOS transistor PM10, a P-type MOS transistor PM11, an N-type MOS transistor NM7, and a resistor R3.

The source electrode of the P-type MOS tube PM10 is connected with a power supply, the drain electrode of the P-type MOS tube PM11 is connected with the drain electrode of the N-type MOS tube NM7, the source electrode of the N-type MOS tube NM7 is connected with the upper end of a resistor R3, the lower end of the resistor R3 is connected with the ground, the grid electrode of the N-type MOS tube NM7 is connected with the drain electrode of the P-type MOS tube PM9, and the grid electrode of the P-type MOS tube PM11 is connected with the grid electrode of the P-type MOS tube PM 3.

The grid electrode of the N-type MOS tube NM7 is connected with the grid electrodes of the N-type MOS tube NM5 and the N-type MOS tube NM6, and the grid voltage of the N-type MOS tube NM7 is equal to vbe3+Vgs5. Since the PNP type transistor has negative temperature characteristics, and voltage decreases with temperature rise, negative temperature current is as follows:

the P-type MOS transistor PM10 and the P-type MOS transistor PM11 serve as current mirrors that mirror the negative temperature current.

As a preferred embodiment, the zero temperature coefficient voltage generating circuit includes a P-type MOS transistor PM12, a P-type MOS transistor PM13, a P-type MOS transistor PM14, a P-type MOS transistor PM15, a resistor R4, and a PNP transistor Q5.

The source electrode of the P-type MOS tube PM12 is connected with a power supply, the drain electrode is connected with the source electrode of the P-type MOS tube PM13, the drain electrode of the P-type MOS tube PM13 is connected with the upper end of a resistor R4 and the grid electrode of the N-type MOS tube NM1, the source electrode of the P-type MOS tube PM14 is connected with the power supply, the drain electrode is connected with the source electrode of the P-type MOS tube PM15, the source electrode of the P-type MOS tube PM15 is connected with the drain electrode of the P-type MOS tube PM14, the lower end of the resistor R4 is connected with the emitter electrode of the PNP-type triode Q5, the base electrode and the collector electrode of the PNP-type triode Q4 are connected with the ground, the grid electrode of the P-type MOS tube PM14 is connected with the grid electrode of the P-type MOS tube PM2, and the grid electrode of the P-type MOS tube PM15 is connected with the grid electrode of the P-type MOS tube PM 3.

The P-type MOS tube PM12 and the P-type MOS tube PM13 adopt a common-source common-gate structure to more accurately mirror the positive temperature current I2, the proper positive temperature coefficient beta 1 is obtained by controlling the sizes of the P-type MOS tube PM12 and the P-type MOS tube PM13, the positive temperature current beta 1I2 is obtained, the P-type MOS tube PM14 and the P-type MOS tube PM15 adopt the common-source common-gate structure to more accurately mirror the positive temperature current I1, the proper negative temperature coefficient beta 2 is obtained by controlling the sizes of the P-type MOS tube PM14 and the P-type MOS tube PM15, and the positive temperature current beta 2I1 is obtained. However, in order to obtain a more accurate zero temperature coefficient voltage, a PNP transistor Q5 is introduced, and since the PNP transistor Q5 itself has a negative temperature characteristic, a temperature coefficient output voltage is introduced for Wen Piaoyue hours when the zero temperature coefficient voltage is formed. The zero temperature coefficient voltage is expressed as:

VREF＝(β1I2+β2I 1)*R4+vbe5

and parameters beta 1 and beta 2 are reasonably regulated, the current beta 1I2 plus beta 2I1 presents positive temperature characteristics, the current is multiplied by R4 to obtain positive temperature voltage, the negative temperature characteristic voltage vbe5 of the PNP triode Q5 is superposed with the positive temperature voltage multiplied by the current beta 1I2 plus beta 2I1 positive temperature current and R4 to obtain the voltage VREF with zero temperature coefficient.

The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be appreciated by persons skilled in the art that the above embodiments are not intended to limit the invention in any way, and that all technical solutions obtained by means of equivalent substitutions or equivalent transformations fall within the scope of the invention.

Claims (6)

1. A low temperature drift voltage reference circuit, comprising: the power supply comprises a starting circuit, a voltage bias circuit, a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit and a zero temperature coefficient voltage generating circuit;

the starting circuit is used for starting the low-temperature drift voltage reference circuit;

the voltage bias circuit is used for generating a bias voltage;

the positive temperature coefficient current generating circuit is used for generating positive temperature current;

the negative temperature coefficient current generating circuit is used for generating negative temperature current;

the zero temperature coefficient voltage generation circuit is used for generating zero temperature voltage;

the starting circuit, the voltage bias circuit, the positive temperature coefficient current generation circuit, the negative temperature coefficient current generation circuit and the zero temperature coefficient voltage generation circuit are sequentially connected.

2. The low temperature drift voltage reference circuit of claim 1, wherein,

the starting circuit comprises a resistor R1, an N-type MOS tube NM1, a P-type MOS tube PM1, an N-type MOS tube NM2 and a P-type MOS tube PM16;

the upper port of the resistor R1 is connected with a power supply, the lower port of the resistor R1 is connected with the drain electrode of the N-type MOS tube NM1, the source electrode of the N-type MOS tube NM1 is connected with the ground, the grid electrode is connected with the output voltage VREF, the source electrode of the P-type MOS tube PM1 is connected with the power supply, the drain electrode is connected with the drain electrode of the N-type MOS tube NM2 and the grid electrode of the P-type MOS tube PM16, the grid electrode is connected with the grid electrode of the N-type MOS tube NM2 and the drain electrode of the N-type MOS tube NM1, the source electrode of the N-type MOS tube NM2 is connected with the ground, and the source electrode of the P-type MOS tube PM16 is connected with the power supply.

3. The low temperature drift voltage reference circuit of claim 2, wherein,

the voltage bias circuit includes: p-type MOS tube PM2, P-type MOS tube PM3, P-type MOS tube PM4, P-type MOS tube PM5, N-type MOS tube NM3, N-type MOS tube NM4, PNP-type triode Q1 and PNP-type triode Q2;

the source electrode and the power supply of P type MOS pipe PM2 are connected, the drain electrode with the source electrode of P type MOS pipe PM3 is connected, the grid electrode with the drain electrode of P type MOS pipe PM3 with the drain electrode of N type MOS pipe NM3 is connected, the grid electrode of P type MOS pipe PM3 with the grid electrode of P type MOS pipe PM4 and the grid electrode of P type MOS pipe PM5 are connected, the source electrode and the power supply of P type MOS pipe PM4 are connected, the drain electrode of P type MOS pipe PM5 with the drain electrode of N type MOS pipe NM4 is connected, the source electrode of N type MOS pipe NM3 with the emitter electrode of PNP type triode NM4 is connected, the source electrode and the emitter electrode of PNP type triode Q2 are connected, the base electrode and the collector electrode of PNP type MOS pipe Q1 are connected with the ground, the base electrode and the collector electrode of PNP type MOS pipe Q2 are connected with the ground, the drain electrode of N type MOS pipe NM3 and the drain electrode of N type MOS pipe NM4 are connected with the drain electrode of P type MOS pipe NM 4.

4. The low temperature drift voltage reference circuit of claim 3, wherein,

the positive temperature coefficient current generating circuit comprises a P-type MOS tube PM6, a P-type MOS tube PM7, a P-type MOS tube PM8, a P-type MOS tube PM9, an N-type MOS tube NM5, an N-type MOS tube NM6, a resistor R2, a PNP-type triode Q3 and a PNP-type triode Q4;

the source and the power supply of P type MOS pipe PM6 are connected, the drain electrode with the source of P type MOS pipe PM7 is connected, the source and the power supply of P type MOS pipe PM8 are connected, the drain electrode with the source of P type MOS pipe PM9 is connected, the drain electrode of P type MOS pipe PM7 with the drain electrode of N type MOS pipe NM5 is connected, the drain electrode of P type MOS pipe PM9 with N type MOS pipe NM5 grid electrode, N type MOS pipe NM6 grid electrode and drain electrode, N type MOS pipe NM 5's source electrode with PNP type triode Q3's projecting electrode is connected, N type MOS pipe NM 6's source electrode with resistance R2's upper end is connected, PNP type triode Q3's base and collector are connected with ground, resistance R2's lower extreme with PNP type triode Q4's projecting electrode is connected, P type MOS pipe PM6 grid electrode with P type MOS pipe PM8 grid electrode with P type MOS pipe PM2 grid electrode and P type MOS pipe PM3 grid electrode is connected with P type MOS pipe PM3 grid electrode and P type MOS pipe PM 3.

5. The low temperature drift voltage reference circuit of claim 4, wherein,

the negative temperature coefficient current generation circuit comprises a P-type MOS tube PM10, a P-type MOS tube PM11, an N-type MOS tube NM7 and a resistor R3;

the source electrode and the power supply of P type MOS pipe PM10 are connected, the drain electrode with the drain electrode of P type MOS pipe PM11 and the drain electrode of N type MOS pipe NM7 are connected, the drain electrode of P type MOS pipe PM11 with the drain electrode of N type MOS pipe NM7 is connected, the source electrode of N type MOS pipe NM7 with the upper end of resistance R3 is connected, the lower extreme of resistance R3 is connected with ground, the grid of N type MOS pipe NM7 with the drain electrode of P type MOS pipe PM9 is connected, the grid of P type MOS pipe PM11 with the grid of P type MOS pipe PM3 is connected.

6. The low temperature drift voltage reference circuit of claim 5, wherein,

the zero temperature coefficient voltage generation circuit comprises a P-type MOS tube PM12, a P-type MOS tube PM13, a P-type MOS tube PM14, a P-type MOS tube PM15, a resistor R4 and a PNP-type triode Q5;

the source electrode and the power supply of P type MOS pipe PM12 are connected, the drain electrode is connected with the source electrode of P type MOS pipe PM13, the drain electrode of P type MOS pipe PM13 with the drain electrode of P type MOS pipe PM15 with the upper end of resistance R4 and the grid of N type MOS pipe NM1 is connected, the source electrode of P type MOS pipe PM14 is connected with the power supply, the drain electrode is connected with the source electrode of P type MOS pipe PM15, the source electrode of P type MOS pipe PM15 is connected with the drain electrode of P type MOS pipe PM14, the lower extreme of resistance R4 with the emitter of PNP type triode Q5 is connected, the base and collector of PNP type triode Q4 are connected with ground, the grid of P type MOS pipe PM14 is connected with the grid of P type MOS pipe PM2, the grid of P type MOS pipe PM13 with the grid of P type MOS pipe PM15 is connected with the grid of P type MOS pipe PM 3.

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