CN115938972A - Semiconductor chamber and semiconductor processing equipment - Google Patents
Semiconductor chamber and semiconductor processing equipment Download PDFInfo
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- CN115938972A CN115938972A CN202110947384.8A CN202110947384A CN115938972A CN 115938972 A CN115938972 A CN 115938972A CN 202110947384 A CN202110947384 A CN 202110947384A CN 115938972 A CN115938972 A CN 115938972A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a semiconductor chamber and semiconductor process equipment, wherein the semiconductor chamber comprises a first chamber body, an isolation valve, a temperature control assembly, a first bearing part and a second bearing part; the isolation valve is arranged in the first cavity body, the isolation valve separates an inner cavity of the first cavity body to form at least two process cavities, the first cavity body is provided with a wafer transmission port, and the wafer transmission port is communicated with one process cavity of the at least two process cavities; each process cavity is provided with a temperature control assembly, and the temperature control effects of the two temperature control assemblies in the two adjacent process cavities are different; the first bearing part and the second bearing part are respectively positioned in two adjacent process cavities, under the condition that an isolation valve between the two adjacent process cavities is opened, the first bearing part can move into the process cavity where the second bearing part is positioned, and the wafer can be transferred between the first bearing part and the second bearing part. The scheme can solve the problem of insufficient productivity of semiconductor process equipment.
Description
Technical Field
The invention relates to the technical field of semiconductor chip manufacturing, in particular to a semiconductor cavity and semiconductor process equipment.
Background
In the related art, a heating chamber, a cooling chamber, a CVD (Chemical Vapor Deposition) chamber, and other process chambers are disposed in the semiconductor processing apparatus.
In the process of processing the wafer by the semiconductor processing equipment, after the wafer is processed in the CVD chamber, the wafer needs to be conveyed into the heating chamber for heating treatment. And after the heating is finished, transferring the wafer into a cooling chamber for cooling, thereby carrying out the annealing process on the wafer. When there is no wafer being processed in the heating chamber or the cooling chamber, the wafer may be transferred into the heating chamber or the cooling chamber. When the wafers are being processed in the heating chamber or the cooling chamber, the wafers in the previous process step need to be transported after the wafers in the process chamber in the next process step are processed and transferred out. Because the process chambers have single function, each process chamber can only realize one process type, thereby prolonging the processing time of the whole wafer and seriously affecting the productivity of semiconductor processing equipment.
In the related art, the number of process chambers that can be communicated with a transfer chamber in a semiconductor processing apparatus is determined, so that under the condition that the total number of the process chambers is kept unchanged, the number of one or more process chambers is increased, and the number of another or more process chambers is reduced. Thus, the problem of insufficient throughput of semiconductor processing equipment cannot be solved by increasing the number of one or more process chambers.
Disclosure of Invention
The invention discloses a semiconductor chamber and semiconductor process equipment, and aims to solve the problem of insufficient productivity of the semiconductor process equipment.
In order to solve the problems, the invention adopts the following technical scheme:
a semiconductor chamber, comprising:
the separation valve is arranged in the first chamber body, the separation valve separates an inner cavity of the first chamber body to form at least two process cavities, the first chamber body is provided with a wafer transmission port, and the wafer transmission port is communicated with one of the at least two process cavities;
the temperature control assemblies are arranged in the process chambers, and the temperature control effects of the two temperature control assemblies in the two adjacent process chambers are different;
the wafer transferring device comprises a first bearing part and a second bearing part, wherein the first bearing part and the second bearing part are respectively positioned in two adjacent process chambers, under the condition that the isolation valve between the two adjacent process chambers is opened, the first bearing part can move into the process chamber where the second bearing part is positioned, and the wafer can be transferred between the first bearing part and the second bearing part.
The semiconductor processing equipment comprises a first process chamber and a second process chamber, wherein the second process chamber is the semiconductor chamber, the number of the first process chamber and the second process chamber is multiple, the multiple first process chambers and the multiple second process chambers are distributed at intervals, and wafers of each first process chamber can be conveyed into the second process chamber which is idle.
The technical scheme adopted by the invention can achieve the following beneficial effects:
in the semiconductor cavity disclosed by the invention, the inner cavity of the first cavity body is divided into at least two process cavities through the isolation valve, each process cavity is provided with the temperature control assembly, the temperature control effects of the temperature control assemblies in the two adjacent process cavities are different, namely, one semiconductor cavity can be compatible with at least two process cavities with different temperature control effects, for example, heating or cooling is respectively realized. That is, one semiconductor chamber can be compatible with at least two different processes, so that the number of process chambers for performing different processes is increased by the semiconductor processing equipment without changing the total number of the process chambers, thereby improving the productivity of the semiconductor processing equipment.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic view of a semiconductor processing apparatus;
FIG. 2 is a schematic structural diagram of a semiconductor chamber according to an embodiment of the present invention;
FIG. 3 is a top view of a semiconductor chamber according to one embodiment of the present disclosure;
fig. 4 is a schematic structural view illustrating a second carrying portion of a semiconductor chamber according to an embodiment of the present invention when a telescopic portion is contracted;
fig. 5 is a schematic structural diagram of the semiconductor chamber according to an embodiment of the invention when the expansion portion of the second supporting portion is expanded.
Description of reference numerals:
110-first chamber body, 111-process chamber, 112-chamber body, 1121-through hole, 1122-assembly gap, 120-second chamber body,
200-an isolation valve,
300-a temperature control component,
410-first bearing part, 420-second bearing part, 421-fixed part, 422-telescopic part,
510-a first air suction pipeline, 511-a first valve, 520-a second air suction pipeline, 521-a second valve,
610-process gas pipeline, 620-pipeline valve,
700-wafer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the disclosed embodiments are merely exemplary of the invention, and are not intended to be exhaustive or exhaustive. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solutions disclosed in the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
In the related art, taking a CVD process as an example, a semiconductor processing apparatus includes a CVD chamber, a heating chamber, and a cooling chamber. As shown in fig. 1, chamber No. 1 is a heating chamber, chamber No. 2 is a cooling chamber, and chambers No. 3 to 6 are CVD chambers.
In the specific process, wafers processed in the No. 3 to No. 6 chambers need to be conveyed into the No. 1 chamber for heating and then conveyed into the No. 2 chamber for cooling, so that the wafers are subjected to an annealing process to improve the performance of the wafers.
For example, when the wafer in the chamber No. 3 is transferred to the chamber No. 1 for processing, the wafers in the chamber No. 4 and the chamber No. 6 need to wait for the chamber No. 1 to be idle, and then are sequentially transferred to the chamber No. 1. This results in a prolonged processing time for the entire wafer, which severely affects the throughput of the semiconductor processing equipment.
Then, since the number of chambers of the semiconductor process equipment is determined, the number of CVD chambers is decreased when the number of heating chambers and cooling chambers is increased, and thus this manner of increasing the number of chambers cannot solve the problem of insufficient productivity of the semiconductor process equipment.
As shown in fig. 2 to 5, the embodiment of the invention discloses a semiconductor chamber, which includes a first chamber body 110, an isolation valve 200, a temperature control assembly 300, a first supporting portion 410, and a second supporting portion 420.
The isolation valve 200 is disposed in the first chamber body 110, and the isolation valve 200 separates an inner cavity of the first chamber body 110 to form at least two process chambers 111. Specifically, at least two process chambers 111 are spaced apart in a height direction of the first chamber body 110. The first chamber body 110 is opened with a wafer transfer port, and the wafer transfer port is communicated with one process chamber 111 of at least two process chambers 111.
Optionally, to further avoid temperature interference between the two process chambers 111, the isolation valve 200 is preferably made of a material with poor thermal conductivity, such as a smooth stainless steel valve.
Each process chamber 111 is provided with a temperature control assembly 300, and the temperature control effects of the two temperature control assemblies 300 in the two adjacent process chambers 111 are different. Such a design may enable a single semiconductor chamber to be compatible with at least two process chambers 111 of different temperatures.
Specifically, in two adjacent process chambers 111, the temperature control assembly 300 in one process chamber 111 can perform a heating function, and the temperature control assembly 300 in the other process chamber 111 can perform a cooling function, that is, one of the two adjacent process chambers 111 can be a heating chamber, and the other can be a cooling chamber.
The first bearing part 410 and the second bearing part 420 are respectively located in two adjacent process chambers 111, and when the isolation valve 200 between the two adjacent process chambers 111 is opened, the first bearing part 410 can move into the process chamber 111 where the second bearing part 420 is located, and the wafer 700 can be transferred between the first bearing part 410 and the second bearing part 420.
In a specific process, the temperature control assembly 300 in one process chamber 111 can be a heater, and the temperature control assembly 300 in the other process chamber 111 can be a cooler, so as to implement cooling and heating functions. The process chamber 111 in which the first carrier 410 is disposed may be a heating chamber, and the chamber in which the second carrier 420 is disposed may be a cooling chamber. At this time, the wafer 700 is transferred to the first carrying portion 410, after the process chamber 111 where the first carrying portion 410 is located is heated, the isolation valve 200 is opened, the first carrying portion 410 transfers the wafer 700 to the process chamber 111 where the second carrying portion 420 is located, and transfers the wafer to the second carrying portion 420, however, the first carrying portion 410 returns to the process chamber 111 where the first carrying portion 410 is located, and closes the isolation valve 200, and then cools the wafer 700. After the cooling process is completed, the isolation valve 200 is opened, the second carrier 420 transfers the wafer 700 to the first carrier 410, the first carrier 410 carries the wafer 700 to the process chamber 111 where the wafer 700 is located, and then the wafer 700 is transferred out of the semiconductor chamber, thereby completing the annealing process of the wafer 700.
Of course, the wafer 700 may be transported out of the semiconductor chamber directly from the cooling chamber after the cooling process is completed, and the invention is not limited thereto.
In the embodiment disclosed in the present application, the semiconductor processing apparatus can be compatible with at least two different processes, so that the number of the processing chambers 111 for performing different processes is increased without changing the total number of the processing chambers, and the throughput of the semiconductor processing apparatus can be improved.
The semiconductor cavity disclosed by the application can replace a cavity 1 and a cavity 2 in the related technology, and the replaced cavity 1 and the replaced cavity 2 can finish heating and cooling processes, so that when the cavity 1 is used for processing, wafers 700 in the cavities 3 to 6 can be transmitted into the cavity 2 without waiting for the cavity 1 to be idle, and therefore under the condition that the total number of the process cavities of semiconductor process equipment is not increased, the number of the process cavities 111 is increased, and the productivity of the semiconductor process equipment can be improved.
In addition, the chamber 1 and the chamber 2 in the related art need to be transported by a manipulator, and the semiconductor chamber in the application does not need to be transported by the manipulator, so that the structure of semiconductor processing equipment is simplified, and meanwhile, the scheduling time and the transporting time in the transporting process are shortened.
In another alternative embodiment, the semiconductor chamber disclosed herein may further include at least two first pumping lines 510, the first pumping lines 510 may be connected to one process chamber 111, the first pumping lines 510 may be used to connect the process chamber 111 to a vacuum controller, the first pumping lines 510 may be provided with a first valve 511, and the first valve 511 controls the vacuum pump to be connected to or disconnected from the process chamber 111. At this time, when the process chamber 111 needs to be evacuated, the first valve 511 may be opened, and the first pumping line 510 is communicated with the process chamber 111, so as to evacuate the corresponding process chamber 111, so that the corresponding process chamber 111 is in a vacuum state.
In this embodiment, the semiconductor chamber is under vacuum during the transfer of the wafer 700, and thus may be connected to a vacuum controller through the first pumping line 510 and the first valve 511, thereby facilitating the vacuum process of the process chamber 111.
In the above embodiment, each process chamber 111 corresponds to one first pumping line 510, and the first pumping line 510 is correspondingly provided with the first valve 511, so that the corresponding process chamber 111 can be vacuumized by opening the first valve 511 corresponding to each process chamber 111.
In the above embodiments, the semiconductor chamber may include a vacuum controller, and of course, the vacuum controller may also be included in the semiconductor processing apparatus for evacuating the entire semiconductor processing apparatus.
In the above embodiment, since the wafer 700 in the vacuum state has poor heat conductivity, in another optional embodiment, the semiconductor chamber disclosed herein may further include at least two process gas lines 610, the process gas lines 610 may be in communication with one process chamber 111, and the process chamber 111 may be in communication with a process gas source through the process gas lines 610. The process gas line 610 may be provided with a line valve 620, and the line valve 620 controls the connection and disconnection of a process gas source to the process chamber 111.
In this embodiment, when the process chamber 111 is performing a process, the corresponding pipeline valve 620 may be opened to ventilate the process chamber 111, so that the process chamber 111 is in an atmospheric state, and a heating or cooling process is performed, thereby increasing a heat conduction or cooling rate of the wafer 700.
The process gas in the above embodiments may be a process gas such as nitrogen, argon, etc., and may also be other process gases, which is not limited herein.
In the above embodiment, the temperatures of two adjacent process chambers 111 are easily influenced, and therefore, in another alternative embodiment, the first chamber body 110 may include at least two chamber portions 112, the chamber portions 112 may be provided with through holes 1121, the through holes 1121 of two adjacent chamber portions 112 are oppositely disposed, and an assembly gap 1122 may be formed between two adjacent chamber portions 112, that is, a certain distance is formed between two adjacent chamber portions 112, which are not in direct contact with each other. The isolation valve 200 may be located in the fitting gap 1122 between the two opposing through holes 1121. At this time, the isolation valve 200 is disposed in the fitting gap 1122, and the two through holes 1121 are communicated or isolated by the isolation valve 200.
In this scheme, a certain distance is provided between two adjacent cavity parts 112, and the two adjacent cavity parts 112 are not in direct contact, so that the temperature of one cavity part 112 is not easily transferred to the other cavity part 112, and thus the temperatures between two adjacent process chambers 111 are not easily influenced with each other, and the reliability and the safety of the semiconductor chamber are improved.
Further, the semiconductor chamber disclosed herein may further include a second chamber body 120 and a second pumping line 520, the first chamber body 110 may be located in the second chamber body 120, the first chamber body 110 and the second chamber body 120 are spaced apart from each other, and an inner cavity of the second chamber body 120 may be communicated with the second pumping line 520. The second pumping line 520 is used for connecting the inner cavity of the second chamber body 120 with the vacuum controller, the second pumping line 520 may be provided with a second valve 521, and the second valve 521 may control the vacuum controller to be connected with or disconnected from the inner cavity of the second chamber body 120.
In this embodiment, the second chamber body 120 can enclose the first chamber body 110 in the inner cavity thereof, and preferably, a plurality of supporting members (not shown) are disposed between the bottom walls of the first and second chamber bodies 110, the supporting members can provide a supporting force for the first chamber body 110, and preferably, the supporting members have a contact area with the first chamber body 110 and the second chamber body 120 as small as possible and are made of a non-heat-conductive material, so as to reduce the temperature conduction between the first chamber body and the second chamber body 120. The design of the second chamber body 120 can prevent the first chamber body 110 from being damaged, improve the safety of the semiconductor chamber, and further avoid the interference of the temperatures of the two process chambers 111 by adjusting the vacuum degree in the inner cavity of the second chamber body 120.
Specifically, the inner cavity of the second chamber body 120 may be evacuated through the second pumping line 520, so that the inner cavity of the second chamber body 120 is in a vacuum state, and thus, the heat transfer performance between two adjacent chamber portions 112 can be reduced, and thus, the temperature influence between two adjacent process chambers 111 is further reduced.
In another alternative embodiment, the second carrier part 420 may include a plurality of sub-carrier parts, and the plurality of sub-carrier parts may be uniformly arranged in a circumferential direction of the inner wall of the corresponding process chamber 111 for forming a carrier surface for carrying the wafer 700. In this embodiment, the second bearing part 420 can be uniformly borne in the circumferential direction of the wafer 700, so that the wafer 700 is uniformly stressed and is not easily inclined, thereby improving the bearing stability of the wafer 700.
In the above embodiment, during the process of transferring the wafer 700, the second carrier part 420 is likely to interfere with the wafer 700, so that the wafer 700 falls off during the process of transferring.
Further, in another optional embodiment, each of the sub-carrying portions may include a fixing portion 421 and an expansion portion 422, wherein the fixing portion 421 is detachably connected to the inner wall of the corresponding process chamber 111, and the expansion portion 422 is capable of expanding and contracting along the fixing portion 421. In this embodiment, the stretching part 422 can be extended or shortened, when the first carrying part 410 transfers the wafer 700 to the second carrying part 420, the stretching part 422 is shortened, the first carrying part 410 conveys the wafer 700 to a position higher than the second carrying part 420, the stretching part 422 is extended, a part of the stretching part 422 extends to a position below the wafer 700, and the wafer 700 is transferred to the stretching part 422 during the falling process of the first carrying part 410, thereby completing the transfer of the wafer 700. When the wafer 700 of the second carrier part 420 is transferred to the first carrier part 410, the wafer 700 is jacked up and the expansion part 422 is shortened in the process of ascending the first carrier part 410, and the expansion part 422 does not interfere with the wafer 700 due to the shortening of the expansion part 422 in the process of falling the first carrier part 410.
In this embodiment, the retractable portion 422 can be retracted, so that interference between the wafer 700 and the first supporting portion 410 is not easy to occur, and reliability and safety of wafer 700 transmission are improved.
Alternatively, the telescopic portion 422 may be a hydraulic cylinder or a pneumatic cylinder, and of course, the telescopic portion 422 may also have other structures, which is not limited herein.
The fixing portion 421 is detachably connected to the inner wall of the process chamber 111 in the above embodiments, so that the sub-carrier portion can be replaced easily, thereby improving the maintainability of the semiconductor chamber. The fixing portion 421 and the inner wall of the process chamber 111 can be connected by a process such as screwing, clipping, etc., or can be connected by other methods, which is not limited herein.
Optionally, the first carrier 410 may include a plurality of pins spaced apart from each other, and the plurality of pins jointly lift the wafer 700.
In the above embodiment, during the transportation of the first carrier part 410 to the adjacent process chamber 111, the first carrier part 410 is likely to collide with the isolation valve 200 during the transportation. To this end, in another alternative embodiment, the semiconductor chamber disclosed in the present application may further include a detection element and a control element, and the detection element and the control element may be in control connection. The detecting element may be disposed in the process chamber 111 where the first carrying part 410 is located, and the detecting element is configured to detect a distance between the first carrying part 410 and the isolation valve 200, and at this time, the detecting element is configured to detect a distance between the first carrying part 410 and the isolation valve 200 in the process chamber 111 corresponding to the first carrying part 410, that is, the first carrying part 410 is in a non-transmission state or is transmitted back to the distance between the process chamber 111 corresponding to the first carrying part and the isolation valve 200.
When the distance between the first bearing part 410 and the isolation valve 200 is greater than or equal to the preset safety switch distance, the control element controls the isolation valve 200 to open or close.
In a specific process engineering, when the first carrying part 410 moves to a distance less than a preset safety switch distance in a process of transferring the wafer 700 from the first carrying part 410 to the adjacent process chamber 111, the isolation valve 200 is already opened, so that the first carrying part 410 or the wafer 700 is prevented from colliding with the isolation valve 200.
When the first carrying part 410 returns to the process chamber 111 where the first carrying part 410 is located, the isolation valve 200 can be closed only when the first carrying part 410 moves to a distance greater than or equal to a preset safety switch distance, so as to avoid collision between the first carrying part 410 or the wafer 700 and the isolation valve 200.
The scheme can improve the safety performance of the semiconductor chamber and avoid the collision of the first bearing part 410 or the wafer 700 and the isolation valve 200.
Alternatively, the preset safety switch distance may be a distance between the bearing surface of the first bearing part 410 and the bottom surface of the isolation valve 200, and the distance may be 5mm, and of course, other values may also be used, which is not limited herein.
In another alternative embodiment, the position where the first carrying part 410 moves to the highest point in the adjacent process chamber 111 may be more than 2mm below the top of the process chamber 111, thereby preventing the first carrying part 410 from colliding with the top of the process chamber 111.
In another alternative embodiment, the isolation valve 200 may be a pneumatic control valve, and the semiconductor chamber disclosed herein may further include a vent line, which may be in communication with the isolation valve 200, and which is vented or de-vented to control the isolation valve 200 to open or close. In this scheme, the air is communicated with the air vent line, so that the isolation valve 200 is controlled to be opened or closed, and the opening or closing process of the isolation valve 200 is simplified.
In the above embodiment, when the entire semiconductor chamber is powered off, the ventilation pipeline stops ventilation, so that the isolation valve 200 is closed by mistake, and the isolation valve 200 is likely to collide with the first bearing portion 410.
Based on this, in another alternative embodiment, the gas line may include a first vent line and a second vent line, both of which may be in communication with the isolation valve 200.
When the first vent line is vented and the second vent line is de-vented, the isolation valve 200 is opened.
With the first vent line vented and the second vent line vented, the isolation valve 200 is closed.
In this scheme, the two ventilation pipelines control the opening and closing of the valve, the isolation valve 200 is only opened in the first ventilation pipeline, and the second ventilation pipeline is opened in the gas-off state. The isolation valve 200 is only in the first ventilation pipeline air-break state, and the second ventilation pipeline air-break state is closed, so in the first ventilation pipeline and the second ventilation pipeline both air-break state or all air-break state, the state of the isolation valve 200 is not changed, therefore, the condition that the isolation valve 200 is mistakenly opened or closed due to misoperation is avoided, the isolation valve 200 is prevented from colliding with the first bearing part 410, and then the isolation valve 200 or the first bearing part 410 is damaged, so as to improve the safety of the semiconductor chamber.
In another alternative embodiment, when the distance between the first carrier 410 and the isolation valve 200 is greater than or equal to the preset safety switch distance during the process of transferring the wafer 700 from the first carrier 410 to the adjacent process chamber 111, the first venting line is vented, and the second venting line is cut off, so that the isolation valve 200 is opened, and the isolation valve 200 is kept in an open state after being opened.
When the first supporting part 410 returns to the process chamber 111 where it is located, and the first supporting part 410 moves to a distance greater than or equal to the preset safety switch distance, the first ventilation pipeline is cut off, and the second ventilation pipeline is ventilated, so that the isolation valve 200 is closed, and the isolation valve 200 is kept in a closed state after being closed.
Based on the semiconductor chamber of any of the above embodiments of the present invention, an embodiment of the present invention further discloses a semiconductor processing apparatus, and the disclosed semiconductor manufacturing apparatus has the semiconductor chamber of any of the above embodiments.
The semiconductor processing equipment comprises a first process chamber and a second process chamber, and the second process chamber can be the semiconductor chamber of any one of the embodiments. The number of the first process chambers and the second process chambers is multiple, the first process chambers and the second process chambers are distributed at intervals, and the wafer 700 of each first process chamber can be transferred into the idle second process chamber.
Specifically, the first process chamber is used for performing an annealing process on the wafer 700, and the second process chamber may be a CVD chamber, an etching chamber, or other process chambers. The first process chamber and the second process chamber in the semiconductor process equipment disclosed in the present application may also adopt the layout manner as shown in fig. 1, the No. 1 chamber and the No. 2 chamber may be replaced with the semiconductor chamber disclosed in the present application, and the No. 3 to No. 6 chambers are a plurality of second process chambers. For example, the wafer processed in the chamber 3 may be placed in the chamber 1, the wafer 700 processed in the chamber 4 may be transferred into the chamber 2, and the wafers 700 in the chambers 5 and 6 may be transferred after waiting for the chambers 1 and 2 to be idle.
In the embodiment disclosed by the application, the semiconductor chambers can be compatible with at least two different processes, so that the number of the process chambers is increased and the capacity of the semiconductor process equipment can be improved under the condition that the total number of the process chambers is not changed by the semiconductor process equipment.
It should be noted that the layout of the semiconductor processing equipment in the related art and the layout chamber disclosed in the present application may be the same, but the structures of the chamber No. 1 and the chamber No. 2 are different.
In the above embodiments of the present invention, the difference between the embodiments is mainly described, and different optimization features between the embodiments can be combined to form a better embodiment as long as they are not contradictory, and further description is omitted here in view of brevity of the text.
The above description is only an example of the present invention, and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (10)
1. A semiconductor chamber, comprising:
the wafer processing device comprises a first chamber body (110) and an isolation valve (200), wherein the isolation valve (200) is arranged in the first chamber body (110), the isolation valve (200) separates an inner cavity of the first chamber body (110) to form at least two process cavities (111), a wafer transmission port is formed in the first chamber body (110), and the wafer transmission port is communicated with one process cavity (111) of the at least two process cavities (111);
the temperature control assemblies (300) are arranged in each process cavity (111), and the temperature control effects of the two temperature control assemblies (300) in the two adjacent process cavities (111) are different;
the wafer transferring device comprises a first bearing part (410) and a second bearing part (420), wherein the first bearing part (410) and the second bearing part (420) are respectively positioned in two adjacent process chambers (111), under the condition that the isolation valve (200) between the two adjacent process chambers (111) is opened, the first bearing part (410) can move into the process chamber (111) where the second bearing part (420) is positioned, and wafers (700) can be transferred between the first bearing part (410) and the second bearing part (420).
2. The semiconductor chamber of claim 1, further comprising at least two first pumping lines (510), the first pumping lines (510) being in communication with one of the process chambers (111), the first pumping lines (510) being configured to communicate the process chamber (111) with a vacuum controller, the first pumping lines (510) being configured with a first valve (511), the first valve (511) controlling the vacuum controller to communicate with or disconnect from the process chamber (111).
3. The semiconductor chamber of claim 2, further comprising at least two process gas lines (610), wherein the process gas lines (610) are in communication with one of the process chambers (111), wherein the process chamber (111) is in communication with a process gas source through the process gas line (610), wherein the process gas line (610) is provided with a line valve (620), and wherein the line valve (620) controls the process gas source to be in communication with or out of communication with the process chamber (111).
4. The semiconductor chamber according to claim 1, wherein the first chamber body (110) comprises at least two chamber portions (112), the chamber portions (112) are opened with through holes (1121), the through holes (1121) of two adjacent chamber portions (112) are oppositely disposed, a fitting gap (1122) is provided between two adjacent chamber portions (112), and the isolation valve (200) is located in the fitting gap (1122) and between two opposite through holes (1121).
5. The semiconductor chamber according to claim 4, further comprising a second chamber body (120) and a second pumping line (520), wherein the first chamber body (110) is located in the second chamber body (120) and spaced apart from the second chamber body, an inner cavity of the second chamber body (120) is communicated with the second pumping line (520), the second pumping line (520) is used for communicating the inner cavity of the second chamber body (120) with a vacuum controller, the second pumping line (520) is provided with a second valve (521), and the second valve (521) controls the vacuum controller to be communicated with or disconnected from the inner cavity of the second chamber body (120).
6. The semiconductor chamber of claim 1, wherein the second carrier part (420) comprises a plurality of sub-carrier parts uniformly arranged in a circumferential direction of the inner wall of the corresponding process chamber (111) for forming a carrier surface for carrying the wafer (700); each sub-bearing part comprises a fixing part (421) and an expansion part (422), wherein the fixing part (421) is detachably connected with the inner wall of the corresponding process chamber (111), and the expansion part (422) can move in an expansion mode along the fixing part (421).
7. The semiconductor chamber according to claim 1, further comprising a detection element and a control element, wherein the detection element is in control connection with the control element, the detection element is disposed in the process chamber (111) where the first bearing part (410) is located, and the detection element is used for detecting a distance between the first bearing part (410) and the isolation valve (200);
when the distance between the first bearing part (410) and the isolation valve (200) is larger than or equal to the preset safety switch distance, the control element controls the isolation valve (200) to be opened or closed.
8. The semiconductor chamber of claim 1, wherein the isolation valve (200) is a pneumatically controlled valve, the semiconductor chamber comprising a vent line in communication with the isolation valve (200), the vent line being vented or de-vented to control the isolation valve to open or close.
9. The semiconductor chamber of claim 8, wherein the vent line comprises a first vent line and a second vent line, each of the first vent line and the second vent line in communication with the isolation valve (200);
-in case the first venting line is vented and the second venting line is de-vented, the isolation valve (200) is opened;
in the event that the first vent line is de-energized and the second vent line is vented, the isolation valve (200) is closed.
10. A semiconductor processing apparatus comprising a first process chamber and a second process chamber, the second process chamber being a semiconductor chamber according to any one of claims 1 to 9, the first process chamber and the second process chamber being in a plurality, the plurality of first process chambers and the plurality of second process chambers being spaced apart, a wafer (700) of each first process chamber being transferable into an empty second process chamber.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110947384.8A CN115938972A (en) | 2021-08-18 | 2021-08-18 | Semiconductor chamber and semiconductor processing equipment |
| PCT/CN2022/112665 WO2023020454A1 (en) | 2021-08-18 | 2022-08-16 | Semiconductor chamber and semiconductor process device |
| TW111130708A TWI822251B (en) | 2021-08-18 | 2022-08-16 | Semiconductor chamber and semiconductor process equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110947384.8A CN115938972A (en) | 2021-08-18 | 2021-08-18 | Semiconductor chamber and semiconductor processing equipment |
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| CN115938972A true CN115938972A (en) | 2023-04-07 |
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| CN202110947384.8A Pending CN115938972A (en) | 2021-08-18 | 2021-08-18 | Semiconductor chamber and semiconductor processing equipment |
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| Country | Link |
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| CN (1) | CN115938972A (en) |
| TW (1) | TWI822251B (en) |
| WO (1) | WO2023020454A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4209357A (en) * | 1979-05-18 | 1980-06-24 | Tegal Corporation | Plasma reactor apparatus |
| TW526580B (en) * | 2002-01-24 | 2003-04-01 | Taiwan Semiconductor Mfg | Semiconductor wafer transmission system combined with temperature control apparatus |
| TW201135845A (en) * | 2009-10-09 | 2011-10-16 | Canon Anelva Corp | Acuum heating and cooling apparatus |
| US8587331B2 (en) * | 2009-12-31 | 2013-11-19 | Tommie E. Berry | Test systems and methods for testing electronic devices |
| CN104616955B (en) * | 2013-11-04 | 2017-02-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Plasma processing equipment |
| CN104752275B (en) * | 2013-12-29 | 2018-01-09 | 北京北方华创微电子装备有限公司 | Processing chamber and semiconductor processing equipment |
| CN110416351A (en) * | 2018-04-27 | 2019-11-05 | 北京创昱科技有限公司 | Chip processing system |
| CN110828273B (en) * | 2018-08-09 | 2022-07-22 | 北京北方华创微电子装备有限公司 | Plasma apparatus and plasma system |
| CN111323076A (en) * | 2018-12-13 | 2020-06-23 | 夏泰鑫半导体(青岛)有限公司 | Detection device and process chamber detection method |
| CN111477582A (en) * | 2020-05-28 | 2020-07-31 | 深圳市捷佳伟创新能源装备股份有限公司 | Silicon wafer process cavity, silicon wafer processing equipment and silicon wafer processing method |
| CN112490149B (en) * | 2020-11-13 | 2024-04-12 | 北京北方华创微电子装备有限公司 | Semiconductor processing apparatus, method for detecting the presence of a wafer in a process chamber |
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- 2021-08-18 CN CN202110947384.8A patent/CN115938972A/en active Pending
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2022
- 2022-08-16 WO PCT/CN2022/112665 patent/WO2023020454A1/en unknown
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| TW202310134A (en) | 2023-03-01 |
| WO2023020454A1 (en) | 2023-02-23 |
| TWI822251B (en) | 2023-11-11 |
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