CN115938945A - Shielding gate power device and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 65
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims description 28
- 239000003989 dielectric material Substances 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 271
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000007517 polishing process Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 210000000746 body region Anatomy 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention relates to a shielded gate power device and a preparation method thereof. The preparation method of the shielding grid power device comprises the following steps: providing a semiconductor layer; forming a trench in the semiconductor layer; forming a shielding gate dielectric layer in the trench; etching the shielding gate dielectric layer to form a shielding gate groove in the shielding gate dielectric layer; forming a shielding grid electrode in the shielding grid groove, wherein the upper surface of the shielding grid electrode is not lower than the upper surface of the shielding grid dielectric layer; forming a grid electrode medium layer on at least the exposed surface of the shielding grid electrode and the exposed side wall of the groove; and forming a grid electrode in the groove, wherein the grid electrode is positioned on the shielding grid electrode. The thickness of the shielding gate dielectric layer at the bottom of the groove can be controlled through an etching process, so that the thickness of the shielding gate dielectric layer at the bottom of the groove is larger than that of the shielding gate dielectric layer on the side wall of the groove, the tip end of the bottom of the shielding gate can be eliminated, the electric field intensity can be reduced, the voltage resistance can be improved, and the device can not be easily broken down at the bottom of the groove.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate power device and a preparation method thereof.
Background
In a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) device, a Shielded Gate Trench (SGT) MOSFET is used as a relatively advanced power device, and has the advantages of lower on-resistance, faster switching speed, and the like compared with a conventional trench MOSFET, and thus is widely applied in many fields.
A structure of a shielded gate trench MOSFET is shown in fig. 1, which may specifically include: the semiconductor layer 10, the trench 11, the shielding grid electrode 12, the shielding grid dielectric layer 13, the isolation dielectric layer 14, the grid electrode 15 and the grid electrode dielectric layer 16. Because the shielding gate dielectric layer 13 is generally formed along the inner wall of the trench 11 by growing or a deposition process, the thickness of the shielding gate dielectric layer 13 at the bottom of the trench 11 is smaller than the thickness of the shielding gate dielectric layer 13 on the side wall of the trench 11, and the bottom of the shielding gate 12 is in a tip shape, so that a strong electric field exists at the bottom of the shielding gate 12, and thus the voltage resistance of the shielding gate dielectric layer 13 is insufficient, and a device is easily broken down at the bottom of the trench 11.
Disclosure of Invention
In view of the defects of the prior art, an object of the present invention is to provide a shielded gate power device and a manufacturing method thereof, so as to solve the problems that in the existing shielded gate trench MOSFET, because the thickness of the shielded gate dielectric layer at the bottom of the trench is smaller than that of the shielded gate dielectric layer on the sidewall of the trench, and the bottom of the shielded gate is in a tip shape, a strong electric field exists at the bottom of the shielded gate, so that the voltage resistance of the shielded gate dielectric layer is insufficient, and the device is easily broken down at the bottom of the trench.
In a first aspect, the present invention provides a method for manufacturing a shielded gate power device, including:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming a shielding gate dielectric layer in the groove, wherein the upper surface of the shielding gate dielectric layer is lower than the top surface of the groove;
etching the shielding gate dielectric layer to form a shielding gate groove in the shielding gate dielectric layer;
forming a shielding grid electrode in the shielding grid groove, wherein the upper surface of the shielding grid electrode is not lower than the upper surface of the shielding grid dielectric layer;
forming a grid dielectric layer on at least the exposed surface of the shielding grid and the exposed side wall of the groove;
and forming a grid electrode in the groove, wherein the grid electrode is positioned on the shielding grid electrode.
According to the preparation method of the shielded gate power device, the shielded gate dielectric layer is formed in the groove, then the shielded gate dielectric layer is etched to form the shielded gate groove, the thickness of the shielded gate dielectric layer at the bottom of the groove can be controlled through an etching process, the thickness of the shielded gate dielectric layer at the bottom of the groove is larger than that of the shielded gate dielectric layer on the side wall of the groove, the tip of the bottom of the shielded gate can be eliminated, the electric field intensity can be reduced, the withstand voltage can be improved, and the device cannot be easily broken down at the bottom of the groove. Meanwhile, the thickness of the shielding gate dielectric layer at the bottom of the groove is controlled through an etching process, so that the thickness of the shielding gate dielectric layer at the bottom of the groove is increased, the source-drain capacitance Cds of the device can be reduced, the switching speed of the device is improved, and the switching loss is reduced.
In one embodiment, forming a trench in the semiconductor layer includes:
forming a patterned mask layer on the upper surface of the semiconductor layer, wherein an opening pattern is arranged in the patterned mask layer, and the opening pattern is defined into the shape and the position of the groove;
and etching the semiconductor layer based on the patterned mask layer so as to form the groove in the semiconductor layer.
In one embodiment, forming a patterned mask layer on the top surface of the semiconductor layer includes:
forming a first mask layer on the upper surface of the semiconductor layer;
forming a second mask layer on the upper surface of the first mask layer;
and patterning the first mask layer and the second mask layer to obtain the patterned mask layer comprising the first patterned mask layer and the second patterned mask layer.
In one embodiment, forming a shield gate dielectric layer in the trench includes:
forming a first shielding gate dielectric material layer on the side wall and the bottom of the groove;
forming a second shielding gate dielectric material layer in the groove and on the upper surface of the graphical mask layer;
and removing the second shielding gate dielectric material on the upper surface of the patterned mask layer, and the part of the first shielding gate dielectric material layer and the part of the second shielding gate dielectric material layer in the groove to obtain a first shielding gate dielectric layer and a second shielding gate dielectric layer, wherein the first shielding gate dielectric layer and the second shielding gate dielectric layer jointly form the shielding gate dielectric layer.
In one embodiment, etching the shield gate dielectric layer to form a shield gate trench in the shield gate dielectric layer includes:
forming side walls in the grooves, wherein the side walls are positioned on the shielding grid dielectric layer, and openings are formed among the side walls;
and etching the shielding grid dielectric layer based on the side wall so as to form the shielding grid groove in the shielding grid dielectric layer.
In one embodiment, before forming the sidewall spacers in the trench, the method further includes: forming a sacrificial layer on the upper surface of the graphical mask layer, the exposed side wall of the groove and the upper surface of the shielding gate dielectric layer;
before the shielding gate dielectric layer is etched based on the side wall, the method further comprises the following steps: etching the sacrificial layer exposed by the opening based on the side wall;
after forming a shield grid in the shield grid groove and before forming a grid dielectric layer on the exposed surface of the shield grid and the exposed side wall of the groove, the method further comprises the following steps: removing the side wall;
after removing the side wall, still include: and removing the sacrificial layer and the patterned mask layer.
In one embodiment, forming a sidewall spacer in the trench includes:
forming a side wall material layer, wherein the side wall material layer covers the surface of the sacrificial layer and fills the groove;
and removing the side wall material layer positioned on the patterned mask layer, and back-etching the side wall material layer positioned in the groove to obtain the side wall.
In one embodiment, forming a gate dielectric layer on at least the exposed surface of the shield gate and the exposed sidewall of the trench includes:
and forming the grid dielectric layer on the exposed surface of the shielding grid, the exposed side wall of the groove and the upper surface of the semiconductor layer by adopting a thermal oxidation process.
In one embodiment, the thickness of the shielding gate dielectric layer at the bottom of the trench is greater than or equal to the thickness of the shielding gate dielectric layer at the sidewall of the trench.
In a second aspect, the invention further provides a shielded gate power device, which is prepared by using the preparation method of the shielded gate power device in the first aspect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technologies, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a conventional shielded gate trench MOSFET;
fig. 2 is a flow chart of a method of fabricating a shielded gate power device provided in an embodiment;
fig. 3 is a schematic cross-sectional structure diagram of a structure obtained in step S10 in the method for manufacturing a shielded gate power device provided in an embodiment;
fig. 4 is a schematic cross-sectional structure diagram of a structure obtained in step S20 in the method for manufacturing a shielded gate power device provided in an embodiment;
fig. 5 to fig. 7 are schematic cross-sectional structural diagrams of structures obtained in step S30 in the manufacturing method of the shielded gate power device provided in an embodiment;
fig. 8 to 9 are schematic cross-sectional structure diagrams of structures obtained in step S40 in the method for manufacturing a shielded gate power device provided in an embodiment;
fig. 10 is a schematic cross-sectional structure view of a structure obtained in step S50 in the method for manufacturing a shielded gate power device provided in an embodiment;
fig. 11 is a schematic cross-sectional structure view of a structure obtained in step S60 in the method for manufacturing a shielded gate power device provided in an embodiment;
fig. 12 is a schematic cross-sectional structure diagram of a structure obtained in step S70 in the manufacturing method of the shielded gate power device provided in an embodiment.
Description of reference numerals:
10. a semiconductor substrate; 11. a trench; 12. a shield gate; 13. shielding the gate dielectric layer; 14. isolating the dielectric layer; 15. a gate electrode; 16. a gate dielectric layer; 20. a semiconductor layer; 21. a trench; 22. patterning the mask layer; 221. a first graphical mask layer; 222. a second graphical mask layer; 23. shielding the gate dielectric layer; 231. a first shielding grid dielectric material layer; 232. a second shielding grid dielectric material layer; 233. a first shielding gate dielectric layer; 234. a second shielding grid dielectric layer; 24. a sacrificial layer; 25. a side wall; 26. an opening; 27. shielding the gate trench; 28. a shield gate; 29. a gate dielectric layer; 30. and a gate.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
The invention provides a preparation method of a shielded gate power device, as shown in fig. 2, the preparation method of the shielded gate power device may include the following steps:
s10: providing a semiconductor layer;
s20: forming a trench in the semiconductor layer;
s30: forming a shielding gate dielectric layer in the groove, wherein the upper surface of the shielding gate dielectric layer is lower than the top surface of the groove;
s40: etching the shielding gate dielectric layer to form a shielding gate groove in the shielding gate dielectric layer;
s50: forming a shielding grid electrode in the shielding grid groove, wherein the upper surface of the shielding grid electrode is not lower than the upper surface of the shielding grid dielectric layer;
s60: forming a grid dielectric layer on at least the exposed surface of the shielding grid and the exposed side wall of the groove;
s70: and forming a grid electrode in the groove, wherein the grid electrode is positioned on the shielding grid electrode.
According to the preparation method of the shielded gate power device, the shielded gate dielectric layer is formed in the groove, then the shielded gate dielectric layer is etched to form the shielded gate groove, the thickness of the shielded gate dielectric layer at the bottom of the groove can be controlled through an etching process, the thickness of the shielded gate dielectric layer at the bottom of the groove is larger than that of the shielded gate dielectric layer on the side wall of the groove, the tip of the bottom of the shielded gate can be eliminated, the electric field intensity can be reduced, the withstand voltage can be improved, and the device cannot be easily broken down at the bottom of the groove. Meanwhile, the thickness of the shielding gate dielectric layer at the bottom of the groove is controlled through an etching process, so that the thickness of the shielding gate dielectric layer at the bottom of the groove can be increased, the source-drain capacitance Cds of the device can be reduced, the switching speed of the device is improved, and the switching loss is reduced.
In step S10, please refer to step S10 in fig. 2 and fig. 3, a semiconductor layer 20 is provided.
As an example, the semiconductor layer 20 may be at least one doped layer, such as at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. The doping concentration range in the semiconductor layer 20 may be set according to actual conditions, and is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
In step S20, please refer to step S20 in fig. 2 and fig. 4, a trench 21 is formed in the semiconductor layer 20.
As an example, step S20 may include the steps of:
s201: forming a patterned mask layer 22 on the upper surface of the semiconductor layer 20, wherein the patterned mask layer 22 has an opening pattern (not shown), and the opening pattern defines the shape and position of the trench 21;
s202: the semiconductor layer 20 is etched based on the patterned mask layer 22 to form the trench 21 in the semiconductor layer 20, as shown in fig. 4.
As an example, step S201 may include the steps of:
s2011: forming a first mask layer (not shown) on the upper surface of the semiconductor layer 20;
s2012: forming a second mask layer (not shown) on the upper surface of the first mask layer;
s2013: the first mask layer and the second mask layer are patterned to obtain the patterned mask layer 22 comprising the first patterned mask layer 221 and the second patterned mask layer 222, as shown in fig. 4.
As an example, in step S2011, an oxide layer may be formed on the upper surface of the semiconductor layer 20 as the first mask layer by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The thickness of the first mask layer may be set according to actual needs, and is not limited herein.
As an example, in step S2012, a nitride layer may be formed on the upper surface of the first mask layer as the second mask layer by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The thickness of the second mask layer can be set according to actual needs, and is not limited herein; in this embodiment, the thickness of the second mask layer may be greater than the thickness of the first mask layer.
As an example step S2013 may comprise the steps of:
s20131: forming a photoresist layer (not shown) on the upper surface of the second mask layer;
s20132: exposing and reflecting the photoresist layer to form a patterned photoresist layer;
s20133: etching the second mask layer and the first mask layer based on the patterned photoresist layer to obtain the first patterned mask layer 221 and the second patterned mask layer 222;
s20134: and removing the patterned photoresist layer.
It should be noted that, in fig. 4, the patterned mask layer 22 includes the first patterned mask layer 221 and the second patterned mask layer 222 as an example, in other examples, the patterned mask layer 22 may also be a single-layer structure, for example, the patterned mask layer 22 may also be a patterned oxide layer or a patterned nitride layer, etc.
As an example, the depth of the trench 21 is smaller than the thickness of the semiconductor layer 20.
As an example, the longitudinal sectional shape of the groove 21 may be, but is not limited to, a U shape as shown in fig. 4, and the longitudinal sectional shape of the groove 21 may also be an inverted trapezoid, a rectangle, or the like.
As an example, the number of the grooves 21 formed in step S20 may be set according to actual needs, fig. 4 only takes the number of the grooves 21 as two as an example, and in other examples, the number of the grooves 21 is not limited to the number in fig. 4, and may be one, three, four, five, six or more, and so on.
In step S30, please refer to step S30 in fig. 2 and fig. 5 to 7, a shielding gate dielectric layer 23 is formed in the trench 21, and an upper surface of the shielding gate dielectric layer 23 is lower than a top surface of the trench 21.
As an example, step S30 may include the steps of:
s301: forming a first shield gate dielectric material layer 231 on the sidewall and bottom of the trench 21, as shown in fig. 5;
s302: forming a second shielding gate dielectric material layer 232 in the trench 21 and on the upper surface of the patterned mask layer 22, as shown in fig. 6;
s303: removing the second shielding gate dielectric material 232 on the upper surface of the patterned mask layer 22, a portion of the first shielding gate dielectric material layer 231 in the trench 21, and a portion of the second shielding gate dielectric material layer 232 to obtain a first shielding gate dielectric layer 233 and a second shielding gate dielectric layer 234, where the first shielding gate dielectric layer 233 and the second shielding gate dielectric layer 234 together form the shielding gate dielectric layer 23, as shown in fig. 7.
As an example, in step S301, an oxide layer may be formed on the sidewalls and the bottom of the trench 21 as the first shielding gate dielectric material layer 231 by using, but not limited to, a thermal oxidation process. The thickness of the first shielding gate dielectric material layer 231 may be set according to actual needs, and is not limited herein.
As an example, in step S302, an oxide layer may be deposited by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process as the second shielding gate dielectric material layer 232.
As an example, in step S303, the second shielding gate dielectric material layer 232 on the upper surface of the patterned mask layer 22 may be removed by using, but not limited to, a chemical mechanical polishing process or an etching process, and then a portion of the first shielding gate dielectric material layer 231 and a portion of the second shielding gate dielectric material layer 232 in the trench 21 are removed by using, but not limited to, a dry etching process, so as to obtain the first shielding gate dielectric layer 233 and the second shielding gate dielectric layer 234.
In step S40, referring to step S40 in fig. 2 and fig. 8 to 9, the shielding gate dielectric layer 23 is etched to form a shielding gate trench 27 in the shielding gate dielectric layer 23.
As an example, step S40 may include the steps of:
s401: forming side walls 25 in the trench 21, where the side walls 25 are located on the shield gate dielectric layer 23, and openings 26 are formed between the side walls 25, as shown in fig. 8;
s402: the shield gate dielectric layer 23 is etched based on the sidewall spacers 25 to form the shield gate trench 27 in the shield gate dielectric layer 23, as shown in fig. 9.
As an example, before step S401, the following steps may be further included:
and forming a sacrificial layer 24 on the upper surface of the patterned mask layer 22, the exposed side wall of the trench 21 and the upper surface of the shielding gate dielectric layer 23.
Specifically, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form an oxide layer on the upper surface of the patterned mask layer 22, the exposed sidewall of the trench 21, and the upper surface of the shield gate dielectric layer 23 as the sacrificial layer 24. The thickness of the sacrificial layer 24 can be set according to actual needs, and is not limited herein.
As an example, step S401 may include the steps of:
s4011: forming a side wall material layer (not shown) covering the surface of the sacrificial layer 24 and filling the trench 21; the side wall material layer can be formed by adopting but not limited to a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process; the spacer material layer may include, but is not limited to, nitride spacers, such as silicon nitride spacers and the like;
s4012: removing the side wall material layer on the patterned mask layer 22, and back-etching the side wall material layer in the trench 21 to obtain the side wall 24; specifically, the sidewall material layer on the patterned mask layer 22 may be removed by, but not limited to, a chemical mechanical polishing process or an etching process; and then, but not limited to, back-etching the side wall material layer in the trench 21 by using a dry etching process to obtain the side wall 24.
As an example, in step S402, the shielding gate dielectric layer 23 may be etched based on the sidewall spacers 25 by using, but not limited to, a dry etching process, so as to form the shielding gate trench 27 in the shielding gate dielectric layer 23. It should be noted that before the shield gate dielectric layer 23 is etched based on the sidewall spacers 25, a step of etching the sacrificial layer 24 exposed by the opening 26 based on the sidewall spacers 25 is further included.
As an example, after forming the shield gate trench 27, the thickness of the shield gate dielectric layer 23 at the bottom of the trench 21 may be greater than or equal to the thickness of the shield gate dielectric layer 23 at the sidewall of the trench 21. In this embodiment, the thickness of the shielding gate dielectric layer 23 located at the bottom of the trench 21 is greater than the thickness of the shielding gate dielectric layer 23 located on the sidewall of the trench 21.
It should be noted that, the shielding gate dielectric layer 23 is etched based on the sidewall 25 to form the shielding gate trench 27 in the shielding gate dielectric layer 23, the purpose of controlling the thickness of the shielding gate dielectric layer 23 at the bottom of the trench 21 can be achieved by controlling the etching process, the thickness of the shielding gate dielectric layer 23 at the bottom of the trench 21 can be made thicker than the thickness of the shielding gate dielectric layer 23 at the sidewall of the trench 21, and the tip of the subsequently formed shielding gate bottom can be eliminated, so that the electric field strength can be reduced, the withstand voltage can be improved, and the device is ensured not to be easily broken down at the bottom of the trench 21. Meanwhile, the thickness of the shielding gate dielectric layer 23 at the bottom of the trench 21 is controlled through an etching process, so that the thickness of the shielding gate dielectric layer 23 at the bottom of the trench 21 is increased, the source-drain capacitance Cds of the device can be reduced, the switching speed of the device is increased, and the switching loss is reduced.
In step S50, please refer to step S50 in fig. 2 and fig. 10, a shielding gate 28 is formed in the shielding gate trench 27, and an upper surface of the shielding gate 28 is not lower than an upper surface of the shielding gate dielectric layer 23.
As an example, step S50 may include the steps of:
s501: forming a shield gate material layer (not shown) in the trench 21, in the shield gate trench 27 and on the semiconductor layer 20; specifically, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like may be used, but not limited to, to form a shielding gate material layer in the trench 21 and on the semiconductor layer 20;
s502: removing the shield gate material layer on the semiconductor layer 20; specifically, the shielding gate material layer on the semiconductor layer 20 may be removed by, but not limited to, a chemical mechanical polishing process or an etching process;
s503: etching back to remove the shielding gate material layer in the trench 21 to obtain the shielding gate 28; specifically, the shielding gate material layer in the trench 21 may be etched back by, but not limited to, a dry etching process.
By way of example, the shield gate 28 may include, but is not limited to, a polysilicon shield gate.
As an example, after step S50, the following steps may be further included:
the side walls 25 are removed. Specifically, the sidewall 25 may be removed by, but not limited to, a dry etching process or a wet etching process.
As an example, after removing the sidewall 25, the method may further include: the sacrificial layer 24 and the patterned masking layer 22 are removed. Specifically, a dry etching process or a wet etching process may be used to remove the sacrificial layer 24 and the patterned mask layer 22; or, the sacrificial layer 24 and the patterned mask layer 22 on the upper surface of the patterned mask layer 22 may be removed by a chemical mechanical polishing process, and then the sacrificial layer 24 in the trench 21 may be removed by an etching process.
In step S60, referring to step S60 in fig. 2 and fig. 11, a gate dielectric layer 29 is formed on at least the exposed surface of the shield gate 28 and the exposed sidewall of the trench 21.
As an example, but not limited to, a thermal oxidation process may be performed to form an oxide layer on the exposed surface of the shield gate 28, the exposed sidewall of the trench 21, and the upper surface of the semiconductor layer 20 as the gate dielectric layer 29. The thickness of the gate dielectric layer 29 can be set according to actual needs, and is not limited herein.
In step S70, referring to step S70 in fig. 2 and fig. 12, a gate 30 is formed in the trench 21, and the gate 30 is located on the shield gate 29.
As an example, step S70 may include the steps of:
s701: forming a gate material layer (not shown) on the upper surface of the gate dielectric layer 29 inside the trench 21 and outside the trench 21; specifically, a polysilicon layer may be formed as the gate material layer by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
s702: removing the gate material layer on the upper surface of the gate dielectric layer 29 outside the trench 21, wherein the gate material layer remaining in the trench 21 is the gate 30; specifically, but not limited to, a chemical mechanical polishing process or an etching process may be used to remove the gate material layer on the upper surface of the gate dielectric layer 29 outside the trench 21.
As an example, the gate 30 may fill the trench 21 without voids.
As an example, after step S70, the following steps may be further included:
forming a body region (not shown) in the semiconductor layer 20, the body region being located at two opposite sides of the trench 21;
forming a source (not shown) in the body region;
forming a gate electrode (not shown), a source electrode (not shown), and a drain electrode (not shown), the gate electrode being electrically connected to the gate electrode 30; the source electrode penetrates through the source electrode and extends into the body region; the drain electrode is electrically connected to the lower surface of the semiconductor layer 10. Specifically, the drain electrode may be located on a lower surface of the semiconductor layer 10.
In another embodiment, with continued reference to fig. 2 to fig. 12, the present invention further provides a shielded gate power device, which can be prepared by the preparation method of the shielded gate power device in the above embodiment. The specific structure of the shielded gate power device can be seen from fig. 2 to 12 and the related text, which are not described herein again.
It should be understood that, although the steps in the flowcharts related to the embodiments are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the above embodiments may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (10)
1. A preparation method of a shielded gate power device is characterized by comprising the following steps:
providing a semiconductor layer;
forming a trench in the semiconductor layer;
forming a shielding gate dielectric layer in the groove, wherein the upper surface of the shielding gate dielectric layer is lower than the top surface of the groove;
etching the shielding gate dielectric layer to form a shielding gate groove in the shielding gate dielectric layer;
forming a shielding grid electrode in the shielding grid groove, wherein the upper surface of the shielding grid electrode is not lower than the upper surface of the shielding grid dielectric layer;
forming a grid dielectric layer on at least the exposed surface of the shielding grid and the exposed side wall of the groove;
and forming a grid electrode in the groove, wherein the grid electrode is positioned on the shielding grid electrode.
2. The method of claim 1, wherein forming a trench in the semiconductor layer comprises:
forming a patterned mask layer on the upper surface of the semiconductor layer, wherein an opening pattern is arranged in the patterned mask layer, and the opening pattern is defined into the shape and the position of the groove;
and etching the semiconductor layer based on the patterned mask layer so as to form the groove in the semiconductor layer.
3. The method of claim 2, wherein forming a patterned mask layer on the top surface of the semiconductor layer comprises:
forming a first mask layer on the upper surface of the semiconductor layer;
forming a second mask layer on the upper surface of the first mask layer;
and patterning the first mask layer and the second mask layer to obtain the patterned mask layer comprising the first patterned mask layer and the second patterned mask layer.
4. The method of claim 2, wherein forming a shield gate dielectric layer in the trench comprises:
forming a first shielding gate dielectric material layer on the side wall and the bottom of the groove;
forming a second shielding gate dielectric material layer in the groove and on the upper surface of the graphical mask layer;
and removing the second shielding gate dielectric material on the upper surface of the patterned mask layer, and the part of the first shielding gate dielectric material layer and the part of the second shielding gate dielectric material layer in the groove to obtain a first shielding gate dielectric layer and a second shielding gate dielectric layer, wherein the first shielding gate dielectric layer and the second shielding gate dielectric layer jointly form the shielding gate dielectric layer.
5. The method of claim 2, wherein etching the shield gate dielectric layer to form a shield gate trench in the shield gate dielectric layer comprises:
forming side walls in the grooves, wherein the side walls are positioned on the shielding grid dielectric layer, and openings are formed among the side walls;
and etching the shielding grid dielectric layer based on the side wall so as to form the shielding grid groove in the shielding grid dielectric layer.
6. The method of manufacturing a shielded gate power device according to claim 5,
before forming a side wall in the trench, the method further includes: forming a sacrificial layer on the upper surface of the graphical mask layer, the exposed side wall of the groove and the upper surface of the shielding gate dielectric layer;
before the shielding gate dielectric layer is etched based on the side wall, the method further comprises the following steps: etching the sacrificial layer exposed by the opening based on the side wall;
after forming the shielding grid in the shielding grid groove, at least before forming a grid dielectric layer on the exposed surface of the shielding grid and the exposed side wall of the groove, the method further comprises the following steps: removing the side wall;
after removing the side wall, still include: and removing the sacrificial layer and the patterned mask layer.
7. The method of claim 6, wherein forming a sidewall in the trench comprises:
forming a side wall material layer, wherein the side wall material layer covers the surface of the sacrificial layer and fills the groove;
and removing the side wall material layer positioned on the patterned mask layer, and back-etching the side wall material layer positioned in the groove to obtain the side wall.
8. The method of claim 5, wherein forming a gate dielectric layer on at least the exposed surface of the shield gate and the exposed sidewall of the trench comprises:
and forming the grid dielectric layer on the exposed surface of the shielding grid, the exposed side wall of the groove and the upper surface of the semiconductor layer by adopting a thermal oxidation process.
9. The method for manufacturing the shielded gate power device according to any one of claims 1 to 8, wherein the thickness of the shielded gate dielectric layer at the bottom of the trench is greater than or equal to the thickness of the shielded gate dielectric layer at the sidewall of the trench.
10. A shielded gate power device, wherein the shielded gate power device is prepared by the preparation method of any one of claims 1 to 9.
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| US20190123158A1 (en) * | 2016-03-31 | 2019-04-25 | Shindengen Electric Manufacturing Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device |
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| CN101299436A (en) * | 2007-04-30 | 2008-11-05 | 万国半导体股份有限公司 | Device structure and manufacturing method using hdp deposited source-body implant block |
| US20190123158A1 (en) * | 2016-03-31 | 2019-04-25 | Shindengen Electric Manufacturing Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device |
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