CN115934027A - Add-subtract switching circuit and electronic equipment - Google Patents
Add-subtract switching circuit and electronic equipment Download PDFInfo
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- CN115934027A CN115934027A CN202310063065.XA CN202310063065A CN115934027A CN 115934027 A CN115934027 A CN 115934027A CN 202310063065 A CN202310063065 A CN 202310063065A CN 115934027 A CN115934027 A CN 115934027A
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Abstract
The present invention relates to an addition-subtraction switching circuit having a simple structure and capable of obtaining an ideal result signal even if the voltage values of two voltage signals to be added or subtracted are unknown values that vary within an unknown range, and an electronic apparatus having the same. The add-subtract switching circuit comprises an operational amplifier module, six resistors with the same resistance value and two optical switching devices which are connected and matched in a specified mode. Moreover, the addition and subtraction switching circuit can perform the switching of addition and subtraction operations only by adjusting one path of control signal.
Description
Technical Field
The application relates to the technical field of signal processing, in particular to an add-subtract switching circuit and electronic equipment.
Background
In signal processing, it is often necessary to add or subtract two voltage signals to obtain a desired resultant signal.
In the related art, the addition operation circuit and the subtraction operation circuit are relatively independent, and a large number of electronic devices are required, so that the integration level is not high.
In addition, in practical applications, at least one of the two voltage signals to be added or subtracted is usually an unknown signal, and the voltage value of the unknown signal may be large or small, and is often a variable square wave signal, so if a general P-type or N-type field effect switching tube is used to build the addition circuit or the subtraction circuit, there may be a case that the field effect switching tube cannot be normally turned on or off because the voltage value of the voltage signal to be calculated is high or low, and thus the result signal cannot be accurately obtained. In addition, the add-subtract switching circuit proposed by the related art has a complicated structure.
Disclosure of Invention
In view of the above, the present application provides an add-subtract switching circuit and an electronic device having the same, which are simple in structure and can obtain an ideal result signal even if the voltage values of two voltage signals to be added or subtracted are unknown values that vary within an unknown range.
In a first aspect, the present application provides an add/subtract switching circuit for a resulting voltage signal obtained by adding or subtracting a second voltage signal and a first voltage signal, the add/subtract switching circuit comprising:
the operational amplifier module is provided with a same-phase input pin, a reverse input pin and an output pin, and the output pin is used for outputting the result voltage signal;
a first resistor having opposite first and second ends, the first end for receiving the first voltage signal;
a second resistor having a third end and a fourth end which are opposite to each other, wherein the third end is connected to the inverting input pin, and the fourth end is connected to the output pin;
a first optical switch device, the second terminal being connected to the third terminal via the first optical switch device;
a third resistor having a fifth terminal and a sixth terminal opposite to each other, the fifth terminal being connected to the first optical switch device, and the sixth terminal being grounded;
a fourth resistor having a seventh end and an eighth end opposite to each other, the seventh end being connected to the first end for receiving the first voltage signal;
a fifth resistor having a ninth terminal and a tenth terminal opposite to each other, the ninth terminal being configured to receive the second voltage signal, and the tenth terminal being connected to the non-inverting input pin;
a second optical switch device, the eighth terminal being connected to the tenth terminal via the second optical switch device;
a sixth resistor having opposite eleventh and twelfth terminals, the eleventh terminal being connected to the second optical switch device, the twelfth terminal being grounded;
the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor have the same resistance value, and the first optical switch device and the second optical switch device are controlled by the same control signal;
the first optical switching device is configured to: in response to the control signal being at a high level, conducting the second terminal with the third terminal, and disconnecting the third terminal with the fifth terminal; in response to the control signal being at a low level, disconnecting the second terminal from the third terminal, and connecting the third terminal with the fifth terminal;
the second optical switching device is configured to: in response to the control signal being at a high level, disconnecting the eighth terminal from the tenth terminal and connecting the tenth terminal with the eleventh terminal; and in response to the control signal being at a low level, conducting the eighth terminal and the tenth terminal, and disconnecting the tenth terminal and the eleventh terminal.
In one possible embodiment, the first optical switching device includes:
a first shell body which is provided with a first opening,
a first light emitting diode, a second light emitting diode, a first photoelectric switch tube and a second photoelectric switch tube which are packaged in the first shell,
is led out from the anode of the first light-emitting diode to a first pin outside the first shell,
is led out from the cathode of the first light-emitting diode to a second pin outside the first shell,
is led out from the anode of the second light-emitting diode to a third pin outside the first shell,
is led out from the cathode of the second light-emitting diode to a fourth pin outside the first shell,
a fifth pin and a sixth pin which are led out of the first photoelectric switch tube to the outside of the first shell,
a seventh pin and an eighth pin which are led out of the first shell from the second photoelectric switch tube;
the first light-emitting diode corresponds to the first photoelectric switching tube, and the second light-emitting diode corresponds to the second photoelectric switching tube;
the first pin and the fourth pin are respectively used for receiving the control signal, the second pin is grounded, the fifth pin is connected with the second end, the sixth pin is respectively connected with the third end and the seventh pin, and the eighth pin is connected with the fifth end;
the third pin is used for connecting a system voltage source to receive a level signal, and the level value of the level signal is higher than the level value of the low level and is not higher than the level value of the high level.
In one possible embodiment, the seventh pin is connected to ground via a first capacitor.
In one possible embodiment, the second optical switching device includes:
a second shell body which is provided with a plurality of holes,
a third light emitting diode, a fourth light emitting diode, a third photoelectric switch tube and a fourth photoelectric switch tube which are packaged in the second shell,
is led out from the anode of the third light-emitting diode to a ninth pin outside the second shell,
is led out from the cathode of the third light-emitting diode to a tenth pin outside the second shell,
is led out from the anode of the fourth light-emitting diode to an eleventh pin outside the second shell,
is led out from the cathode of the fourth light-emitting diode to a twelfth pin outside the second shell,
a thirteenth pin and a fourteenth pin which are led out of the third photoelectric switch tube to the outside of the first shell,
a fifteenth pin and a sixteenth pin which are led out of the first shell from the fourth photoelectric switch tube;
the third light emitting diode corresponds to the third photoelectric switching tube, and the fourth light emitting diode corresponds to the fourth photoelectric switching tube;
the tenth pin and the eleventh pin are respectively used for receiving the control signal, the twelfth pin is grounded, the thirteenth pin is connected with the eighth end, the fourteenth pin is respectively connected with the tenth end and the fifteenth pin, and the sixteenth pin is connected with the tenth end.
Wherein the ninth pin is for connecting the system voltage source to receive the level signal from the system voltage source.
In one possible embodiment, the fifteenth pin is grounded via a second capacitor.
In a possible implementation manner, the operational amplifier module, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the first optical switch device, and the second optical switch device are disposed on a same PCB.
In a possible embodiment, the PCB board is provided with:
a first voltage signal access terminal connected to the first end,
a second voltage signal access terminal connected to the seventh terminal, an
And a voltage signal output terminal connected to the output pin.
In a possible implementation manner, a system voltage source access terminal is disposed on the PCB, and the system voltage source access terminal is connected to the third pin and the ninth pin respectively.
In a second aspect, the present application provides an electronic device, which includes the add-subtract switching circuit as described in the first aspect.
In one possible embodiment, the electronic device includes a protective housing that houses the add-drop switching circuit entirely within it.
According to the addition-subtraction switching circuit provided by the application, the structure is simple, and even if the voltage values of two voltage signals to be added or subtracted are unknown values which change in an unknown range, an ideal result signal can be obtained. Moreover, the addition and subtraction switching circuit can perform the switching of addition and subtraction operations only by adjusting one path of control signal.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.
Fig. 1 is a schematic structural diagram of an add-drop switching circuit according to an embodiment of the present application.
Fig. 2 is a simplified diagram of the add-subtract switching circuit of fig. 1 in a subtraction state.
Fig. 3 is a simplified diagram of the add-subtract switching circuit shown in fig. 1 in an addition state.
Fig. 4 is a schematic structural view of the first optical switching device of fig. 1.
Fig. 5 is a schematic structural view of the second optical switching device of fig. 1.
Description of reference numerals:
an OP-operational amplifier module;
u1-a first optical switch device, U2-a second optical switch device;
r1-a first resistor, R2-a second resistor, R3-a third resistor, R4-a fourth resistor, R5-a fifth resistor, and R6-a sixth resistor;
m1-a first shell, M2-a second shell;
s1-a first pin, S2-a second pin, S3-a third pin, S4-a fourth pin, S5-a fifth pin, S6-a sixth pin, S7-a seventh pin, S8-an eighth pin, S9-a ninth pin, S10-a tenth pin, S11-an eleventh pin, S12-a twelfth pin, S13-a thirteenth pin, S14-a fourteenth pin, S15-a fifteenth pin, S16-a sixteenth pin;
d1-a first light emitting diode, D2-a second light emitting diode, D3-a third light emitting diode, and D4-a fourth light emitting diode;
k1-a first photoelectric switching tube, K2-a second photoelectric switching tube, K3-a first photoelectric switching tube and K4-a second photoelectric switching tube;
c1-a first capacitor, C2-a second capacitor;
VREF-a first voltage signal, VIN-a second voltage signal, VOUT-a resulting voltage signal;
EN-control signal, VSYS-system voltage source.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings of the embodiments of the present application. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the application without any inventive step, are within the scope of protection of the application. It will be understood that some of the technical means of the various embodiments described herein may be replaced or combined with each other without conflict.
In the description of the present application and claims, the terms "first," "second," and the like, if any, are used solely to distinguish one from another as between described objects and not necessarily in any sequential or technical sense. Thus, an object defined as "first," "second," etc. may explicitly or implicitly include one or more of the object. Also, the use of the terms "a" or "an" and the like, do not denote a limitation of quantity, but rather denote the presence of at least one.
Fig. 1 shows an embodiment of an add-subtract switching circuit of the present application, which is used for adding or subtracting a second voltage signal VIN and a first voltage signal VREF to obtain a resultant voltage signal, in an application scenario, a voltage value (or level value) of the second voltage signal VIN is a constant voltage value, and a voltage value of the first voltage signal VREF is an adjustable value.
The add-subtract switching circuit comprises an operational amplifier module OP, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first optical switch device U1 and a second optical switch device U2.
The operational amplifier module OP is provided with a non-inverting input pin, an inverting input pin and an output pin, wherein the output pin is used for outputting the result voltage signal VOUT obtained after operation.
The first resistor R1 has a first end and a second end opposite to each other, wherein the first end is used for receiving the first voltage signal VREF. In fig. 1, the first terminal is a right end of the first resistor R1, and the second terminal is a left end of the first resistor R1.
The second resistor R2 has a third end and a fourth end opposite to each other, wherein the third end is connected to the inverting input pin of the operational amplifier module OP, and the fourth end is connected to the output pin of the operational amplifier module OP. In fig. 1, the third terminal is the left terminal of the second resistor R2, and the fourth terminal is the right terminal of the second resistor R2.
The third resistor R3 has a fifth end and a sixth end opposite to each other, wherein the fifth end is connected to the first optical switch device U1, and the sixth end is grounded. In fig. 1, the fifth terminal is the left terminal of the third resistor R3, and the sixth terminal is the right terminal of the third resistor R3.
The fourth resistor R4 has a seventh terminal and an eighth terminal opposite to each other, wherein the seventh terminal is connected to the first terminal of the first resistor R1, so as to be able to receive the first voltage signal VREF as well. In fig. 1, the seventh terminal is the right terminal of the fourth resistor R4, and the eighth terminal is the left terminal of the fourth resistor R4.
The fifth resistor R5 has a ninth end and a tenth end opposite to each other, wherein the ninth end is used for receiving the second voltage signal VIN, and the tenth end is connected to the non-inverting input pin of the operational amplifier module OP. In fig. 1, the ninth terminal is the left terminal of the fifth resistor R5, and the tenth terminal is the right terminal of the fifth resistor R5.
The sixth resistor R6 has an eleventh terminal and a twelfth terminal opposite to each other, wherein the eleventh terminal is connected to the second optical switch device U2, and the twelfth terminal is grounded. In fig. 1, the eleventh terminal is a left terminal of the sixth resistor R6, and the twelfth terminal is a right terminal of the sixth resistor R6.
The first optical switch device U1 connects the second terminal of the first resistor R1 and the third terminal of the second resistor R2 in a disconnectable manner, in other words, the second terminal of the first resistor R1 is connected to the third terminal of the second resistor R2 via the first optical switch device U1.
The second optical switch device U2 disconnectably connects the eighth terminal of the fourth resistor R4 with the tenth terminal of the fifth resistor R5, in other words, the eighth terminal of the fourth resistor R4 is connected to the tenth terminal of the fifth resistor R5 via the second optical switch device U2.
The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 have the same resistance, i.e., R1= R2= R3= R4= R5= R6 (in this equation, each algebraic number represents the resistance of the corresponding resistor).
The first optical switch device U1 and the second optical switch device U2 are controlled by the same control signal EN.
The first optical switching device U1 is configured to: in response to the control signal EN being at a high level, turning on the second terminal of the first resistor R1 and the third terminal of the second resistor R2, and turning off the third terminal of the second resistor R2 and the fifth terminal of the third resistor R3; in response to the control signal EN being at a low level, the second terminal of the first resistor R1 is disconnected from the third terminal of the second resistor R2, and the third terminal of the second resistor R2 is connected to the fifth terminal of the third resistor R3.
The second optical switching device U2 is configured to: in response to the control signal EN being at a high level, disconnecting the eighth terminal of the fourth resistor R4 from the tenth terminal of the fifth resistor R5, and connecting the tenth terminal of the fifth resistor R5 with the eleventh terminal of the sixth resistor R6; in response to the control signal EN being at a low level, the eighth terminal of the fourth resistor R4 and the tenth terminal of the fifth resistor R5 are turned on, and the tenth terminal of the fifth resistor R5 and the eleventh terminal of the sixth resistor R6 are turned off.
Now, referring to fig. 1 in conjunction with fig. 2 and fig. 3, the operation principle of the add-subtract switching circuit is described as follows:
when the control signal EN applied to the first optical switch device U1 and the second optical switch device U2 is at a high level, the first optical switch device U1 turns on the second terminal of the first resistor R1 and the third terminal of the second resistor R2, and turns off the third terminal of the second resistor R2 and the fifth terminal of the third resistor R3, and the second optical switch device U2 turns off the eighth terminal of the fourth resistor R4 and the tenth terminal of the fifth resistor R5, and turns on the tenth terminal of the fifth resistor R5 and the eleventh terminal of the sixth resistor R6. At this time, the add-subtract switching circuit in fig. 1 can be simplified to the state shown in fig. 2.
In fig. 2, R1= R2= R5= R6, the voltage at the non-inverting input terminal of the operational amplifier module OP is VIN/2, and the voltage at the inverting input terminal is also VIN/2 according to the electrical characteristics of the operational amplifier module OP itself, so as to make the voltage at the inverting input terminal reach VIN/2, an equation is obtained: (VIN/2-VREF)/R1 = (VOUT-VIN/2)/R2, and since R1= R2, VOUT = VIN-VREF can be obtained. Therefore, the addition and subtraction switching circuit works in a subtraction operation state at this time.
When the control signal EN applied to the first optical switch device U1 and the second optical switch device U2 is at a low level, the first optical switch device U1 disconnects the second terminal of the first resistor R1 from the third terminal of the second resistor R2, and connects the third terminal of the second resistor R2 with the fifth terminal of the third resistor R3, and the second optical switch device U2 connects the eighth terminal of the fourth resistor R4 with the tenth terminal of the fifth resistor R5, and disconnects the tenth terminal of the fifth resistor R5 from the eleventh terminal of the sixth resistor R6. At this time, the add-subtract switching circuit in fig. 1 can be simplified to the state shown in fig. 3.
In fig. 3, R2= R3= R4= R5, the voltage of the non-inverting input terminal of the operational amplifier module OP is (VIN + VREF)/2, the voltage of the inverting input terminal is also (VIN + VREF)/2 according to the electrical characteristics of the operational amplifier module OP itself, and based on the voltage of the inverting input terminal is (VIN + VREF)/2, an equation is obtained: (VIN + VREF)/(2 × R3) = (VOUT- (VIN + VREF)/2)/R2, and since R2= R3, it is possible to derive VOUT = VIN + VREF. It can be seen that the add/subtract switching circuit operates in an addition state at this time.
Referring to fig. 4 in combination with fig. 1, the first optical switch device U1 includes a first housing M1, a first light emitting diode D1, a second light emitting diode D2, a first photoelectric switch tube K1, a second photoelectric switch tube K2, a first pin S1, a second pin S2, a third pin S3, a fourth pin S4, a fifth pin S5, a sixth pin S6, a seventh pin S7, and an eighth pin S8.
The first light emitting diode D1, the second light emitting diode D2, the first photoelectric switching tube K1 and the second photoelectric switching tube K2 are completely encapsulated in the first casing M1. The first pin S1 is led out of the first housing M1 from the anode of the first light emitting diode D1. The second pin S2 is led out of the first casing M1 from the cathode of the first light emitting diode D1. The third pin S3 is led out of the first casing M1 from the anode of the second light emitting diode D2. The fourth pin S4 is led out of the first casing M1 from the cathode of the second led D2. The fifth pin S5 and the sixth pin S6 are respectively led out of the two poles of the first photoelectric switching tube K1 to the outside of the first casing M1. The seventh pin S7 and the eighth pin S8 are respectively led out of the two poles of the second photoelectric switching tube K2 to the outside of the first casing M1.
The first light emitting diode D1 corresponds to the first photoelectric switch tube K1, and the second light emitting diode D2 corresponds to the second photoelectric switch tube K2. That is, when the first light emitting diode D1 does not emit light, the first photo switch tube K1 is in an off state; when the first light emitting diode D1 is powered on to emit light, the first photoelectric switching tube K1 receives the light signal and is turned on. When the second light-emitting diode D2 does not emit light, the second photoelectric switch tube K2 is in a disconnected state; when the second light emitting diode D2 is powered on to emit light, the second photoelectric switch tube K2 receives the optical signal and is turned on.
The first pin S1 and the fourth pin S4 are respectively configured to receive the control signal EN, the second pin S2 is grounded, the fifth pin S5 is connected to the second end of the first resistor R1, the sixth pin S6 is connected to the third end of the second resistor R2, the sixth pin S6 is connected to the seventh pin S7 through a vertical short line at the upper portion in fig. 1 (so that the sixth pin S6 is electrically connected to the seventh pin S7 all the time), and the eighth pin S8 is connected to the fifth end of the third resistor R3. The third pin S3 is used to connect the system voltage source VSYS to receive a stable level signal from the system voltage source VSYS, the level value of which is higher than that of the low-level control signal EN and the level value of which is not higher than that of the high-level control signal EN. For example, the level value provided by the system voltage source VSYS may be a constant 3.3V, and the level value of the control signal EN in the high state is 3.3V or less.
When the control signal EN is at a high level, the first light emitting diode D1 is powered on to emit light, and the corresponding first photoelectric switch tube K1 is turned on when receiving illumination, so that the fifth pin S5 and the sixth pin S6 are turned on, and the first resistor R1 and the second resistor R2 are turned on. Meanwhile, the level value of the high-level control signal EN is not lower than the level value of the level signal provided by the system voltage source VSYS, so the anode potential of the second light emitting diode D2 is not higher than the cathode potential, and the second light emitting diode D2 does not emit light, so the second photoelectric switch tube K2 is in a disconnected state, the seventh pin S7 and the eighth pin S8 are disconnected, and the second resistor R2 and the third resistor R3 are disconnected
When the control signal EN is at a low level (e.g., zero), the voltage potential at both ends of the first light emitting diode D1 is equal and does not emit light, the corresponding first photoelectric switch tube K1 is in an off state, and the first resistor R1 and the second resistor R2 are disconnected. Meanwhile, at two ends of the second light emitting diode D2, the level value of the low level control signal EN is lower than the level signal provided by the system voltage source VSYS, and the anode potential is higher than the cathode potential, so that the second light emitting diode D2 is electrified to emit light, and the second photoelectric switch tube K2 is conducted after receiving illumination, so that the seventh pin S7 and the eighth pin S8 are conducted, and further the second resistor R2 and the third resistor R3 are conducted.
To obtain the filtering effect, the present embodiment connects the seventh pin S7 to ground via the first capacitor C1.
Referring to fig. 5 in combination with fig. 1, the second optical switch device U2 has a structure substantially the same as that of the first optical switch device U1, and includes a second casing M2, a third light emitting diode D3, a fourth light emitting diode D4, a third photoelectric switch tube K3, a fourth photoelectric switch tube K4, a ninth pin S9, a tenth pin S10, an eleventh pin S11, a twelfth pin S12, a thirteenth pin S13, a fourteenth pin S14, a fifteenth pin S15, and a sixteenth pin S16.
The third light emitting diode D3, the fourth light emitting diode D4, the third photoelectric switching tube K3 and the fourth photoelectric switching tube K4 are completely encapsulated in the second casing M2. The ninth pin S9 is led out of the second casing M2 from the anode of the third light emitting diode D3. The tenth pin S10 is led out of the second casing M2 from the cathode of the third led D3. The eleventh pin S11 is led out of the second casing M2 from the anode of the fourth light emitting diode D4. The twelfth pin S12 is led out of the second casing M2 from the cathode of the fourth light emitting diode D4. The thirteenth pin S13 and the fourteenth pin S14 are respectively led out of the second casing M2 from the two poles of the third photoelectric switching tube K3. The fifteenth pin S15 and the sixteenth pin S16 are respectively led out from the two poles of the fourth photoelectric switching tube K4 to the outside of the second casing M2.
The tenth pin S10 and the eleventh pin S11 are respectively configured to receive the aforementioned control signal EN, the twelfth pin S12 is grounded, the thirteenth pin S13 is connected to the eighth end of the fourth resistor R4, the fourteenth pin S14 is connected to the tenth end of the fifth resistor R5, the fourteenth pin S14 and the fifteenth pin S15 are connected through a vertical short line at the bottom in fig. 1, and the sixteenth pin S16 is connected to the tenth end. The ninth pin S9 is also used to connect the aforementioned system voltage source VSYS to receive the aforementioned level signal from the system voltage source VSYS.
When the control signal EN is at a high level, the level values provided by the control signal EN at the high level and the system voltage source VSYS at the cathode terminal and the anode terminal of the third light emitting diode respectively are not higher than the level signal of the control signal, so that the third light emitting diode does not emit light, and therefore, the third photoelectric switch tube is in an off state, the thirteenth pin S13 and the fourteenth pin S14 are off, and the fourth resistor R4 is off from the fifth resistor R5. Meanwhile, the two ends of the fourth photodiode are electrified to emit light due to potential difference, and the corresponding fourth photoelectric switch tube is conducted due to illumination, so that the fifteenth pin S15 and the sixteenth pin S16 are conducted, and the fifth resistor R5 and the sixth resistor R6 are conducted.
When the control signal EN is at a low level (e.g., zero), at two ends of the third led, the control signal EN at the low level has a potential difference with a level signal provided by the system voltage source VSYS, and the anode potential is higher than the cathode potential, so that the third led is energized to emit light, and the third photo-switch tube is turned on by illumination, so that the thirteenth pin S13 and the fourteenth pin S14 are turned on, and the fourth resistor R4 and the fifth resistor R5 are turned on. In this case, the potential across the fourth led is equal and does not emit light, the corresponding fourth photo switch is turned off, and the fifth resistor R5 and the sixth resistor R6 are turned off.
In order to obtain the filtering effect, the present embodiment connects the fifteenth pin S15 to the ground via the second capacitor C2.
The operational amplifier module OP, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first optical switch device U1 and the second optical switch device U2 may be disposed on a same small-area PCB board, and a first voltage signal VREF access terminal, a voltage signal output terminal and a system voltage source VSYS access terminal are disposed on the PCB board. The first voltage signal VREF input terminal, which is an input terminal of the first voltage signal VREF, is connected to the first end of the first resistor R1, and thereby also to the seventh end of the fourth resistor R4. A second voltage signal VIN input terminal, which is an input terminal of the second voltage signal VIN, is connected to a ninth terminal of the fifth resistor R5. The voltage signal output terminal, which is the output terminal of the aforementioned resultant voltage signal VOUT, is connected to the output pin of the operational amplifier module OP. The system voltage source VSYS access terminal is used as an access terminal of the level signal provided by the system voltage source VSYS and is respectively connected with the third pin S3 and the ninth pin S9. In this way, the add-drop switching circuit is made to be an independent electrical component, thereby enabling flexible attachment in various circuit systems.
In addition, the embodiment of the application further provides electronic equipment which comprises the addition and subtraction switching circuit. The electronic device may include a protective case that houses all of the add-subtract switching circuit therein.
Claims (10)
1. An addition-subtraction switching circuit for adding or subtracting a second voltage signal and a first voltage signal to obtain a resultant voltage signal, the addition-subtraction switching circuit comprising:
the operational amplifier module is provided with a same-phase input pin, a reverse input pin and an output pin, and the output pin is used for outputting the result voltage signal;
a first resistor having opposite first and second ends, the first end for receiving the first voltage signal;
a second resistor having a third terminal and a fourth terminal opposite to each other, the third terminal being connected to the inverting input pin, and the fourth terminal being connected to the output pin;
a first optical switching device, the second terminal being connected to the third terminal via the first optical switching device;
a third resistor having a fifth end and a sixth end opposite to each other, the fifth end being connected to the first optical switch device, and the sixth end being grounded;
a fourth resistor having a seventh end and an eighth end opposite to each other, the seventh end being connected to the first end for receiving the first voltage signal;
a fifth resistor having a ninth terminal and a tenth terminal opposite to each other, the ninth terminal being configured to receive the second voltage signal, and the tenth terminal being connected to the non-inverting input pin;
a second optical switch device, the eighth terminal being connected to the tenth terminal via the second optical switch device;
a sixth resistor having opposite eleventh and twelfth terminals, the eleventh terminal being connected to the second optical switch device, the twelfth terminal being grounded;
the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor have the same resistance value, and the first optical switch device and the second optical switch device are controlled by the same control signal;
the first optical switching device is configured to: in response to the control signal being at a high level, conducting the second terminal with the third terminal, and disconnecting the third terminal with the fifth terminal; in response to the control signal being at a low level, disconnecting the second terminal from the third terminal, and connecting the third terminal with the fifth terminal;
the second optical switching device is configured to: in response to the control signal being at a high level, disconnecting the eighth terminal from the tenth terminal and connecting the tenth terminal with the eleventh terminal; and in response to the control signal being at a low level, conducting the eighth terminal and the tenth terminal, and disconnecting the tenth terminal and the eleventh terminal.
2. A plus-minus switching circuit according to claim 1, wherein said first optical switching device comprises:
a first shell body which is provided with a first opening,
a first light emitting diode, a second light emitting diode, a first photoelectric switch tube and a second photoelectric switch tube which are packaged in the first shell,
a first pin led out of the first housing from an anode of the first light emitting diode,
is led out from the cathode of the first light-emitting diode to a second pin outside the first shell,
is led out from the anode of the second light-emitting diode to a third pin outside the first shell,
is led out from the cathode of the second light-emitting diode to a fourth pin outside the first shell,
a fifth pin and a sixth pin which are led out of the first photoelectric switch tube to the outside of the first shell,
a seventh pin and an eighth pin which are led out of the first shell from the second photoelectric switching tube;
the first light-emitting diode corresponds to the first photoelectric switching tube, and the second light-emitting diode corresponds to the second photoelectric switching tube;
the first pin and the fourth pin are respectively used for receiving the control signal, the second pin is grounded, the fifth pin is connected with the second end, the sixth pin is respectively connected with the third end and the seventh pin, and the eighth pin is connected with the fifth end;
wherein the third pin is to connect a system voltage source to receive a level signal from the system voltage source, a level value of the level signal being higher than a level value of the low level and not higher than a level value of the high level.
3. The add-subtract switching circuit according to claim 2, wherein the seventh pin is connected to ground via a first capacitor.
4. An add-drop switching circuit according to claim 2, wherein said second optical switching device comprises:
a second shell body which is provided with a plurality of holes,
a third light emitting diode, a fourth light emitting diode, a third photoelectric switch tube and a fourth photoelectric switch tube which are packaged in the second shell,
is led out from the anode of the third light-emitting diode to a ninth pin outside the second shell,
is led out from the cathode of the third light-emitting diode to a tenth pin outside the second shell,
is led out from the anode of the fourth light-emitting diode to an eleventh pin outside the second shell,
is led out from the cathode of the fourth light-emitting diode to a twelfth pin outside the second shell,
a thirteenth pin and a fourteenth pin which are led out of the third photoelectric switch tube to the outside of the first shell,
a fifteenth pin and a sixteenth pin which are led out of the first shell from the fourth photoelectric switch tube;
the third light emitting diode corresponds to the third photoelectric switching tube, and the fourth light emitting diode corresponds to the fourth photoelectric switching tube;
the tenth pin and the eleventh pin are respectively used for receiving the control signal, the twelfth pin is grounded, the thirteenth pin is connected with the eighth end, the fourteenth pin is respectively connected with the tenth end and the fifteenth pin, and the sixteenth pin is connected with the tenth end;
wherein the ninth pin is for connecting the system voltage source to receive the level signal from the system voltage source.
5. The add-subtract switching circuit according to claim 4, wherein the fifteenth pin is connected to ground via a second capacitor.
6. The add-subtract switching circuit of claim 4, wherein the operational amplifier module, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the first optical switch device and the second optical switch device are arranged on a same PCB.
7. The add-subtract switching circuit according to claim 6, wherein the PCB board is provided with:
a first voltage signal access terminal connected to the first end,
a second voltage signal access terminal connected to the seventh terminal, an
And the voltage signal output terminal is connected with the output pin.
8. The add-subtract switching circuit as claimed in claim 7, wherein the PCB board is provided with system voltage source access terminals, and the system voltage source access terminals are respectively connected with the third pin and the ninth pin.
9. An electronic device comprising the add-subtract switching circuit according to any one of claims 1 to 8.
10. The electronic device of claim 9, wherein the electronic device comprises a protective housing that houses the add-subtract switching circuit entirely within the protective housing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310063065.XA CN115934027B (en) | 2023-01-16 | 2023-01-16 | Addition and subtraction switching circuit and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310063065.XA CN115934027B (en) | 2023-01-16 | 2023-01-16 | Addition and subtraction switching circuit and electronic equipment |
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| CN115934027A true CN115934027A (en) | 2023-04-07 |
| CN115934027B CN115934027B (en) | 2023-05-23 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150170760A1 (en) * | 2013-12-17 | 2015-06-18 | Intermolecuarl Inc. | Resistive Switching Sample and Hold |
| CN213068994U (en) * | 2020-08-07 | 2021-04-27 | 河南翔宇医疗设备股份有限公司 | Acquisition circuit and detection device of two-way symmetrical analog voltage signal |
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2023
- 2023-01-16 CN CN202310063065.XA patent/CN115934027B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150170760A1 (en) * | 2013-12-17 | 2015-06-18 | Intermolecuarl Inc. | Resistive Switching Sample and Hold |
| CN213068994U (en) * | 2020-08-07 | 2021-04-27 | 河南翔宇医疗设备股份有限公司 | Acquisition circuit and detection device of two-way symmetrical analog voltage signal |
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| CN115934027B (en) | 2023-05-23 |
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