CN115934027B - Addition and subtraction switching circuit and electronic equipment - Google Patents
Addition and subtraction switching circuit and electronic equipment Download PDFInfo
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- CN115934027B CN115934027B CN202310063065.XA CN202310063065A CN115934027B CN 115934027 B CN115934027 B CN 115934027B CN 202310063065 A CN202310063065 A CN 202310063065A CN 115934027 B CN115934027 B CN 115934027B
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Abstract
The application relates to an add-subtract switching circuit with a simple structure and an electronic device with the same, and the add-subtract switching circuit can obtain an ideal result signal even if the voltage values of two voltage signals to be added or subtracted are unknown values which change in an unknown range. The add-drop switching circuit comprises an operational amplifier module, six resistors with the same resistance value and two optical switching devices, wherein the operational amplifier module, the six resistors and the two optical switching devices are connected and matched in a specified mode. The addition and subtraction switching circuit can switch addition and subtraction operation only by adjusting one path of control signal.
Description
Technical Field
The application relates to the technical field of signal processing, in particular to an add-subtract switching circuit and electronic equipment.
Background
In signal processing, it is often necessary to add or subtract two voltage signals to obtain the desired resulting signal.
In the related art, the addition circuit and the subtraction circuit are relatively independent, and a large number of electronic devices are required to be used, so that the integration level is not high.
In addition, in practical applications, at least one of the two voltage signals to be added or subtracted is usually an unknown signal, and the voltage value of the unknown signal may be large or small, and is often a variable square wave signal, so if a general P-type or N-type field effect switching tube is used to build the addition circuit or the subtraction circuit, there is a possibility that the field effect switching tube cannot be normally turned on or turned off due to a higher or lower voltage value of the voltage signal to be operated, so that a result signal cannot be accurately obtained. In addition, the structure of the add-drop switching circuit proposed by the related art is relatively complex.
Disclosure of Invention
In view of this, the present application proposes an add-subtract switching circuit with a simple structure and an electronic apparatus having the same, which can obtain an ideal result signal even if the voltage values of two voltage signals to be added or subtracted are unknown values that vary within an unknown range.
In a first aspect, the present application proposes an add-subtract switching circuit for adding or subtracting a second voltage signal and a first voltage signal to or from a resultant voltage signal, the add-subtract switching circuit including:
the operational amplifier module is provided with an in-phase input pin, a reverse input pin and an output pin, wherein the output pin is used for outputting the result voltage signal;
a first resistor having opposite first and second ends, the first end for receiving the first voltage signal;
a second resistor having opposite third and fourth ends, the third end being connected to the inverting input pin and the fourth end being connected to the output pin;
a first optical switching device, the second terminal being connected to the third terminal via the first optical switching device;
a third resistor having opposite fifth and sixth ends, the fifth end being connected to the first optical switching device, the sixth end being grounded;
a fourth resistor having opposite seventh and eighth ends, the seventh end connected to the first end for receiving the first voltage signal;
a fifth resistor having opposite ninth and tenth ends, the ninth end for receiving the second voltage signal, the tenth end connected to the non-inverting input pin;
a second optical switching device, the eighth terminal being connected to the tenth terminal via the second optical switching device;
a sixth resistor having opposite tenth and twelfth ends, the eleventh end connected to the second optical switching device, the twelfth end grounded;
the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor have the same resistance value, and the first optical switching device and the second optical switching device are controlled by the same control signal;
the first optical switching device is configured to: in response to the control signal being high, the second end is conducted with the third end, and the third end is disconnected with the fifth end; in response to the control signal being low, disconnecting the second terminal from the third terminal and conducting the third terminal from the fifth terminal;
the second optical switching device is configured to: disconnecting the eighth terminal from the tenth terminal and conducting the tenth terminal from the eleventh terminal in response to the control signal being high; and in response to the control signal being at a low level, the eighth terminal is turned on with the tenth terminal, and the tenth terminal is turned off with the eleventh terminal.
In one possible embodiment, the first optical switching device includes:
the first housing is provided with a first opening,
a first light emitting diode, a second light emitting diode, a first photoelectric switch tube and a second photoelectric switch tube which are encapsulated in the first shell,
a first pin led out of the first shell from the anode of the first light emitting diode,
a second pin led out of the first shell from the cathode of the first light emitting diode,
a third pin led out of the first shell from the anode of the second light emitting diode,
a fourth pin led out of the first housing from the cathode of the second light emitting diode,
a fifth pin and a sixth pin led out of the first casing from the first photoelectric switch tube,
a seventh pin and an eighth pin led out of the first housing from the second photoelectric switch tube;
the first light-emitting diode corresponds to the first photoelectric switch tube, and the second light-emitting diode corresponds to the second photoelectric switch tube;
the first pin and the fourth pin are respectively used for receiving the control signal, the second pin is grounded, the fifth pin is connected with the second end, the sixth pin is respectively connected with the third end and the seventh pin, and the eighth pin is connected with the fifth end;
the third pin is used for being connected with a system voltage source to receive a level signal, and the level value of the level signal is higher than the level value of the low level and is not higher than the level value of the high level.
In one possible embodiment, the seventh pin is grounded via a first capacitor.
In one possible embodiment, the second optical switching device includes:
a second housing, which is provided with a second opening,
a third light emitting diode, a fourth light emitting diode, a third photoelectric switch tube and a fourth photoelectric switch tube which are encapsulated in the second shell,
a ninth pin led out of the second casing from the anode of the third light emitting diode,
a tenth pin led out of the second casing from the cathode of the third light emitting diode,
an eleventh pin led out of the second housing from the anode of the fourth light emitting diode,
a twelfth pin led out of the second casing from the cathode of the fourth light emitting diode,
a thirteenth pin and a fourteenth pin led out of the first housing from the third photoelectric switch tube,
fifteenth and sixteenth pins led out of the first housing from the fourth phototransistor;
the third light-emitting diode corresponds to the third photoelectric switch tube, and the fourth light-emitting diode corresponds to the fourth photoelectric switch tube;
the tenth pin and the eleventh pin are respectively used for receiving the control signal, the twelfth pin is grounded, the thirteenth pin is connected with the eighth end, the fourteenth pin is respectively connected with the tenth end and the fifteenth pin, and the sixteenth pin is connected with the tenth end.
Wherein the ninth pin is used for connecting the system voltage source to receive the level signal from the system voltage source.
In one possible embodiment, the fifteenth pin is grounded via a second capacitor.
In one possible implementation manner, the operational amplifier module, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the first optical switching device and the second optical switching device are disposed on the same PCB board.
In one possible implementation manner, the PCB board is provided with:
a first voltage signal access terminal connected to the first end,
a second voltage signal access terminal connected to the seventh end, and
and the voltage signal output terminal is connected with the output pin.
In one possible implementation manner, a system voltage source access terminal is arranged on the PCB board, and the system voltage source access terminal is respectively connected with the third pin and the ninth pin.
In a second aspect, the present application proposes an electronic device comprising an add-drop switching circuit as described in the first aspect.
In one possible embodiment, the electronic device includes a protective case in which the add-drop switching circuit is housed entirely.
According to the addition and subtraction switching circuit provided by the application, the structure is simple, and even if the voltage values of the two voltage signals to be added or subtracted are unknown values which change in an unknown range, an ideal result signal can be obtained. The addition and subtraction switching circuit can switch addition and subtraction operation only by adjusting one path of control signal.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following brief description of the drawings of the embodiments will make it apparent that the drawings in the following description relate only to some embodiments of the present application and are not limiting of the present application.
Fig. 1 is a schematic diagram of a configuration of an add-drop switching circuit according to an embodiment of the present application.
Fig. 2 is a simplified diagram of the addition-subtraction switching circuit shown in fig. 1 in a subtraction state.
Fig. 3 is a simplified diagram of the addition/subtraction switching circuit shown in fig. 1 in an addition state.
Fig. 4 is a schematic structural view of the first optical switching device in fig. 1.
Fig. 5 is a schematic structural view of the second optical switching device in fig. 1.
Reference numerals illustrate:
an OP-operational amplifier module;
u1-a first optical switching device, U2-a second optical switching device;
r1-a first resistor, R2-a second resistor, R3-a third resistor, R4-a fourth resistor, R5-a fifth resistor and R6-a sixth resistor;
m1-a first shell and M2-a second shell;
s1-a first pin, S2-a second pin, S3-a third pin, S4-a fourth pin, S5-a fifth pin, S6-a sixth pin, S7-a seventh pin, S8-an eighth pin, S9-a ninth pin, S10-a tenth pin, S11-an eleventh pin, S12-a twelfth pin, S13-a thirteenth pin, S14-a fourteenth pin, S15-a fifteenth pin, and S16-a sixteenth pin;
d1-a first light-emitting diode, D2-a second light-emitting diode, D3-a third light-emitting diode, D4-a fourth light-emitting diode;
the device comprises a K1-first photoelectric switch tube, a K2-second photoelectric switch tube, a K3-first photoelectric switch tube and a K4-second photoelectric switch tube;
c1-a first capacitor, C2-a second capacitor;
VREF-a first voltage signal, VIN-a second voltage signal, VOUT-a resulting voltage signal;
EN-control signal, VSYS-system voltage source.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without the benefit of the present disclosure, are intended to be within the scope of the present application based on the described embodiments. It is to be understood that some of the technical means of the various embodiments described herein may be interchanged or combined without conflict.
In the description of the present specification and claims, the terms "first," "second," and the like, if any, are used merely to distinguish between the described objects and do not have any sequential or technical meaning. Thus, an object defining "first," "second," etc. may explicitly or implicitly include one or more such objects. Also, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.
Fig. 1 shows a specific embodiment of the add-subtract switching circuit according to the present application, which is used for adding or subtracting the second voltage signal VIN and the first voltage signal VREF to obtain a resultant voltage signal, and in an application scenario, the voltage value (or the level value) of the second voltage signal VIN is a constant voltage value, and the voltage value of the first voltage signal VREF is an adjustable value.
The add-drop switching circuit comprises an operational amplifier module OP, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first optical switching device U1 and a second optical switching device U2.
The operational amplifier module OP has an in-phase input pin, an inverse input pin and an output pin, wherein the output pin is used for outputting the result voltage signal VOUT obtained after operation.
The first resistor R1 has a first end and a second end opposite to each other, wherein the first end is configured to receive the first voltage signal VREF. In fig. 1, the first end is the right end of the first resistor R1, and the second end is the left end of the first resistor R1.
The second resistor R2 has a third end and a fourth end opposite to each other, wherein the third end is connected to the inverting input pin of the OP-amp module OP, and the fourth end is connected to the output pin of the OP-amp module OP. In fig. 1, the third terminal is the left end of the second resistor R2, and the fourth terminal is the right end of the second resistor R2.
The third resistor R3 has a fifth end and a sixth end opposite to each other, wherein the fifth end is connected to the first optical switching device U1, and the sixth end is grounded. In fig. 1, the fifth end is the left end of the third resistor R3, and the sixth end is the right end of the third resistor R3.
The fourth resistor R4 has opposite seventh and eighth terminals, wherein the seventh terminal is connected to the first terminal of the first resistor R1 so as to be able to receive the first voltage signal VREF as well. In fig. 1, the seventh end is the right end of the fourth resistor R4, and the eighth end is the left end of the fourth resistor R4.
The fifth resistor R5 has a ninth end and a tenth end opposite to each other, wherein the ninth end is configured to receive the second voltage signal VIN, and the tenth end is connected to the non-inverting input pin of the OP-amp module OP. In fig. 1, the ninth end is the left end of the fifth resistor R5, and the tenth end is the right end of the fifth resistor R5.
The sixth resistor R6 has opposite tenth and twelfth ends, wherein the eleventh end is connected to the second optical switching device U2 and the twelfth end is grounded. In fig. 1, the tenth end is the left end of the sixth resistor R6, and the twelfth end is the right end of the sixth resistor R6.
The first optical switching device U1 disconnectably connects the second end of the first resistor R1 with the third end of the second resistor R2, in other words, the second end of the first resistor R1 is connected to the third end of the second resistor R2 via the first optical switching device U1.
The second optical switching device U2 disconnectably connects the eighth terminal of the fourth resistor R4 with the tenth terminal of the fifth resistor R5, in other words, the eighth terminal of the fourth resistor R4 is connected to the tenth terminal of the fifth resistor R5 via the second optical switching device U2.
The resistances of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are the same, that is, r1=r2=r3=r4=r5=r6 (in this equation, each algebraic number represents the resistance of the corresponding resistor).
The first optical switching device U1 and the second optical switching device U2 are controlled by the same control signal EN.
The first optical switching device U1 is configured to: in response to the control signal EN being at a high level, the second end of the first resistor R1 is turned on with the third end of the second resistor R2, and the third end of the second resistor R2 is disconnected with the fifth end of the third resistor R3; in response to the control signal EN being at a low level, the second terminal of the first resistor R1 is disconnected from the third terminal of the second resistor R2, and the third terminal of the second resistor R2 is turned on with the fifth terminal of the third resistor R3.
The second optical switching device U2 is configured to: in response to the control signal EN being at a high level, disconnecting the eighth terminal of the fourth resistor R4 from the tenth terminal of the fifth resistor R5, and turning on the tenth terminal of the fifth resistor R5 from the eleventh terminal of the sixth resistor R6; in response to the control signal EN being at a low level, the eighth terminal of the fourth resistor R4 is turned on with the tenth terminal of the fifth resistor R5, and the tenth terminal of the fifth resistor R5 is turned off with the eleventh terminal of the sixth resistor R6.
Referring to fig. 1 again and referring to fig. 2 and 3, the working principle of the add-drop switching circuit is described as follows:
when the control signal EN applied to the first and second optical switching devices U1 and U2 is at a high level, the first optical switching device U1 turns on the second terminal of the first resistor R1 and the third terminal of the second resistor R2 and turns off the third terminal of the second resistor R2 and the fifth terminal of the third resistor R3, and the second optical switching device U2 turns off the eighth terminal of the fourth resistor R4 and the tenth terminal of the fifth resistor R5 and turns on the tenth terminal of the fifth resistor R5 and the eleventh terminal of the sixth resistor R6. At this time, the addition-subtraction switching circuit in fig. 1 can be simplified to the state shown in fig. 2.
In fig. 2, r1=r2=r5=r6, the voltage at the non-inverting input terminal of the OP is VIN/2, and according to the electrical characteristics of the OP itself, the voltage at the inverting input terminal is also VIN/2, so as to enable the voltage at the inverting input terminal to reach VIN/2, an equation is obtained: (VIN/2-VREF)/r1= (VOUT-VIN/2)/R2, and because r1=r2, vout=vin-VREF can be obtained. It can be seen that the add-subtract switching circuit operates in a subtraction state at this time.
When the control signal EN applied to the first and second optical switching devices U1 and U2 is at a low level, the first optical switching device U1 disconnects the second terminal of the first resistor R1 from the third terminal of the second resistor R2 and turns on the third terminal of the second resistor R2 from the fifth terminal of the third resistor R3, and the second optical switching device U2 turns on the eighth terminal of the fourth resistor R4 from the tenth terminal of the fifth resistor R5 and disconnects the tenth terminal of the fifth resistor R5 from the eleventh terminal of the sixth resistor R6. At this time, the addition-subtraction switching circuit in fig. 1 can be simplified to the state shown in fig. 3.
In fig. 3, r2=r3=r4=r5, the in-phase terminal voltage of the OP is (vin+vref)/2, and according to the electrical characteristics of the OP itself, the terminal voltage of the inverting input is also (vin+vref)/2, and based on the voltage of the inverting input is (vin+vref)/2, the equation is obtained: (vin+vref)/(2×r3) = (VOUT- (vin+vref)/2)/R2, and because r2=r3, vout=vin+vref can be obtained. It can be seen that the add-subtract switching circuit operates in the addition state at this time.
Referring to fig. 4 in combination with fig. 1, the first optical switching device U1 includes a first housing M1, a first light emitting diode D1, a second light emitting diode D2, a first photoelectric switch K1 and a second photoelectric switch K2, a first pin S1, a second pin S2, a third pin S3, a fourth pin S4, a fifth pin S5, a sixth pin S6, a seventh pin S7, and an eighth pin S8.
The first light emitting diode D1, the second light emitting diode D2, the first photoelectric switch tube K1 and the second photoelectric switch tube K2 are completely encapsulated in the first housing M1. The first pin S1 is led out of the first casing M1 from the anode of the first light emitting diode D1. The second pin S2 is led out of the first casing M1 from the cathode of the first light emitting diode D1. The third pin S3 is led out of the first casing M1 from the anode of the second light emitting diode D2. The fourth pin S4 is led out of the first casing M1 from the cathode of the second light emitting diode D2. The fifth pin S5 and the sixth pin S6 are led out of the first casing M1 from two poles of the first photoelectric switch tube K1, respectively. The seventh pin S7 and the eighth pin S8 are respectively led out of the first casing M1 from two poles of the second photoelectric switch tube K2.
The first light emitting diode D1 corresponds to the first photoelectric switch tube K1, and the second light emitting diode D2 corresponds to the second photoelectric switch tube K2. That is, when the first light emitting diode D1 does not emit light, the first photoelectric switch tube K1 is in an off state; when the first light emitting diode D1 is powered on to emit light, the first photoelectric switch tube K1 receives the light signal and is turned on. When the second light emitting diode D2 does not emit light, the second photoelectric switch tube K2 is in an off state; when the second light emitting diode D2 is powered on to emit light, the second photoelectric switch tube K2 receives the light signal and is turned on.
The first pin S1 and the fourth pin S4 are respectively configured to receive the aforementioned control signal EN, the second pin S2 is grounded, the fifth pin S5 is connected to the second end of the first resistor R1, the sixth pin S6 is connected to the third end of the second resistor R2, the sixth pin S6 and the seventh pin S7 are connected through a vertical stub at the upper part in fig. 1 (such that the sixth pin S6 and the seventh pin S7 are always electrically connected), and the eighth pin S8 is connected to the fifth end of the third resistor R3. The third pin S3 is for connecting the system voltage source VSYS to receive a stable level signal from the system voltage source VSYS, the level value of which is higher than the level value of the low level control signal EN, and the level value of which is not higher than the level value of the high level control signal EN. For example, the level value supplied from the system voltage source VSYS may be constant 3.3V, and the level value of the control signal EN in the high level state may be 3.3V or less.
When the control signal EN is at a high level, the first light emitting diode D1 is powered on to emit light, and the corresponding first photoelectric switch tube K1 is turned on after receiving the light, so that the fifth pin S5 and the sixth pin S6 are turned on, and the first resistor R1 and the second resistor R2 are turned on. Meanwhile, since the level value of the high-level control signal EN is not lower than the level value of the level signal provided by the system voltage source VSYS, the anode potential of the second light emitting diode D2 is not higher than the cathode potential, the second light emitting diode D2 does not emit light, and therefore the second photoelectric switch tube K2 is in an off state, the seventh pin S7 and the eighth pin S8 are disconnected, and the second resistor R2 and the third resistor R3 are disconnected
When the control signal EN is at a low level (e.g., zero), the electric potential at both ends of the first light emitting diode D1 is equivalent and does not emit light, and the corresponding first photoelectric switch tube K1 is in an off state, and the first resistor R1 and the second resistor R2 are disconnected. Meanwhile, at two ends of the second light emitting diode D2, the level value of the low level control signal EN is lower than the level signal provided by the system voltage source VSYS, and the anode potential is higher than the cathode potential, so that the second light emitting diode D2 is electrified to emit light, the second photoelectric switch tube K2 receives illumination to be turned on, so that the seventh pin S7 and the eighth pin S8 are turned on, and the second resistor R2 and the third resistor R3 are turned on.
In order to obtain the filtering effect, the present embodiment connects the seventh pin S7 to the ground via the first capacitor C1.
Referring to fig. 5 in combination with fig. 1, the second optical switching device U2 has substantially the same structure as the first optical switching device U1, and includes a second housing M2, a third light emitting diode D3, a fourth light emitting diode D4, a third photoelectric switching tube K3, a fourth photoelectric switching tube K4, a ninth pin S9, a tenth pin S10, an eleventh pin S11, a twelfth pin S12, a thirteenth pin S13, a fourteenth pin S14, a fifteenth pin S15, and a sixteenth pin S16.
The third light emitting diode D3, the fourth light emitting diode D4, the third phototransistor K3, and the fourth phototransistor K4 are completely encapsulated within the second housing M2. The ninth pin S9 is led out of the second housing M2 from the anode of the third light emitting diode D3. The tenth pin S10 is led out of the second housing M2 from the cathode of the third light emitting diode D3. The eleventh pin S11 is led out of the second housing M2 from the anode of the fourth light emitting diode D4. The twelfth pin S12 is led out of the second housing M2 from the cathode of the fourth light emitting diode D4. The thirteenth pin S13 and the fourteenth pin S14 are respectively led out of the second casing M2 from two poles of the third photoelectric switch tube K3. The fifteenth pin S15 and the sixteenth pin S16 are led out of the second housing M2 from both poles of the fourth photoelectric switch tube K4, respectively.
The tenth pin S10 and the eleventh pin S11 are each configured to receive the aforementioned control signal EN, the twelfth pin S12 is grounded, the thirteenth pin S13 is connected to the eighth end of the fourth resistor R4, the fourteenth pin S14 is connected to the tenth end of the fifth resistor R5, and the fourteenth pin S14 and the fifteenth pin S15 are connected through a vertical stub at the lower side in fig. 1, and the sixteenth pin S16 is connected to the tenth end. The ninth pin S9 is also used to connect the aforementioned system voltage source VSYS to receive the aforementioned level signal from the system voltage source VSYS.
When the control signal EN is at a high level, the level values provided by the control signal EN and the system voltage source VSYS, which are at high levels, are not higher than the level signal of the control signal at the cathode terminal and the anode terminal of the third light emitting diode, so that the third light emitting diode does not emit light, and therefore the third photoelectric switch tube is in an off state, the thirteenth pin S13 and the fourteenth pin S14 are disconnected, and the fourth resistor R4 is disconnected from the fifth resistor R5. Meanwhile, the potential difference exists at two ends of the fourth light diode to enable the fourth light diode to be electrified and emit light, and the fourth photoelectric switch tube corresponding to the fourth light diode is connected with illumination to conduct, so that the fifteenth pin S15 and the sixteenth pin S16 are conducted, and further the fifth resistor R5 and the sixth resistor R6 are conducted.
When the control signal EN is at a low level (e.g., zero), there is a potential difference between the control signal EN at the low level and the level signal provided by the system voltage source VSYS at both ends of the third light emitting diode, and the anode potential is higher than the cathode potential, so that the third light emitting diode is powered on and emits light, and the third photoelectric switch tube is connected to be turned on by illumination, so that the thirteenth pin S13 and the fourteenth pin S14 are turned on, and the fourth resistor R4 and the fifth resistor R5 are turned on. In this case, the potential across the fourth light emitting diode is equivalent and does not emit light, and the fourth photoelectric switching tube corresponding thereto is in an off state, and the fifth resistor R5 and the sixth resistor R6 are turned off.
In order to obtain the filtering effect, the fifteenth pin S15 is grounded via the second capacitor C2.
The operational amplifier module OP, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first optical switching device U1 and the second optical switching device U2 may be disposed on a PCB board with the same small area, and a first voltage signal VREF access terminal, a voltage signal output terminal and a system voltage source VSYS access terminal are disposed on the PCB board. The first voltage signal VREF access terminal, which is the access terminal of the first voltage signal VREF, is connected to the first end of the first resistor R1, and thus is also connected to the seventh end of the fourth resistor R4. The second voltage signal VIN access terminal, which is the access terminal of the second voltage signal VIN, is connected to the ninth end of the fifth resistor R5. The voltage signal output terminal as the output terminal of the result voltage signal VOUT is connected to the output pin of the OP. The system voltage source VSYS is connected to the third pin S3 and the ninth pin S9 as an access terminal for the level signal provided by the system voltage source VSYS. In this way, the add-drop switching circuit is enabled as a single electrical component, enabling flexible attachment in various circuitry.
In addition, the embodiment of the application also provides electronic equipment, which comprises the addition and subtraction switching circuit. The electronic device may include a protective case that houses all of the add-drop switching circuits therein.
Claims (8)
1. An add-subtract switching circuit for performing addition or subtraction on a second voltage signal and a first voltage signal to obtain a resultant voltage signal, the add-subtract switching circuit comprising:
the operational amplifier module is provided with an in-phase input pin, a reverse input pin and an output pin, wherein the output pin is used for outputting the result voltage signal;
a first resistor having opposite first and second ends, the first end for receiving the first voltage signal;
a second resistor having opposite third and fourth ends, the third end being connected to the inverting input pin and the fourth end being connected to the output pin;
a first optical switching device, the second terminal being connected to the third terminal via the first optical switching device;
a third resistor having opposite fifth and sixth ends, the fifth end being connected to the first optical switching device, the sixth end being grounded;
a fourth resistor having opposite seventh and eighth ends, the seventh end connected to the first end for receiving the first voltage signal;
a fifth resistor having opposite ninth and tenth ends, the ninth end for receiving the second voltage signal, the tenth end connected to the non-inverting input pin;
a second optical switching device, the eighth terminal being connected to the tenth terminal via the second optical switching device;
a sixth resistor having opposite tenth and twelfth ends, the eleventh end connected to the second optical switching device, the twelfth end grounded;
the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor have the same resistance value, and the first optical switching device and the second optical switching device are controlled by the same control signal;
the first optical switching device is configured to: in response to the control signal being high, the second end is conducted with the third end, and the third end is disconnected with the fifth end; in response to the control signal being low, disconnecting the second terminal from the third terminal and conducting the third terminal from the fifth terminal;
the second optical switching device is configured to: disconnecting the eighth terminal from the tenth terminal and conducting the tenth terminal from the eleventh terminal in response to the control signal being high; in response to the control signal being low, turning on the eighth terminal and the tenth terminal, and turning off the tenth terminal and the eleventh terminal;
the first optical switching device includes:
the first housing is provided with a first opening,
a first light emitting diode, a second light emitting diode, a first photoelectric switch tube and a second photoelectric switch tube which are encapsulated in the first shell,
a first pin led out of the first shell from the anode of the first light emitting diode,
a second pin led out of the first shell from the cathode of the first light emitting diode,
a third pin led out of the first shell from the anode of the second light emitting diode,
a fourth pin led out of the first housing from the cathode of the second light emitting diode,
a fifth pin and a sixth pin led out of the first casing from the first photoelectric switch tube,
a seventh pin and an eighth pin led out of the first housing from the second photoelectric switch tube;
the first light-emitting diode corresponds to the first photoelectric switch tube, and the second light-emitting diode corresponds to the second photoelectric switch tube;
the first pin and the fourth pin are respectively used for receiving the control signal, the second pin is grounded, the fifth pin is connected with the second end, the sixth pin is respectively connected with the third end and the seventh pin, and the eighth pin is connected with the fifth end;
wherein the third pin is used for connecting a system voltage source to receive a level signal from the system voltage source, the level value of the level signal is higher than the level value of the low level and is not higher than the level value of the high level;
the second optical switching device includes:
a second housing, which is provided with a second opening,
a third light emitting diode, a fourth light emitting diode, a third photoelectric switch tube and a fourth photoelectric switch tube which are encapsulated in the second shell,
a ninth pin led out of the second casing from the anode of the third light emitting diode,
a tenth pin led out of the second casing from the cathode of the third light emitting diode,
an eleventh pin led out of the second housing from the anode of the fourth light emitting diode,
a twelfth pin led out of the second casing from the cathode of the fourth light emitting diode,
a thirteenth pin and a fourteenth pin led out of the first housing from the third photoelectric switch tube,
fifteenth and sixteenth pins led out of the first housing from the fourth phototransistor;
the third light-emitting diode corresponds to the third photoelectric switch tube, and the fourth light-emitting diode corresponds to the fourth photoelectric switch tube;
the tenth pin and the eleventh pin are respectively used for receiving the control signal, the twelfth pin is grounded, the thirteenth pin is connected with the eighth end, the fourteenth pin is respectively connected with the tenth end and the fifteenth pin, and the sixteenth pin is connected with the tenth end;
wherein the ninth pin is used for connecting the system voltage source to receive the level signal from the system voltage source.
2. The add-drop switching circuit of claim 1, wherein the seventh pin is grounded via a first capacitor.
3. The add-drop switching circuit of claim 1, wherein the fifteenth pin is grounded via a second capacitor.
4. The add-drop switching circuit of claim 1, wherein the op-amp module, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the first optical switching device, and the second optical switching device are disposed on a same PCB board.
5. The add-drop switching circuit according to claim 4, wherein the PCB board is provided with:
a first voltage signal access terminal connected to the first end,
a second voltage signal access terminal connected to the seventh end, and
and the voltage signal output terminal is connected with the output pin.
6. The add-drop switching circuit of claim 5, wherein a system voltage source access terminal is provided on the PCB, and the system voltage source access terminal is connected to the third pin and the ninth pin, respectively.
7. An electronic device comprising the add-drop switching circuit according to any one of claims 1 to 6.
8. The electronic device of claim 7, wherein the electronic device comprises a protective housing in which the add-drop switching circuit is housed entirely.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310063065.XA CN115934027B (en) | 2023-01-16 | 2023-01-16 | Addition and subtraction switching circuit and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310063065.XA CN115934027B (en) | 2023-01-16 | 2023-01-16 | Addition and subtraction switching circuit and electronic equipment |
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| Publication Number | Publication Date |
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| CN115934027A CN115934027A (en) | 2023-04-07 |
| CN115934027B true CN115934027B (en) | 2023-05-23 |
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| CN202310063065.XA Active CN115934027B (en) | 2023-01-16 | 2023-01-16 | Addition and subtraction switching circuit and electronic equipment |
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Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9245649B2 (en) * | 2013-12-17 | 2016-01-26 | Intermolecular, Inc. | Resistive switching sample and hold |
| CN213068994U (en) * | 2020-08-07 | 2021-04-27 | 河南翔宇医疗设备股份有限公司 | Acquisition circuit and detection device of two-way symmetrical analog voltage signal |
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