CN115931423A - Slicing method and slicing device for failure point position of semiconductor chip - Google Patents
Slicing method and slicing device for failure point position of semiconductor chip Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000002093 peripheral effect Effects 0.000 claims abstract description 125
- 238000012545 processing Methods 0.000 claims abstract description 31
- 238000012986 modification Methods 0.000 claims abstract description 18
- 230000004048 modification Effects 0.000 claims abstract description 18
- 239000011241 protective layer Substances 0.000 claims description 26
- 238000005520 cutting process Methods 0.000 claims description 25
- 238000010884 ion-beam technique Methods 0.000 description 22
- 238000010894 electron beam technology Methods 0.000 description 18
- 239000003550 marker Substances 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
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Abstract
The invention provides a slicing method and a slicing device for a failure point position of a semiconductor chip, wherein the slicing method comprises the following steps: acquiring a failure point position; performing combined marking processing on the periphery of the failure point position to obtain a combined marking position, wherein the combined marking position comprises a peripheral marking group, a warning marking group and a target marking group; slicing the position of the failure point according to the peripheral mark group to obtain an initial slice; performing fine modification processing on the initial slice according to the warning mark group and the target mark group to generate a target slice; and slicing the target slice to obtain a failure point sample. By the slicing method and the slicing device for the failure point position of the semiconductor chip, the slicing accuracy of the failure point position of the semiconductor chip can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a slicing method and a slicing device for failure point positions of a semiconductor chip.
Background
In the process of slicing the position of the failure point of the semiconductor chip, observation by means of a transmission electron microscope is often required. Before observation, the electrical failure point of the semiconductor chip needs to be sliced so that the transmission electron microscope can observe the sliced sample. The slice sample preparation mainly depends on a focused ion beam cutting instrument to slice the semiconductor chip, and because the magnification of the focused ion beam cutting instrument is limited, the electrical failure point of the semiconductor chip cannot be accurately sliced.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for dicing the failure point position of a semiconductor chip, which can improve the accuracy of dicing the failure point position of the semiconductor chip.
To achieve the above and other related objects, the present invention provides a method for dicing a location of a failure point of a semiconductor chip, comprising:
acquiring a failure point position;
performing combined marking processing on the periphery of the failure point position to obtain a combined marking position, wherein the combined marking position comprises a peripheral marking group, a warning marking group and a target marking group;
slicing the position of the failure point according to the peripheral mark group to obtain an initial slice;
performing fine modification processing on the initial slice according to the warning mark group and the target mark group to generate a target slice;
and slicing the target slice to obtain a failure point sample.
In an embodiment of the present invention, the step of performing combined marking processing on the periphery of the failure point position to obtain a combined marking position includes:
and marking in the horizontal direction and the vertical direction of the position of the failure point to obtain a peripheral mark group, wherein the peripheral mark group comprises a first peripheral mark and a second peripheral mark.
In an embodiment of the present invention, after the step of performing the marking processing in the horizontal direction and the vertical direction of the failure point position to obtain the peripheral mark group, the method further includes: and marking two sides of the straight line of the first peripheral mark to obtain an alarm mark group, wherein the alarm mark group comprises a first alarm mark and a second alarm mark.
In an embodiment of the present invention, after the steps of performing marking processing on two sides of the straight line where the first peripheral mark is located and obtaining the warning mark group, the method further includes: and marking between the straight line of the first warning mark and the straight line of the second warning mark to obtain a target mark group.
In an embodiment of the present invention, the first peripheral mark is located in a vertical direction of the failure point position, the second peripheral mark is located in a horizontal direction of the failure point position, and a straight line where the first peripheral mark is located intersects a straight line where the second peripheral mark is located at the failure point position.
In an embodiment of the present invention, the straight line of the first warning mark and the straight line of the second warning mark are parallel to each other.
In an embodiment of the present invention, before the step of slicing the failure point position according to the peripheral mark group to obtain an initial slice, the method further includes:
and attaching a protective layer on the position of the failure point, wherein the peripheral mark group is positioned outside the protective layer, and the warning mark group and the target mark group are positioned inside the protective layer.
In an embodiment of the present invention, the step of slicing the failure point position according to the peripheral mark group to obtain an initial slice includes:
slicing the position of the first peripheral mark along the horizontal direction at one side of the failure point position until the edge of the slice is positioned at one side of the second peripheral mark;
and slicing the other side of the position of the failure point along the horizontal direction, and stopping until the edge of the slice is positioned on one side of the second peripheral mark to obtain an initial slice.
In an embodiment of the present invention, the step of performing a refinement process on the initial slice according to the warning marker group and the target marker group to generate a target slice includes:
performing fine modification treatment on one side of the initial slice, and cutting off the first warning mark until the edge of the slice contacts with the target mark group;
and performing fine modification on the other side of the initial slice, and cutting off the second warning mark until the edge of the slice contacts with the target mark group to generate a target slice.
The present invention also provides a slicing apparatus for a failure point position of a semiconductor chip, comprising:
the position acquisition module is used for acquiring the position of a failure point;
the mark processing module is used for carrying out combined mark processing on the periphery of the failure point position to obtain a combined mark position, wherein the combined mark position comprises a peripheral mark group, a warning mark group and a target mark group;
the first slicing module is used for slicing the position of the failure point according to the peripheral mark group to obtain an initial slice;
the second slicing module is used for performing fine modification processing on the initial slices according to the warning mark group and the target mark group to generate target slices; and
and the third slicing module is used for slicing the target slice to obtain a failure point sample.
As described above, the present invention provides a method for slicing a failure point position of a semiconductor chip, wherein when a plurality of repeating units are located near the failure point position, a warning mark group and a target mark group can remind a worker to slice to a target position, so that an electrical failure point of the semiconductor chip can be accurately sliced, and thus, an obtained failure sample application sheet has good quality, and the accuracy of slicing the failure point position of the semiconductor chip can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts based on these drawings:
FIG. 1 is a flow chart of a method for slicing the location of a failure point of a semiconductor chip according to the present invention;
FIG. 2 is a flowchart of step S20 in FIG. 1;
FIG. 3 is a flowchart of step S40 in FIG. 1;
FIG. 4 is a flowchart of step S50 in FIG. 1;
FIG. 5 is a schematic diagram showing the structure of the combined marker position during slicing at the failure point position according to the present invention;
FIG. 6 is a schematic view of the protective layer during slicing at the failure point location according to the present invention;
FIG. 7 is a schematic structural diagram of an initial slice during slicing at the location of a failure point according to the present invention;
FIG. 8 is a schematic view of a cut to a first warning flag location during slicing of the location of a failure point in accordance with the present invention;
FIG. 9 is a schematic diagram showing the position of a target marker set during slicing at the location of a failure point in accordance with the present invention;
FIG. 10 is a schematic illustration of a cut to a second warning flag location during slicing of the location of the failure point of the present invention;
FIG. 11 is a schematic view of a target slice during slicing at a failure point location according to the present invention;
fig. 12 is a schematic structural diagram of a dicing apparatus for a position of a failure point of a semiconductor chip according to the present invention.
Element number description:
110. a position of a failure point; 120. a first peripheral mark; 130. a second peripheral mark; 140. a first warning label; 150. a second warning label; 160. a target mark;
210. a position acquisition module; 220. a marking processing module; 230. a protection processing module; 240. a first slicing module; 250. a second slicing module; 260. and a third slicing module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a failure point inevitably occurs in the integrated circuit inside the semiconductor chip during the development, production and use processes, and after the failure point occurs, the semiconductor chip needs to be sliced at the failure point position so that the designer can find out the corresponding technical defect. The invention provides a slicing method for a failure point position of a semiconductor chip, which can be applied to the failure point analysis process of the semiconductor chip and comprises the following steps:
s10, acquiring a failure point position;
s20, performing combined marking processing on the periphery of the position of the failure point to obtain a combined marking position, wherein the combined marking position comprises a peripheral marking group, a warning marking group and a target marking group;
s30, attaching a protective layer at the position of a failure point;
s40, slicing the failure point position of the semiconductor chip according to the peripheral mark group to obtain an initial slice;
s50, performing fine modification treatment on the initial slice according to the warning mark group and the target mark group to generate a target slice;
and S60, slicing the target slice of the semiconductor chip to obtain a failure point sample.
In one embodiment of the present invention, when step S10 is performed, the location of the fail point is obtained. Specifically, since there may be a plurality of failure points on the semiconductor chip, a specific position of each failure point may be obtained, so as to perform a subsequent slicing process on the semiconductor chip, cut out the failure points, and slice the failure points at the failure point positions.
Referring to fig. 2, when step S20 is executed, that is, the combined mark processing is performed on the periphery of the position of the failure point, so as to obtain the combined mark position, where the combined mark position includes the peripheral mark group, the warning mark group, and the target mark group. Specifically, step S20 may include the following steps:
step S21, marking in the horizontal direction and the vertical direction of the position of the failure point to obtain a peripheral mark group, wherein the peripheral mark group comprises at least two peripheral marks which are divided into a first peripheral mark and a second peripheral mark, at least one first peripheral mark is arranged in the vertical direction of the position of the failure point, at least one second peripheral mark is arranged in the horizontal direction of the position of the failure point, and the straight line of the first peripheral mark intersects with the straight line of the second peripheral mark at the position of the failure point;
step S22, marking two sides of the straight line of the first peripheral mark to obtain a warning mark group, wherein the warning mark group comprises at least two warning marks which are divided into a first warning mark and a second warning mark;
and S23, marking between the straight line of the first warning mark and the straight line of the second warning mark to obtain a target mark group, wherein the target mark group comprises at least one target mark, and the straight line of the target mark intersects with the position of the failure point.
In one embodiment of the present invention, when step S21 is performed, i.e., the marking process is performed in the horizontal direction and the vertical direction of the fail point position, the peripheral mark group is acquired. Specifically, after a certain fail point position 110 is obtained, a marking process may be performed on the periphery of the fail point position 110 to obtain a peripheral mark group. For example, a first peripheral mark 120 may be disposed in a vertical direction of the fail point position 110, a second peripheral mark 130 may be disposed in a horizontal direction of the fail point position 110, and the first peripheral mark 120 and the second peripheral mark 130 may cooperate to form a peripheral mark group. The first peripheral mark 120 and the second peripheral mark 130 can be formed by focusing a gallium ion beam emitted from a focused ion beam cutting apparatus and then applying the gallium ion beam to the surface of the semiconductor chip. The first peripheral mark 120 may have a long shape, such as a rectangle or a oval, and the second peripheral mark 130 may also have a long shape, such as a rectangle or a oval. The line along which the first peripheral indicia 120 is located may be collinear with the failure point location 110, and the line along which the second peripheral indicia 130 is located may also be collinear with the failure point location 110, i.e., the line along which the first peripheral indicia 120 is located is perpendicular to the line along which the second peripheral indicia 130 is located, and intersects at the failure point location 110. The number of the first peripheral marks 120 may be one, two, multiple, etc. The number of the second peripheral marks 130 may be one, two, multiple, etc. When the number of the first peripheral marks 120 is two, two first peripheral marks 120 may be located on two sides of the failure point location 110, and the two first peripheral marks 120 and the failure point location 110 may be located on the same straight line. When the number of the second peripheral marks 130 is two, two second peripheral marks 130 may be located on both sides of the fail point position 110, and the two second peripheral marks 130 and the fail point position 110 may be located on the same straight line.
In one embodiment of the present invention, when step S22 is executed, that is, the marking process is performed on two sides of the straight line of the first peripheral mark, to obtain the warning mark group, where the warning mark group includes at least two warning marks, and the warning marks are divided into a first warning mark and a second warning mark. Specifically, after the first peripheral mark 120 is obtained, a first warning mark 140 and a second warning mark 150 may be respectively disposed on two sides of a straight line where the first peripheral mark 120 and the failure point position 110 are located, and the first warning mark 140 and the second warning mark 150 cooperate with each other to form a warning mark group. The gallium ion beam emitted from the focused ion beam cutting instrument is focused and acts on the surface of the semiconductor chip to form the first warning mark 140 and the second warning mark 150. The first warning mark 140 may have a shape of a long bar, for example, a rectangle or a oval, and the second warning mark 150 may have a shape of a long bar, for example, a rectangle or a oval. The number of the first warning marks 140 may be one, two, multiple, etc. The number of the second warning marks 150 may be one, two, more, etc. Taking the number of the first warning marks 140 as one, and the number of the second warning marks 150 as one for illustration, the first warning marks 140 may be located at one side between the fail point position 110 and the first peripheral mark 120, the first warning marks 140 may be located at the other side of the fail point position 110, the second warning marks 150 may be located at one side between the fail point position 110 and the first peripheral mark 120, and the second warning marks 150 may be located at the other side of the fail point position 110. That is, the first warning mark 140 and the second warning mark 150 may be located on one side of the fail point location 110, and the first warning mark 140 and the second warning mark 150 may also be located on two sides of the fail point location 110. When the number of the first warning marks 140 is plural, the number of the plural first warning marks 140 may be located on the same straight line. When the number of the second warning marks 150 is plural, the number of the plural second warning marks 150 may be located on the same straight line. The straight line of the first warning mark 140 and the straight line of the second warning mark 150 are parallel to each other, and the fail point position 110 is located between the two parallel lines. In the horizontal direction, the distance between the first warning mark 140 and the failure point location 110 may be represented as a first distance, and the first distance may be between 2 to 3um, for example, the first distance may be 2um, the first distance may also be 2.5um, and the first distance may also be 3um. In the horizontal direction, the distance between the second warning mark 150 and the failure point 110 may be represented as a second distance, and the second distance may be between 2um and 3um, for example, the second distance may be 2um, the second distance may also be 2.5um, and the second distance may also be 3um.
In one embodiment of the present invention, when step S23 is executed, that is, a marking process is performed between a straight line of the first warning mark and a straight line of the second warning mark, a target mark group is obtained, where the target mark group includes at least one target mark, and the straight line of the target mark intersects with the position of the failure point. Specifically, after the first warning mark 140 and the second warning mark 150 are obtained, a target mark group may be set between the straight line of the first warning mark 140 and the straight line of the second warning mark 150, and the target mark group may include at least one target mark 160. The target mark 160 can be formed by focusing a gallium ion beam emitted from a focused ion beam cutting apparatus and then applying the focused gallium ion beam to the surface of the semiconductor chip. The target mark 160 may be in the shape of a long bar, for example, a rectangle, or a waist circle. The number of the target mark 160 may be one, two, or more. Taking the number of target marks 160 as an example, the target mark 160 may be located on one side between the fail point position 110 and the first peripheral mark 120, and the target mark 160 may also be located on the other side of the fail point position 110. Taking the number of the target marks 160 as two for example, two target marks 160 may be located on one side between the fail point location 110 and the first peripheral mark 120, two target marks 160 may also be located on the other side of the fail point location 110, and two target marks 160 may also be located on two sides of the fail point location 110, respectively. The line of the target mark 160 may intersect the failure point location 110. In the horizontal direction, the distance between the target marker 160 and the failure point position 110 may be represented as a third distance, and the third distance may be between 3um and 4um, for example, the third distance may be 3um, the third distance may also be 3.5um, and the third distance may also be 4um.
In one embodiment of the present invention, when step S30 is performed, a protective layer is attached at the position of the failure point. Specifically, after the failure point position, the peripheral mark group, the warning mark group and the target mark group are obtained, a protective layer may be plated near the failure point position of the semiconductor chip, and the protective layer may be made of platinum Pt, tungsten W, carbon C, or the like. The protective layer can protect the failure point and prevent the focused ion beam cutting instrument from damaging the failure point when the focused ion beam cutting instrument slices a semiconductor chip. After the protective layer is coated, the failure point location 110, the warning mark group and the target mark group may be located in the protective layer, and the peripheral mark group may be located outside the protective layer.
Referring to fig. 3, in an embodiment of the invention, when step S40 is executed, the semiconductor chip is sliced at the failure point position according to the peripheral mark group, so as to obtain an initial slice. Specifically, the step S40 may include the following steps:
s41, slicing the position of the first peripheral mark along the horizontal direction at one side of the position of the failure point until the edge of the slice is positioned at one side of the second peripheral mark;
and S42, slicing the other side of the position of the failure point along the horizontal direction until the edge of the slice is positioned on one side of the second peripheral mark, and obtaining an initial slice, wherein the initial slice is of a plate-shaped structure.
In one embodiment of the present invention, when step S41 is performed, that is, on the side of the position of the fail point, the slicing process is performed on the position where the first peripheral mark is located in the horizontal direction until the edge of the slice is located on the side of the second peripheral mark. Specifically, when the slicing process is required for the fail point position 110, the slicing process may be performed on the position of the first peripheral mark 120 in the horizontal direction on the side of the fail point position 110 until the edge of the slice is located on the side of the second peripheral mark 130. The surface of the semiconductor chip can be sliced by an electron beam current emitted by a focused ion beam cutting instrument, and the intensity of the electron beam current can be in a range of 18 to 24nA, for example, 18nA, 21nA or 24nA.
In one embodiment of the present invention, when step S42 is performed, that is, the slicing process is performed on the other side of the position of the fail point in the horizontal direction until the edge of the slice is located on one side of the second peripheral mark, an initial slice is obtained, wherein the initial slice has a plate-like structure. Specifically, after slicing one side of the fail point position 110, the other side of the fail point position 110 may be sliced until the edge of the slice is positioned at one side of the second peripheral mark 130. The surface of the semiconductor chip can be sliced by an electron beam current emitted by a focused ion beam cutting instrument, and the intensity of the electron beam current can be in the range of 18 to 24nA, for example, 18nA, 21nA or 24nA. After the slicing treatment is finished, an initial slice can be obtained, the shape of the initial slice can be a plate-shaped structure, the length of the initial slice can be in the range of 10-14um, the width of the initial slice can be in the range of 1.2-1.4um, and the depth of the initial slice can be in the range of 3-5um. For example, the length of the initial slice may be 10um, the length of the initial slice may be 12um, and the length of the initial slice may be 14um. The width of the initial slice can be 1.2um, the width of the initial slice can also be 1.3um, and the width of the initial slice can also be 1.4um. The depth of the initial slice may be 3um, the depth of the initial slice may also be 4um, and the depth of the initial slice may also be 5um.
Referring to fig. 4, when step S50 is executed, the initial slice is sliced according to the warning mark group and the target mark group, and a target slice is generated. Specifically, step S50 may include the following steps:
s51, performing fine modification treatment on one side of the initial slice, and cutting off the first warning mark until the edge of the slice contacts with the target mark group;
and S52, performing fine modification on the other side of the initial slice, and cutting off the second warning mark until the edge of the slice contacts with the target mark group to generate a target slice.
In one embodiment of the present invention, when step S51 is performed, i.e., one side of the initial slice is subjected to a fine modification process, the first warning mark is cut off until the edge of the slice contacts the target mark group. Specifically, after the initial slice is obtained, since the initial slice has a relatively thick thickness, it needs to be further sliced, and the thickness of the initial slice is adjusted to be within a suitable range. The side face of the initial slice can be sliced by an electron beam emitted by a focused ion beam cutting instrument, and the intensity of the electron beam can be in the range of 70 to 90pa, for example, 70pA, 80pA or 90pA. When one side of the initial slice is sliced, the position of the initial slice can be adjusted, so that the initial slice gradually approaches to the electron beam. When the initial slice is sliced by the electron beam, the first warning mark 140 is cut first, at this time, the staff can be reminded to pay attention to the slicing range until the edge of the slice contacts with the target mark group, at this time, the focused ion beam cutting instrument stops emitting the electron beam, and the slicing of one side of the initial slice is completed.
In one embodiment of the present invention, when step S52 is executed, i.e., the other side of the initial slice is subjected to the fine modification processing, the second warning mark is cut off until the edge of the slice contacts with the target mark set, and a target slice is generated. Specifically, after performing the fine modification process on one side of the initial slice, the initial slice may be turned over to perform the fine modification process on the other side of the initial slice. The side face of the initial slice can be sliced by an electron beam emitted by a focused ion beam cutting instrument, and the intensity of the electron beam can be in the range of 70 to 90pa, for example, 70pA, 80pA or 90pA. When one side of the initial slice is sliced, the position of the initial slice can be adjusted, so that the initial slice gradually approaches to the electron beam. When the initial slice is sliced by the electron beam, the first warning mark 140 is cut first, at this time, the staff can be reminded to pay attention to the slicing range until the edge of the slice contacts with the target mark group, at this time, the focused ion beam cutting instrument stops emitting the electron beam, the slicing of the other side of the initial slice is completed, and the target slice is generated. The shape of the target slice can be a plate-shaped structure, the length of the target slice can be within the range of 10-14um, the width of the target slice can be within the range of 80-120nm, and the depth of the target slice can be within the range of 3-5um. For example, the length of the target slice may be 10um, the length of the target slice may be 12um, and the length of the target slice may be 14um. The width of the target slice can be 80nm, the width of the target slice can also be 100nm, and the width of the target slice can also be 120nm. The depth of the target slice can be 3um, the depth of the target slice can also be 4um, and the depth of the target slice can also be 5um.
In one embodiment of the present invention, when step S60 is executed, the target slice of the semiconductor chip is subjected to a slicing process to obtain a fail point sample. Specifically, after the target slice is obtained, since both sides of the target slice are connected to the semiconductor chip, both sides of the target slice need to be cut off to separate the target slice from the semiconductor chip. During the cutting process, the side face of the initial slice can be sliced by an electron beam emitted by a focused ion beam cutting instrument, and the intensity of the electron beam can be in the range of 70 to 90pa, for example, 70pA, 80pA or 90pA.
Referring to fig. 5, 6, 7, 8, 9, 10 and 11, in an embodiment of the present invention, for a dicing process of a failure point of a semiconductor chip, the failure point position 110 may be obtained first, and then the marking is performed on the periphery of the failure point position 110, and the first peripheral mark 120, the second peripheral mark 130, the first warning mark 140, the second warning mark 150 and the target mark 160 are obtained. The failure point location 110 may then be protected by spraying a protective layer in the vicinity of the failure point location 110, the first peripheral marker 120 and the second peripheral marker 130 may be located on the outside of the protective layer, and the first warning marker 140, the second warning marker 150, and the target marker 160 may be located on the inside of the protective layer. After the protective layer is generated, the fail point position 110 may be sliced according to the first peripheral mark 120 and the second peripheral mark 130, and an initial slice is obtained. The fine trimming process can be performed on one side of the initial slice, when the first warning mark 140 is cut, the staff can be reminded that the slicing of the one side of the initial slice is about to be completed, and when the target mark 160 is cut, the staff can be reminded that the slicing of the one side of the initial slice is completed. The semiconductor slice can be rotated to perform fine trimming on the other side of the initial slice, when the second warning mark 150 is cut, the worker can be reminded that the other side of the initial slice is ready to be sliced, and when the target mark 160 is cut, the worker can be reminded that the slicing on the other side of the initial slice is ready to be sliced, and then the target slice can be obtained. And finally, taking out the target slice from the semiconductor chip to obtain a failure point sample wafer, and slicing the failure point position of the failure point sample wafer through a transmission electron microscope.
Therefore, in the scheme, when a plurality of repeating units are arranged near the failure point position, the warning mark group and the target mark group can remind a worker to cut the target position, the electrical failure point of the semiconductor chip can be accurately sliced, the quality of the obtained failure sample application sheet is good, and the accuracy of slicing the failure point position of the semiconductor chip can be effectively improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Referring to fig. 12, the present invention further provides a device for slicing the fail point position of the semiconductor chip, wherein the device for slicing the fail point position of the semiconductor chip corresponds to the method for slicing the fail point position of the semiconductor chip one to one. The slicing apparatus for the location of the fail point of the semiconductor chip may include a position acquisition module 210, a marking processing module 220, a protection processing module 230, a first slicing module 240, a second slicing module 250, and a third slicing module 260.
In one embodiment of the invention, the location acquisition module 210 may be used to acquire the location of the failed point. Specifically, since there may be a plurality of failure points on the semiconductor chip, a specific position of each failure point may be obtained, so that the semiconductor chip may be sliced subsequently, the failure points may be cut out, and the failure points may be sliced at the failure point positions.
In one embodiment of the present invention, the mark processing module 220 may be configured to perform a combined mark process on the periphery of the position of the failure point, and obtain a combined mark position, where the combined mark position includes a peripheral mark group, a warning mark group, and a target mark group. The marking processing module 220 may be specifically configured to perform marking processing in a horizontal direction and a vertical direction of a failure point position to obtain a peripheral marking group, where the peripheral marking group includes at least two peripheral markings, the peripheral markings are divided into a first peripheral marking and a second peripheral marking, at least one first peripheral marking is in the vertical direction of the failure point position, at least one second peripheral marking is in the horizontal direction of the failure point position, a straight line where the first peripheral marking is located intersects with a straight line where the second peripheral marking is located at the failure point position, and marking processing is performed on both sides of the straight line where the first peripheral marking is located to obtain an alarm marking group, where the alarm marking group includes at least two alarm markings, the alarm marking is divided into a first alarm marking and a second alarm marking, and marking processing is performed between the straight line where the first alarm marking is located and the straight line where the second alarm marking is located to obtain a target marking group, where the target marking group includes at least one target marking, and the straight line where the target marking is located intersects with the failure point position.
In one embodiment of the invention, the protection processing module 230 may be used to attach a protective layer at the location of the failure point. Specifically, after the failure point position, the peripheral mark group, the warning mark group and the target mark group are obtained, a protective layer may be plated near the failure point position of the semiconductor chip, and the protective layer may be made of platinum Pt, tungsten W, carbon C, or the like. The protective layer can protect the failure point and prevent the focused ion beam cutting instrument from damaging the failure point when the focused ion beam cutting instrument slices a semiconductor chip. After the protective layer is coated, the failure point location 110, the warning mark group and the target mark group may be located in the protective layer, and the peripheral mark group may be located at the periphery of the protective layer.
In an embodiment of the present invention, the first dicing module 240 may be configured to perform a dicing process on the failure point positions of the semiconductor chips according to the peripheral mark group to obtain initial dicing. The first slicing module 240 may be specifically configured to slice the position of the first peripheral mark along the horizontal direction at one side of the failure point position, stop when the edge of the slice is located at one side of the second peripheral mark, slice the other side of the failure point position along the horizontal direction, and stop when the edge of the slice is located at one side of the second peripheral mark, so as to obtain an initial slice, where the initial slice is in a plate-shaped structure.
In one embodiment of the present invention, the second slicing module 250 may be configured to slice the initial slice according to the warning flag set and the target flag set to generate a target slice. The second slicing module 250 may be specifically configured to perform refinement on one side of the initial slice, remove the first warning mark until the edge of the slice contacts the target mark group, perform refinement on the other side of the initial slice, and remove the second warning mark until the edge of the slice contacts the target mark group, so as to generate the target slice.
In an embodiment of the present invention, the third slicing module 260 may be configured to slice a target slice of a semiconductor chip to obtain a failure point sample. Specifically, after the target slice is obtained, since both sides of the target slice are connected to the semiconductor chip, both sides of the target slice need to be cut off to separate the target slice from the semiconductor chip. During the cutting process, the side face of the initial slice can be sliced by an electron beam emitted by a focused ion beam cutting instrument, and the intensity of the electron beam can be in the range of 70 to 90pa, for example, 70pA, 80pA or 90pA. After the two sides of the target slice are separated from the semiconductor chip, a failure point sample wafer can be obtained, and then the failure point position of the failure point sample wafer can be sliced through a transmission electron microscope.
In the description of the present specification, reference to the description of the terms "present embodiment," "example," "specific example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A method for slicing a position of a failure point of a semiconductor chip is characterized by comprising the following steps:
acquiring a failure point position;
performing combined marking processing on the periphery of the failure point position to obtain a combined marking position, wherein the combined marking position comprises a peripheral marking group, a warning marking group and a target marking group;
slicing the position of the failure point according to the peripheral mark group to obtain an initial slice;
performing fine modification processing on the initial slice according to the warning mark group and the target mark group to generate a target slice;
and slicing the target slice to obtain a failure point sample.
2. The method of claim 1, wherein the step of performing the combined mark processing on the periphery of the failure point position to obtain the combined mark position comprises:
and marking in the horizontal direction and the vertical direction of the position of the failure point to obtain a peripheral mark group, wherein the peripheral mark group comprises a first peripheral mark and a second peripheral mark.
3. The method for dicing positions of failure points of a semiconductor chip according to claim 2, wherein after the step of performing marking processing in the horizontal direction and the vertical direction of the positions of failure points and obtaining the peripheral mark group, the method further comprises:
and marking two sides of the straight line of the first peripheral mark to obtain a warning mark group, wherein the warning mark group comprises a first warning mark and a second warning mark.
4. The method for dicing positions of failure points of a semiconductor chip according to claim 3, wherein after the step of performing marking processing on both sides of the straight line where the first peripheral mark is located to obtain the warning mark group, the method further comprises:
and marking between the straight line of the first warning mark and the straight line of the second warning mark to obtain a target mark group.
5. The method of dicing a position of a failure point of a semiconductor chip according to claim 2, wherein the first peripheral mark is located in a vertical direction of the position of the failure point, the second peripheral mark is located in a horizontal direction of the position of the failure point, and a straight line in which the first peripheral mark is located intersects a straight line in which the second peripheral mark is located at the position of the failure point.
6. The method of dicing a position of a failure point of a semiconductor chip according to claim 3, wherein the straight line on which the first warning mark is located and the straight line on which the second warning mark is located are parallel to each other.
7. The method of claim 1, wherein before the step of slicing the location of the failure point according to the peripheral mark group to obtain an initial slice, the method further comprises:
and attaching a protective layer at the position of the failure point, wherein the peripheral mark group is positioned outside the protective layer, and the warning mark group and the target mark group are positioned inside the protective layer.
8. The method of claim 1, wherein the step of slicing the position of the failure point according to the peripheral mark group to obtain an initial slice comprises:
slicing the position of the first peripheral mark along the horizontal direction at one side of the failure point position until the edge of the slice is positioned at one side of the second peripheral mark;
and slicing the other side of the position of the failure point along the horizontal direction until the edge of the slice is positioned on one side of the second peripheral mark, and obtaining an initial slice.
9. The method as claimed in claim 1, wherein the step of generating the target slice by performing a fine modification process on the initial slice according to the warning mark group and the target mark group comprises:
performing fine modification treatment on one side of the initial slice, and cutting off the first warning mark until the edge of the slice contacts with the target mark group;
and performing fine modification treatment on the other side of the initial slice, and cutting off the second warning mark until the edge of the slice contacts with the target mark group to generate a target slice.
10. A dicing apparatus for a position of a failure point of a semiconductor chip, comprising:
the position acquisition module is used for acquiring the position of a failure point;
the mark processing module is used for carrying out combined mark processing on the periphery of the failure point position to obtain a combined mark position, wherein the combined mark position comprises a peripheral mark group, a warning mark group and a target mark group;
the first slicing module is used for slicing the position of the failure point according to the peripheral mark group to obtain an initial slice;
the second slicing module is used for performing fine modification processing on the initial slices according to the warning mark group and the target mark group to generate target slices; and
and the third slicing module is used for slicing the target slice to obtain a failure point sample.
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