CN115882995A - FPGA module and audio conversion equipment - Google Patents
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Abstract
The invention discloses an FPGA module and audio conversion equipment adopting the module, which comprises: network module, clock module and host system, the clock module includes: the clock calibration unit is used for generating parallel data, receiving clock frequency difference from the main control module and adjusting the generated parallel data according to the clock frequency difference; the serialization unit is used for carrying out parallel-serial conversion on the parallel data to obtain a basic clock signal; a counting unit for generating a time stamp according to the basic clock signal; the network module obtains a timestamp of the message leaving the time according to the message type in the PTP message, the main control module calculates time difference and network delay according to the timestamp obtained by the network module, and then obtains the clock frequency difference according to a preset rule. According to the invention, the hardware timestamp is generated through the FPGA internal module, and the timestamps at the end-to-end terminals of the network are obtained, so that the calculation of internal delay on the time difference is reduced, and the clock synchronization accuracy is improved.
Description
Technical Field
The invention relates to the field of clock synchronization, in particular to an FPGA (field programmable gate array) module and audio conversion equipment comprising the same.
Background
Precision Time Protocol (PTP), a Protocol used to synchronize clocks in a computer network, achieves clock accuracy in the sub-microsecond range in a local area network, and makes it suitable for measurement and control systems.
In the same local area network, the slave node keeps synchronization with the master node in the same local area network through the network, in the prior art, the master node and the slave node generally generate local clock signals through special clock chips, and the devices run a PTP protocol to send Sync, delay _ Req and Delay _ Resq instructions to finish time calibration of the slave node, so as to achieve the purpose of clock synchronization. However, the use of a dedicated clock chip is very limited by the supply of the chip manufacturer, and the hardware cost is relatively high. In addition, the time difference offset between the master node and the slave node is changed due to asynchronous clock frequencies, and in the prior art, when synchronous calibration is realized according to a PTP protocol, the delay of a PTP message in equipment and the jitter of network delay due to network environment change and other reasons are not considered, so that the obtained time difference is influenced, the acquisition of the clock frequency difference is further influenced, and the accuracy of the realized clock synchronization is not high enough.
Disclosure of Invention
In view of the above, because the existing clock synchronization accuracy is not high enough, the invention provides an FPGA module and an audio conversion device including the FPGA module, which generate a hardware timestamp through an FPGA internal module and acquire timestamps at end-to-end terminals of a network, thereby reducing the influence of internal delay and network delay on time difference calculation and improving the clock synchronization accuracy.
In order to solve the above problems, the present invention provides an FPGA module, which implements clock synchronization based on a PTP protocol, including: the network module receives and sends PTP messages according to a network protocol, the master control module synchronously calibrates the clock module, and the clock module comprises:
the clock calibration unit is used for generating parallel data, receiving clock frequency difference from the main control module and adjusting the generated parallel data according to the clock frequency difference;
the serialization unit is used for carrying out parallel-serial conversion on the parallel data to obtain a basic clock signal;
a counting unit for generating a time stamp according to the basic clock signal;
the network module obtains a timestamp of the message when the message is separated from the PTP message according to the message type in the PTP message, the main control module calculates time difference and network delay according to the timestamp obtained by the network module, and then obtains the clock frequency difference according to a preset rule.
The PTP messages comprise a Sync message, a Delay _ Req message and a Delay _ Resq message, the FPGA module is applied to a master node and a slave node, the time for the master node and the slave node to interact with a group of PTP messages is a synchronization period, one synchronization period corresponds to a time difference, network Delay and synchronization time point, and the synchronization time point is a time point in the synchronization period.
Further, in order to reduce interference of the internal delay of the device on the network delay and the time difference calculation, for any synchronization period, acquiring the corresponding time difference and the network delay includes:
the master node sends a Sync message, and a network module of the master node acquires a first timestamp of the Sync message when the Sync message leaves the network module and encapsulates the acquired first timestamp in the Sync message;
the slave node receives the Sync message, and a network module of the slave node acquires a second timestamp of the Sync message when the Sync message leaves the network module; the master control module of the slave node receives the Sync message and the second timestamp from the network module, and analyzes the first timestamp from the Sync message;
the slave node sends the Delay _ Req message, and a network module of the slave node acquires a third timestamp of the Delay _ Req message when the Delay _ Req message leaves the network module and sends the third timestamp to a main control module of the slave node;
the main node receives a Delay _ Req message, and a network module of the main node acquires a fourth timestamp of the Delay _ Req message when the Delay _ Req message leaves the main node;
the master node sends the Delay _ Resq message, and a network module of the master node encapsulates the fourth timestamp in the Delay _ Resq message;
the slave node receives the Delay _ Resq message, a network module of the slave node receives the Delay _ Resq message and sends the Delay _ Resq message to the main control module, and the main control module analyzes the fourth time stamp from the Delay _ Resq message;
and the master control module of the slave node calculates the time difference and the network delay between the master node and the slave node according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp.
Furthermore, in order to reduce the influence of network Delay jitter on the time difference acquisition in a synchronization cycle, in order to make the first timestamp closer to the third timestamp, the master control module of the slave node predicts the time for the master node to send the Sync message, and controls the slave node to send the Delay _ Req message according to the predicted time.
Wherein, the preset rule is as follows: setting a calibration period, and acquiring a clock frequency difference once by the main control module in each calibration period.
As an embodiment, in order to further reduce interference of network delay jitter to a time difference, for each calibration period, the acquiring, by the master control module, the clock frequency difference includes:
setting a plurality of statistical periods in a calibration period, wherein the statistical periods comprise a plurality of synchronous periods;
taking the time difference corresponding to the synchronization period with the minimum network delay as the preferred time difference in each statistical period;
and performing linear fitting on the optimal time difference of each statistical period and the corresponding synchronous time point to obtain the clock frequency difference in the calibration period.
As another embodiment, for each calibration period, the acquiring, by the master control module, the clock frequency difference includes:
the calibration period comprises a plurality of synchronization periods;
and selecting any two synchronous periods, and calculating the clock frequency difference according to the time difference and the synchronous time point corresponding to the selected synchronous periods.
For convenience of operation, for any synchronization period, its corresponding synchronization time point is its first timestamp.
In addition, the invention also discloses audio conversion equipment, and the FPGA module of the audio conversion equipment is disclosed.
The audio conversion equipment also comprises an analog-to-digital conversion module and a digital-to-analog conversion module, wherein the analog-to-digital conversion module is accessed to an analog audio signal and converts the analog audio signal into a digital audio signal; the digital-to-analog conversion module converts the digital audio signal into an analog audio signal and outputs the analog audio signal; the FPGA module also comprises a coding and decoding module, the coding and decoding module realizes the conversion between digital audio signals and IP audio streams, and the IP audio streams refer to the digital audio signals capable of being transmitted in a network; and the network module in the FPGA module sends and receives the IP audio stream according to a network protocol.
Compared with the prior art, the invention has the following advantages:
according to the FPGA module, parallel data are converted in a parallel-serial mode to generate clock signals, and therefore when the time difference between the master node and the slave node is obtained based on a PTP (precision time protocol), time delay interference inside equipment and interference caused by network instability are reduced as much as possible, the obtained time difference is closer to a real time difference, and therefore the clock frequency difference between the master node and the slave node is obtained based on the obtained time difference, and accurate clock synchronization is achieved; the audio conversion equipment adopts the FPGA module to realize the synchronization among the equipment in the same network, and ensures the reliability and the stability of IP audio stream transmission.
Drawings
FIG. 1 is a block diagram of an audio conversion device according to the present invention;
FIG. 2 is a block diagram of the FPGA module of FIG. 1;
FIG. 3 is a schematic diagram of the connection between the master node and the slave node in the same network for implementing clock synchronization through PTP protocol;
FIG. 4 is a schematic diagram of a process for implementing clock synchronization between a master node and a slave node in the same network through a PTP protocol;
FIG. 5 is a schematic diagram of the time difference between a master node and a slave node in a symmetric network over time;
fig. 6 is a schematic diagram of the time difference between the master node and the slave node in the asymmetric network as a function of time.
Detailed Description
The present invention will be further described with reference to the following examples.
In fig. 1, the audio conversion apparatus 100 of the present invention includes an FPGA module, an analog-to-digital conversion module, and a digital-to-analog conversion module, where the FPGA module includes: the device comprises a network module, a coding and decoding module, a clock module and a main control module; an analog-to-digital conversion module, which is connected to an analog audio input interface (not shown), and is used for accessing an analog audio signal and converting the analog audio signal into a digital audio signal; a digital-to-analog conversion module, connected to an analog audio output interface (not shown), for converting the digital audio signal into an analog audio signal and outputting the analog audio signal; a network module connected to a network interface (not shown), receiving and transmitting network data according to a network protocol, and acquiring a timestamp from the clock module; the coding and decoding module is used for realizing conversion between the digital audio signal and the IP audio stream; the clock module is used for generating a clock signal required by timestamp and digital audio signal transmission in the equipment, and for convenience of description, the clock signal is called as a working clock signal; and the main control module controls each module in the FPGA module to work and synchronously calibrates the clock module.
The network protocol may be an ethernet protocol, the IP audio stream refers to a digital audio signal capable of being transmitted in a network, for example, a data stream satisfying the protocols such as AES67, NDI, SRT, etc., that is, the main function of the audio conversion apparatus 100 is to realize the interconversion between the IP audio stream and the analog audio signal. The operating clock signals are related to the transmission protocol used by the device, such as the common digital audio transmission standard I2S (Inter-IC Sound), and include BCLK, SCLK, MCLK, and WCLK, and the frequency of the operating clock signals is an integer multiple of the audio sampling rate.
The application of the above audio conversion device in a communication network inevitably needs to satisfy network clock synchronization to ensure the reliability and stability of data transmission. The following description focuses on the clock module in the FPGA module.
As an implementation manner, a precision clock synchronization protocol (PTP) is adopted in the present invention to implement clock synchronization between the audio conversion devices in the same network. As shown in fig. 2, the clock module of the present invention includes a clock calibration unit, a serialization unit, a clock generation unit, and a counting unit; the clock calibration unit generates parallel data, receives clock frequency difference and adjusts the output parallel data according to the clock frequency difference; the serialization unit receives the parallel data and performs parallel-serial conversion on the parallel data to obtain a basic clock signal; the clock generating unit generates a working clock signal according to the basic clock signal; the counting unit generates a time stamp from the base clock signal.
When the clock calibration unit generates the parallel data, the frequency of the working clock can be referred to, I2S is taken as an example, and the adopted working clock signals are all integer multiples of the audio sampling rate, so that the frequency of the basic clock signal is set to be N times (N is a power of 2) of the audio sampling rate, and the working clock signal can be obtained through a counting frequency division mode (50% duty ratio), so that the frequency of the generated working clock is more stable, and the total harmonic distortion and the signal-to-noise ratio of the audio can be improved.
The clock frequency difference refers to the difference between the clock frequencies of the master node and the slave node to be synchronized, and can be reflected by a counting ratio like a timestamp. For the sake of statistics, the clock frequency difference may be set in ppb (part per billion). As an implementation mode, the serialization unit in the invention can be realized by using a SerDes (Multi-Gigabit Serializer/Deserializer), the frequency of serial data generated by a SerDes module is generally above 5GHz, and the precision of clock regulation can reach at least 0.2ns.
Assuming that the basic clock signal is 100Hz and the serializing unit frequency is 5GHz, the clock calibration unit periodically outputs the parallel data 0x3FFFFFE000000 to obtain the basic clock signal, i.e. the frequency of the basic clock signal is adjusted by the high and low bits. If the frequency difference between the slave node and the master node is +100ppb, the actual clock frequency of the slave node is 100MHz +100ppb 100MHz =100.00001MHz, and the clock cycle difference between the master node and the slave node is 10 3 * (1/100-1/00.00001) ns, i.e. passing N =0.2/[10 ] 3 *(1/100-1/00.00001)]After the bits are positioned, namely after about 20 ten thousand times, the master node is slower than the slave node by 0.2ns, so that the parallel data of the slave node is adjusted, and one high bit is added every 20 ten thousand cycles, so that the same frequency of the basic clocks of the master node and the slave node can be realized.
With reference to fig. 1 and fig. 2, the network module transmits and receives PTP messages in the network according to a network protocol, acquires a timestamp of the PTP message when the PTP message is separated from the network according to a type of the PTP message, and transmits the acquired timestamp to the main control module; and the master control module calculates the clock frequency difference according to the received time stamp and sends the clock frequency difference to a clock calibration unit in the clock module.
PTP messages include a Header (Header), a Body (Body), and an addition (Suffix), some fields in the Header mark the type of the message, taking PTPv2 as an example, a messageId field in the Header identifies the type of the message, and the Sync message, the Delay _ Req message, and the Delay _ Resq message referred to in the following embodiments all correspond to different message type identifications.
As an embodiment, as shown in fig. 3, both the master node 200 and the slave node 300 located in the same local area network include the clock module shown in fig. 2, the module structures of the master node 200 and the slave node 300 may be the same as the module structure of the audio conversion device 100 in fig. 1, and may also include other functional modules, and fig. 3 only illustrates the modules related to implementing clock synchronization. According to the PTP protocol specification, a plurality of devices interconnected through a network can select a device with high time accuracy as a master node through an Announce message, and only the clock synchronization process after the master node is determined is described in this embodiment. As shown in fig. 4, the master node and the slave node periodically transmit and receive PTP packet groups through the network module, and in each synchronization period, the method includes the following steps:
the master node 200 sends a Sync message, when the Sync message passes through a network module away from the master node 200, the network module of the master node 200 acquires a first timestamp T1 from a counting unit of the network module, and encapsulates the acquired first timestamp T1 in the Sync message;
receiving a Sync message from the slave node 300, acquiring a second timestamp T2 from a counting unit of the network module of the slave node 300 when the Sync message reaches the network module of the slave node 300, and sending the Sync message and the second timestamp T2 to a master control module of the slave node 300;
a master control module of the slave node 300 receives a Sync message and analyzes the Sync message to obtain a first time stamp T1 and a second time stamp T2;
the slave node 300 sends a Delay _ Req message, when the Delay _ Req message passes through a network module away from the slave node 300, the network module of the slave node 300 acquires a third timestamp T3 from a counting unit thereof, and sends the third timestamp T3 to a master control module of the slave node;
the main node 200 receives the Delay _ Req message, when the Delay _ Req message reaches the network module of the main node 200, the network module of the main node 200 acquires a fourth time stamp T4 from a counting unit thereof, encapsulates the fourth time stamp T4 in the Delay _ Resq message, and the main node 200 sends the Delay _ Resq message;
the slave node 300 receives the Delay _ Resq message, and the master control module of the slave node 300 analyzes the Delay _ Resq message to obtain a fourth timestamp T4 therein. Up to this point, the first time stamp T1, the second time stamp T2, the third time stamp T3 and the fourth time stamp T4 are known to the master module of the slave node 300.
In the above embodiment, only the steps of implementing the clock synchronization mode by using the single-step mode under the request-response mechanism are described, and the FPGA module in the present invention is also applicable to the double-step mode.
For each synchronization period, the master control module of the slave node 300 can obtain the unidirectional network delays between the master node and the slave node in the network as Delay _1 and Delay _2 and the time differences Offset _1 and Offset _2 corresponding to the synchronization time points T1 and T3 according to the first time stamp T1, the second time stamp T2, the third time stamp T3 and the fourth time stamp T4, and the calculation formula is as follows:
T1 + Delay_1 + Offset_1=T2；
T3+ Delay_2 – Offset_2=T4。
with reference to the above formula, in a symmetric network, that is, when the network Delay is stable (Delay _1= Delay _ 2), as shown in fig. 5, where the change rates of the clocks of the master node and the slave node along with the time t are the clock frequencies of the master node and the slave node, respectively, and the clock frequency of the slave node 300 is higher than the clock frequency of the master node 200, the time difference Offset will be larger and larger, and increase linearly; similarly, if the clock frequency of the slave node 300 is lower than the clock frequency of the master node 200, the time difference Offset is smaller and smaller, and the linearity is reduced; if the clock frequency of the slave node 300 matches the clock frequency of the master node 200, the Offset at any time remains unchanged (not shown), i.e., the slave node 300 and the master node 200 are relatively synchronized. The present embodiment performs clock frequency calibration on the slave node 300 by the clock frequency difference, so that the clock frequencies between the master node 200 and the slave node 300 tend to be consistent. In the prior art, in each synchronization period, it is further assumed that the time difference between the synchronization time points is stable, i.e. Offset _1= Offset_2, and then:
Delay_1= Delay_2 =[ (T2 – T1)+ (T4 – T3)]/2；
Offset_1= Offset_2= [(T2 –T1) – (T4 – T3)]/2。
obviously, the time difference obtained in this way is not accurate enough, based on the above analysis, in order to more accurately obtain the clock frequency difference through the time difference Offset to improve the clock calibration precision, the time for the master node 200 to send the Sync message and the time for the slave node 300 to send the Delay _ Req message should be kept consistent as much as possible, and in this embodiment, a further improvement is made, for each synchronization period, before the slave node 300 sends the Delay _ Req message, the master control module of the slave node 300 predicts the time for the master node to send the Sync message (the PTP message group sending period and the message sending interval are fixed), and then sends the Delay _ Req message according to the predicted time.
How the present embodiment obtains the clock frequency difference from the time difference Offset will be specifically described below.
In the above and fig. 5, taking the example that the clock frequency of the slave node 300 is higher than the clock frequency of the master node 200, each synchronization period corresponds to a synchronization time point, such as t1, t2, t3, t4 \8230, tn, and the time differences Offset corresponding to the synchronization periods (i.e. the synchronization time points) are Offset respectively 1 、Offset 2 、Offset 3 、Offset 4 …，Offset n For convenience of operation, T1, T2, T3, T4 \8230, tn may be the first time stamp T1 of each synchronization period, and obviously, the clock frequency difference in fig. 5 is fixed and does not change with the passage of time. In any calibration period (including several synchronization periods), the master control module of the slave node 300 obtains the clock frequency difference corresponding to any two synchronization periods, that is, calculates according to the time difference corresponding to the selected synchronization period and the synchronization time pointAnd the clock frequency difference is sent to the clock calibration unit, the clock calibration unit changes the output parallel data according to the clock frequency difference, and the basic clock signal generated by the corresponding serialization unit changes, so that the frequency synchronization between the master node and the slave node is realized.
For example, if the calibration period is two synchronization period intervals in fig. 5, it includes at least two synchronization periods, and if a certain calibration period includes a synchronization period one (corresponding to the synchronization time point t 1) and a synchronization period two (corresponding to the synchronization time point t 2), the clock frequency difference of the calibration period is (Offset) 2 – Offset 1 )/(t2 –t1)。
When a network receives and sends packets, it is inevitable that network Delay jitter occurs due to switch congestion, network asymmetry, and the like, and the actually obtained time difference Offset is as shown in fig. 6, so that in order to further improve the accuracy of clock calibration, the present embodiment further improves the method for obtaining the clock frequency difference, specifically:
setting a plurality of statistical periods in each calibration period, wherein any statistical period comprises a plurality of synchronous periods, and acquiring a time difference Offset corresponding to the synchronous period with the minimum network Delay in the statistical period as an optimal time difference in the statistical period;
and in the calibration period, performing linear fitting according to the optimal time difference obtained in each statistical period and the corresponding synchronous time point to obtain the clock frequency difference in the calibration period.
For example, each synchronization period corresponds to a synchronization time point, such as t1, t2, t3, t4 \8230inFIG. 6, tn, and the time difference Offset corresponding to each synchronization period (i.e. each synchronization time point) is Offset 1 、Offset 2 、Offset 3 、Offset 4 …，Offset n In combination with the above, each synchronization period has a corresponding network Delay and time Offset, and it is assumed that one calibration period includes two statistical periods, each statistical period includes two synchronization periods, and a time period (0, t 4) is a calibration period, and includes two statistical periods, which are a time period (0, t 2) and a time, respectivelySegment (t 2, t 4) set in the network Delay corresponding to the synchronization time point t2 in the first statistical period 2 At a minimum, the preferred time difference over the statistical period is Offset 2 (ii) a If the network Delay corresponding to the time point t3 is synchronized in the second statistical period 3 At a minimum, the preferred time difference over the statistical period is Offset 3 Then the preferred time difference is Offset 3 Obviously, the clock frequency difference in the calibration period is (Offset) obtained by means of linear fitting 3 – Offset 2 )/(t3 –t2)。
The time difference of the node corresponding to the minimum network delay is obtained as the optimal time difference by setting the statistical period, so that Offset jitter caused by network abnormality can be greatly reduced, and the precision of clock synchronization calibration is improved.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the embodiments, and various equivalent modifications can be made within the technical spirit of the present invention, and the scope of the present invention is also within the scope of the present invention.
Claims (10)
1. The utility model provides a FPGA module, realizes clock synchronization based on PTP agreement, includes: the network module receives and sends PTP messages according to a network protocol, and the master control module synchronously calibrates the clock module, and is characterized in that the clock module comprises:
the clock calibration unit is used for generating parallel data, receiving clock frequency difference from the main control module and adjusting the generated parallel data according to the clock frequency difference;
the serialization unit is used for carrying out parallel-serial conversion on the parallel data to obtain a basic clock signal;
a counting unit for generating a time stamp according to the basic clock signal;
the network module obtains a timestamp of the message when the message is separated from the PTP message according to the message type in the PTP message, the main control module calculates time difference and network delay according to the timestamp obtained by the network module, and then obtains the clock frequency difference according to a preset rule.
2. The FPGA module of claim 1, wherein the PTP messages include a Sync message, a Delay _ Req message, and a Delay _ Resq message, and the FPGA module is applied to a master node and a slave node, a time when the master node and the slave node interact with each other through a set of PTP messages is a synchronization period, one synchronization period corresponds to one time difference, one network Delay, and one synchronization time point, and the synchronization time point is one time point in the synchronization period.
3. The FPGA module of claim 2, wherein for any synchronization period, obtaining the corresponding time difference and network delay comprises:
the master node sends a Sync message, and a network module of the master node acquires a first timestamp of the Sync message when the Sync message leaves the network module and encapsulates the acquired first timestamp in the Sync message;
the slave node receives the Sync message, and a network module of the slave node acquires a second timestamp of the Sync message when the Sync message leaves the network module; the master control module of the slave node receives the Sync message and the second timestamp from the network module, and analyzes the first timestamp from the Sync message;
the slave node sends the Delay _ Req message, and a network module of the slave node acquires a third timestamp of the Delay _ Req message when the Delay _ Req message leaves the network module and sends the third timestamp to a main control module of the slave node;
the main node receives a Delay _ Req message, and a network module of the main node acquires a fourth timestamp of the Delay _ Req message when the Delay _ Req message leaves the main node;
the master node sends the Delay _ Resq message, and a network module of the master node encapsulates the fourth timestamp in the Delay _ Resq message;
the slave node receives the Delay _ Resq message, a network module of the slave node receives the Delay _ Resq message and sends the Delay _ Resq message to the main control module, and the main control module analyzes the fourth time stamp from the Delay _ Resq message;
and the master control module of the slave node calculates the time difference and the network delay between the master node and the slave node according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp.
4. The FPGA module of claim 3, wherein the master control module of the slave node predicts a time when the master node transmits the Sync message, and controls the slave node to transmit the Delay _ Req message according to the predicted time.
5. The FPGA module of claim 4, wherein the predetermined rule is: setting a calibration period, and acquiring a clock frequency difference once by the master control module in each calibration period.
6. The FPGA module of claim 5, wherein the obtaining of the clock frequency difference by the master module for each calibration cycle comprises:
setting a plurality of statistical periods in a calibration period, wherein the statistical periods comprise a plurality of synchronous periods;
taking the time difference corresponding to the synchronization period with the minimum network delay as the preferred time difference in each statistical period;
and performing linear fitting on the optimal time difference of each statistical period and the corresponding synchronous time point to obtain the clock frequency difference in the calibration period.
7. The FPGA module of claim 5, wherein the obtaining the clock frequency difference by the master module for each calibration cycle comprises:
the calibration period comprises a plurality of synchronization periods;
and selecting any two synchronous periods, and calculating the clock frequency difference according to the time difference and the synchronous time point corresponding to the selected synchronous periods.
8. The FPGA module according to claim 6 or 7, wherein for any synchronization cycle, the corresponding synchronization time point is the first timestamp thereof.
9. Audio conversion device, characterized in that it comprises an FPGA module according to any one of claims 1 to 8.
10. The audio conversion device of claim 9, further comprising an analog-to-digital conversion module and a digital-to-analog conversion module, wherein the analog-to-digital conversion module is connected to the analog audio signal and converts the analog audio signal into a digital audio signal; the digital-to-analog conversion module converts the digital audio signal into an analog audio signal and outputs the analog audio signal; the FPGA module also comprises a coding and decoding module, the coding and decoding module realizes the conversion between digital audio signals and IP audio streams, and the IP audio streams refer to the digital audio signals which can be transmitted in a network; and the network module in the FPGA module sends and receives the IP audio stream according to a network protocol.
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