CN115882995B - FPGA module and audio conversion equipment - Google Patents
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Abstract
The invention discloses an FPGA module and an audio conversion device adopting the same, comprising: the system comprises a network module, a clock module and a main control module, wherein the clock module comprises: the clock calibration unit is used for generating parallel data, receiving clock frequency difference from the main control module and adjusting the generated parallel data according to the clock frequency difference; the serializing unit is used for carrying out parallel-serial conversion on the parallel data to obtain a basic clock signal; a counting unit for generating a time stamp according to the base clock signal; the network module obtains the time stamp of the message after the message is separated according to the message type in the PTP message, the main control module calculates the time difference and the network delay according to the time stamp obtained by the network module, and then obtains the clock frequency difference according to a preset rule. According to the invention, the hardware time stamp is generated through the FPGA internal module, the time stamp at the end-to-end position of the network is obtained, the calculation of internal delay on the time difference is reduced, and the clock synchronization accuracy is improved.
Description
Technical Field
The invention relates to the field of clock synchronization, in particular to an FPGA module and audio conversion equipment comprising the same.
Background
The precision time synchronization protocol (Precision Time Protocol, PTP), a protocol for synchronizing clocks in a computer network, achieves clock accuracy in the sub-microsecond range in a local area network, making it suitable for use in measurement and control systems.
In the same local area network, the slave node keeps synchronous with the master node in the same local area network through the network, in the prior art, the master node and the slave node generally generate local clock signals through special clock chips, and a PTP protocol is operated among devices to send Sync, delay_req and delay_Resq instructions to finish the time calibration of the slave node, so that the aim of clock synchronization is fulfilled. However, the use of dedicated clock chips is highly limited by the supply of the chip manufacturer and the hardware costs are relatively high. In addition, the time difference offset between the master node and the slave node is changed due to the fact that clock frequencies are not synchronized, when synchronization calibration is achieved according to a PTP protocol in the prior art, delay of a PTP message in equipment is not considered, network delay is dithered due to network environment change and the like, the obtained time difference is further affected, the obtaining of the clock frequency difference is further affected, and the achieved clock synchronization accuracy is not high enough.
Disclosure of Invention
In view of the above, the invention provides an FPGA module and an audio conversion apparatus including the FPGA module, which generate a hardware timestamp through an FPGA internal module and obtain a timestamp at a network end-to-end position, so as to reduce the influence of internal delay and network delay on time difference calculation and improve clock synchronization accuracy.
In order to solve the above problems, the present invention provides an FPGA module, which realizes clock synchronization based on PTP protocol, comprising: the network module receives and transmits PTP messages according to a network protocol, the master control module synchronously calibrates the clock module, and the clock module comprises:
the clock calibration unit is used for generating parallel data, receiving clock frequency difference from the main control module and adjusting the generated parallel data according to the clock frequency difference;
the serializing unit is used for carrying out parallel-serial conversion on the parallel data to obtain a basic clock signal;
a counting unit for generating a time stamp according to the base clock signal;
the network module obtains the time stamp of the message after the message is separated according to the message type in the PTP message, the main control module calculates the time difference and the network delay according to the time stamp obtained by the network module, and then obtains the clock frequency difference according to a preset rule.
The method comprises the steps that the PTP message comprises a Sync message, a delay_Req message and a delay_Resq message, the FPGA module is applied to a master node and a slave node, the time of interaction of a group of PTP messages by the master node and the slave node is a synchronization period, one synchronization period corresponds to one time difference, network Delay and synchronization time point, and the synchronization time point is one time point in the synchronization period.
Further, to reduce interference of internal delay of the device on calculation of the network delay and the time difference, for any synchronization period, obtaining the corresponding time difference and the network delay includes:
the method comprises the steps that a master node sends a Sync message, a network module of the master node obtains a first time stamp of the Sync message after the Sync message is separated from the network module, and the obtained first time stamp is packaged in the Sync message;
the slave node receives the Sync message, and a network module of the slave node acquires a second timestamp of the Sync message after the Sync message is separated from the network module; the master control module of the slave node receives the Sync message and the second timestamp from the network module and analyzes the first timestamp from the Sync message;
the slave node sends the delay_req message, and a network module of the slave node obtains a third timestamp of the delay_req message after the delay_req message is separated and sends the third timestamp to a main control module of the slave node;
the master node receives the delay_req message, and a network module of the master node obtains a fourth timestamp of the delay_req message after the delay_req message is isolated;
the master node sends the delay_resq message, and a network module of the master node encapsulates the fourth timestamp in the delay_resq message;
the slave node receives the delay_resq message, a network module of the slave node receives the delay_resq message and sends the delay_resq message to the master control module, and the master control module analyzes the fourth timestamp from the delay_resq message;
and the master control module of the slave node calculates the time difference and the network delay between the master node and the slave node according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp.
Furthermore, in order to reduce the influence of network Delay jitter on the time difference acquisition in a synchronization period, in order to make the first time stamp more approximate to the third time stamp, the master control module of the slave node predicts the time for sending the Sync message by the master node, and controls the slave node to send the delay_req message according to the predicted time.
Wherein, the preset rule is: setting a calibration period, and acquiring a clock frequency difference once in each calibration period by the main control module.
As an implementation manner, to further reduce interference of network delay jitter on time difference, for each calibration period, the master control module obtains the clock frequency difference, including:
setting a plurality of statistical periods in the calibration period, wherein the statistical periods comprise a plurality of synchronous periods;
taking the time difference corresponding to the synchronization period with the minimum network delay in each statistical period as the preferred time difference in the statistical period;
and carrying out linear fitting on the optimal time difference of each statistical period and the corresponding synchronous time point to obtain the clock frequency difference in the calibration period.
As another embodiment, for each calibration period, the master control module obtains the clock frequency difference, including:
the calibration period comprises a number of synchronization periods;
and selecting any two synchronous periods, and calculating the clock frequency difference according to the time difference corresponding to the selected synchronous periods and the synchronous time point.
For ease of operation, for any synchronization period, its corresponding synchronization time point is its first timestamp.
In addition, the invention also discloses audio conversion equipment, and the FPGA module of the audio conversion equipment.
The audio conversion equipment further comprises an analog-to-digital conversion module and a digital-to-analog conversion module, wherein the analog-to-digital conversion module is connected with the analog audio signal and converts the analog audio signal into a digital audio signal; the digital-to-analog conversion module converts the digital audio signal into an analog audio signal and outputs the analog audio signal; the FPGA module further comprises a coding and decoding module, the coding and decoding module realizes conversion between digital audio signals and IP audio streams, and the IP audio streams refer to the digital audio signals which can be transmitted in a network; and a network module in the FPGA module sends and receives the IP audio stream according to a network protocol.
Compared with the prior art, the invention has the following advantages:
according to the invention, the FPGA module generates clock signals by parallel-serial conversion of parallel data, so that internal time delay interference of equipment and interference caused by unstable network are reduced as much as possible when the time difference of a master node and a slave node is acquired based on a PTP protocol, the acquired time difference is more similar to the real time difference, and therefore, the clock frequency difference between the master node and the slave node is obtained based on the acquired time difference, and accurate clock synchronization is realized; the audio conversion equipment adopts the FPGA module to realize the synchronization among the equipment in the same network, and ensures the reliability and stability of IP audio stream transmission.
Drawings
FIG. 1 is a block diagram of an audio conversion device according to the present invention;
FIG. 2 is a schematic block diagram of the FPGA module of FIG. 1;
fig. 3 is a schematic connection diagram of implementing clock synchronization between master and slave nodes in the same network through PTP protocol;
fig. 4 is a schematic flow chart of implementing clock synchronization between master and slave nodes in the same network through PTP protocol;
FIG. 5 is a schematic diagram of the time difference between master and slave nodes in a symmetric network over time;
fig. 6 is a schematic diagram of time differences between master and slave nodes in an asymmetric network over time.
Detailed Description
The invention will be further illustrated with reference to examples.
The audio conversion device 100 of the present invention in fig. 1 includes an FPGA module, an analog-to-digital conversion module, and a digital-to-analog conversion module, where the FPGA module includes: the system comprises a network module, a coding and decoding module, a clock module and a main control module; the analog-to-digital conversion module is connected with an analog audio input interface (not shown), is connected with an analog audio signal and converts the analog audio signal into a digital audio signal; the digital-to-analog conversion module is connected with an analog audio output interface (not shown) and used for converting the digital audio signal into an analog audio signal and outputting the analog audio signal; a network module connected to a network interface (not shown), receiving and transmitting network data according to a network protocol, and acquiring a time stamp from the clock module; the encoding and decoding module is used for realizing conversion between the digital audio signal and the IP audio stream; a clock module for generating a time stamp and a clock signal required by the transmission of the digital audio signal inside the device, wherein the clock signal is called as a working clock signal for convenience of description; and the main control module is used for controlling each module in the FPGA module to work and synchronously calibrating the clock module.
The network protocol may be an ethernet protocol, and the IP audio stream refers to a digital audio signal that can be transmitted in a network, for example, a data stream that satisfies protocols such as AES67, NDI, or SRT, that is, the main function of the audio conversion apparatus 100 is to implement mutual conversion between an IP audio stream and an analog audio signal. The aforementioned operating clock signals are related to the use of a transmission protocol by devices, such as the common digital audio transmission standard I2S (Inter-IC Sound, integrated Interchip Sound), which uses operating clock signals including BCLK, SCLK, MCLK and WCLK, each of which has a frequency that is an integer multiple of the audio sampling rate.
The application of the audio conversion device in the communication network inevitably needs to meet the synchronization of network clocks to ensure the reliability and stability of data transmission. The clock module in the FPGA module will be described with emphasis.
As an embodiment, the present invention uses precision clock synchronization protocol (PTP) to achieve clock synchronization between the audio conversion devices in the same network. As shown in fig. 2, the clock module in the present invention includes a clock calibration unit, a serialization unit, a clock generation unit, and a counting unit; the clock calibration unit generates parallel data, receives clock frequency difference and adjusts the output parallel data according to the clock frequency difference; the serialization unit receives the parallel data and performs parallel-serial conversion on the parallel data to obtain a basic clock signal; the clock generation unit generates a working clock signal according to the basic clock signal; the counting unit generates a time stamp from the base clock signal.
When the clock calibration unit generates parallel data, the frequency of the working clock can be referred to, taking I2S as an example, and because the adopted working clock signals are all integer multiples of the audio sampling rate, the frequency of the basic clock signal is set to be N times of the audio sampling rate (N is the power of 2), and the working clock signal can be obtained by a counting frequency division mode (50% duty ratio), so that the generated working clock frequency is more stable, and the improvement of the total harmonic distortion and the signal-to-noise ratio of the audio is facilitated.
The above clock frequency difference refers to the difference between the clock frequencies of the master and slave nodes to be synchronized, and can be reflected by a count ratio, like a time stamp. For ease of statistics, the clock frequency difference may be set in units of ppb (part per billion). As one implementation mode, the serializing unit can be realized by adopting a SerDes (Multi-Gigabit Serializer/Deserializer, serializer/Deserializer), and the serial data frequency generated by the SerDes module is generally above 5GHz, so that the precision in clock adjustment can reach at least 0.2ns.
Assuming that the basic clock signal is 100Hz and the frequency of the serialization unit is 5GHz, the clock calibration unit periodically outputs the parallel data 0x3FFFFFE000000 to obtain the basic clock signal, that is, adjusts the frequency of the basic clock signal through high and low bits. If the frequency difference between the slave node and the master node is +100ppb, the actual clock frequency of the slave node is 100mhz+100ppb x 100mhz= 100.00001MHz, and the clock period difference between the master and slave nodes is 10 3 * (1/100-1/00.00001) ns, i.e. through N=0.2/[ 10 ] 3 *(1/100-1/00.00001)]After the bit is set, namely about 20 ten thousand times later, the master node is 0.2ns slower than the slave node, so that the parallel data of the slave node is adjusted, and one high bit is added every 20 ten thousand periods, so that the same frequency of the basic clocks of the master node and the slave node can be realized.
With reference to fig. 1 and fig. 2, a network module sends and receives PTP messages in a network according to a network protocol, obtains a time stamp of the PTP messages when the PTP messages are separated according to a PTP message type, and sends the obtained time stamp to a main control module; the master control module calculates clock frequency difference according to the received time stamp and sends the clock frequency difference to a clock calibration unit in the clock module.
The PTP message includes a Header (Header), a Body (Body), and an additional (diffix), some fields in the Header mark the type of the message, and in the case of PTPv2, the message id field in the Header identifies the type of the message, and the Sync message, delay_req message, and delay_req message referred to in the embodiments below all correspond to different message type identifications.
As an example, as shown in fig. 3, each of the master node 200 and the slave node 300 located in the same lan includes the clock module shown in fig. 2, and the module structures of the master node 200 and the slave node 300 may be the same as those of the audio conversion device 100 in fig. 1, and may include other functional modules, and fig. 3 only shows the modules related to achieving clock synchronization. According to the PTP protocol, a plurality of devices interconnected through a network may select a device with high time accuracy as a master node through an Announce message, and this embodiment only focuses on the clock synchronization process after the master node determines. As shown in fig. 4, the master node and the slave node periodically send and receive PTP packet groups through the network module, and in each synchronization period, the method includes the following steps:
the master node 200 transmits a Sync message, and when the Sync message passes through a network module separated from the master node 200, the network module of the master node 200 acquires a first timestamp T1 from a counting unit thereof and encapsulates the acquired first timestamp T1 in the Sync message;
the slave node 300 receives the Sync message, when the Sync message reaches the network module of the slave node 300, the network module of the slave node 300 acquires a second time stamp T2 from the counting unit thereof, and sends the Sync message and the second time stamp T2 to the master control module of the slave node 300;
the method comprises the steps that a main control module of a slave node 300 receives a Sync message and analyzes the Sync message to obtain a first timestamp T1 and a second timestamp T2;
the slave node 300 sends a delay_req message, and when the delay_req message passes through a network module of the slave node 300, the network module of the slave node 300 obtains a third timestamp T3 from a counting unit of the network module of the slave node, and sends the third timestamp T3 to a master control module of the slave node;
the master node 200 receives the delay_req message, when the delay_req message reaches the network module of the master node 200, the network module of the master node 200 obtains a fourth timestamp T4 from the counting unit thereof, encapsulates the fourth timestamp T4 in the delay_req message, and the master node 200 sends the delay_req message;
the slave node 300 receives the delay_resq message, and the master control module of the slave node 300 analyzes the delay_resq message to obtain a fourth timestamp T4 therein. Up to this point, the master module of the slave node 300 knows the first timestamp T1, the second timestamp T2, the third timestamp T3 and the fourth timestamp T4.
In the above embodiment, only the step of implementing the clock synchronization mode by adopting the single-step mode under the request response mechanism is described, and the FPGA module in the present invention is also applicable to the double-step mode.
For each synchronization period, the master control module of the slave node 300 can obtain the unidirectional network Delay between the master node and the slave node in the network according to the first timestamp T1, the second timestamp T2, the third timestamp T3 and the fourth timestamp T4 as follows as delay_1 and delay_2 and the time difference offset_1 and offset_2 corresponding to the synchronization time points T1 and T3:
T1 + Delay_1 + Offset_1=T2；
T3+ Delay_2 – Offset_2=T4。
in combination with the above formula, for a symmetric network, i.e. in the case of stable network Delay (delay_1=delay_2), as shown in fig. 5, the change rates of the clocks of the master node and the slave node with time t are respectively the clock frequencies of the master node and the slave node, and the clock frequency of the slave node 300 is higher than the clock frequency of the master node 200, the time difference Offset will be larger and increases linearly; similarly, if the clock frequency of the slave node 300 is lower than the clock frequency of the master node 200, the time difference Offset will be smaller and smaller, and linearly reduced; if the clock frequency of the slave node 300 coincides with the clock frequency of the master node 200, the Offset at any time remains unchanged (not shown), i.e., the slave node 300 and the master node 200 are relatively synchronized. The clock frequency calibration is performed on the slave node 300 through the clock frequency difference, so that the clock frequencies between the master node 200 and the slave node 300 tend to be consistent. In the prior art, it is further assumed that the time difference between the synchronization time points is stable, i.e., offset_1=offset_2, at each synchronization period, and then, the following is obtained:
Delay_1= Delay_2 =[ (T2 – T1)+ (T4 – T3)]/2；
Offset_1= Offset_2= [(T2 –T1) – (T4 – T3)]/2。
it is obvious that the time difference obtained in this way is not accurate enough, based on the above analysis, in order to obtain the clock frequency difference by the time difference Offset more accurately so as to improve the clock calibration accuracy, the time when the master node 200 transmits the Sync message and the slave node 300 transmits the delay_req message should be kept consistent as much as possible, and this embodiment further improves, for each synchronization period, the slave node 300 predicts the time when the master node transmits the Sync message before transmitting the delay_req message (the PTP message group transmission period and the message transmission interval are fixed) by the master module of the slave node 300, and then transmits the delay_req message according to the predicted time.
The following will describe in detail how the present embodiment acquires the clock frequency difference from the time difference Offset.
In conjunction with the above description and fig. 5, taking the example that the clock frequency of the slave node 300 is higher than that of the master node 200, each synchronization period corresponds to a synchronization time point, for example, the time differences Offset corresponding to the synchronization periods (i.e. the synchronization time points) are respectively Offset 1 、Offset 2 、Offset 3 、Offset 4 …，Offset n For ease of operation, T1, T2, T3, T4 …, tn may be the first timestamp T1 of each synchronization period, it being apparent that the clock frequency difference in fig. 5 is fixed and does not change over time. In any calibration period (including a plurality of synchronization periods), the master control module of the slave node 300 obtains clock frequency differences corresponding to any two synchronization periods, namely, calculates the clock frequency differences according to the time differences and the synchronization time points corresponding to the selected synchronization periods, and sends the clock frequency differences to the clock calibration unit of the slave node, the clock calibration unit changes the output parallel data according to the clock frequency differences, and the basic clock signals generated by the corresponding serialization units are changed, so that frequency synchronization between the master node and the slave node is realized.
For example, if the calibration period is two synchronization period intervals in fig. 5, it includes at least two synchronization periods, and if one calibration period includes one synchronization period (corresponding to the synchronization time point t 1) and two synchronization periods (corresponding to the synchronization time point t 2), the clock frequency difference of the calibration period is (Offset) 2 – Offset 1 )/(t2 –t1)。
When the network receives and transmits the packet, the network Delay jitter caused by reasons of switch congestion, network asymmetry and the like is unavoidable, and the actually acquired time difference Offset is shown in fig. 6, so that in order to further improve the accuracy of clock calibration, the embodiment further improves the acquisition mode of the clock frequency difference, specifically:
setting a plurality of statistic periods in each calibration period, wherein any statistic period comprises a plurality of synchronization periods, and acquiring a time difference Offset corresponding to the synchronization period with the minimum network Delay in the statistic period as a preferable time difference in the statistic period;
and in the calibration period, carrying out linear fitting on the optimal time difference obtained according to each statistical period and the corresponding synchronous time point to obtain the clock frequency difference in the calibration period.
For example, each synchronization period corresponds to a synchronization time point, such as t1, t2, t3, t4 …, tn in fig. 6, and the time difference Offset corresponding to each synchronization period (i.e. each synchronization time point) is Offset 1 、Offset 2 、Offset 3 、Offset 4 …，Offset n In combination with the above, each synchronization period has a corresponding network Delay and a time difference Offset, and assuming that two statistics periods are included in one calibration period, each statistics period includes two synchronization periods, and a time period (0, t 4) is set as one calibration period, two statistics periods are included in the calibration period, and are respectively a time period (0, t 2) and a time period (t 2, t 4), and the network Delay corresponding to the synchronization time point t2 in the first statistics period is set 2 Minimum, the preferred time difference in the statistical period is Offset 2 The method comprises the steps of carrying out a first treatment on the surface of the In the second statistical period, if the network Delay corresponding to the synchronization time point t3 is the same 3 Minimum, the preferred time difference in the statistical period is Offset 3 Then the preferred time difference is Offset 3 It is apparent that the clock frequency difference in the calibration period is obtained by linear fitting as (Offset 3 – Offset 2 )/(t3 –t2)。
The time difference of the node corresponding to the minimum network time delay is obtained through setting the statistical period to serve as the optimal time difference, offset jitter caused by network abnormality can be greatly reduced, and the accuracy of clock synchronization calibration is improved.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific details of the above embodiments, and various equivalent changes can be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all the equivalent changes belong to the protection scope of the present invention.
Claims (10)
1. An FPGA module for implementing clock synchronization based on PTP protocol, comprising: the network module receives and transmits PTP messages according to a network protocol, and the master control module synchronously calibrates the clock module, and is characterized in that the clock module comprises:
the clock calibration unit is used for generating parallel data, receiving clock frequency difference from the main control module and adjusting the generated parallel data according to the clock frequency difference;
the serializing unit is used for carrying out parallel-serial conversion on the parallel data to obtain a basic clock signal; the frequency of the basic clock signal is adjusted by the high and low bits of the parallel data, and the clock calibration unit adjusts the number of the high and low bits of the parallel data according to the clock frequency difference and the frequency of parallel-serial conversion of the serialization unit; a counting unit for generating a time stamp according to the base clock signal;
the network module obtains the time stamp of the message after the message is separated according to the message type in the PTP message, the main control module calculates the time difference and the network delay according to the time stamp obtained by the network module, and then obtains the clock frequency difference according to a preset rule.
2. The FPGA module according to claim 1, wherein the PTP messages include a Sync message, a delay_req message, and a delay_resq message, and the FPGA module is applied to a master node and a slave node, and a time of interaction of a group of PTP messages by the master node and the slave node is a synchronization period, and one synchronization period corresponds to a time difference, a network Delay, and a synchronization time point, and the synchronization time point is a time point in the synchronization period.
3. The FPGA module of claim 2, wherein for any synchronization period, obtaining the corresponding time difference and network delay comprises:
the method comprises the steps that a master node sends a Sync message, a network module of the master node obtains a first time stamp of the Sync message after the Sync message is separated from the network module, and the obtained first time stamp is packaged in the Sync message;
the slave node receives the Sync message, and a network module of the slave node acquires a second timestamp of the Sync message after the Sync message is separated from the network module; the master control module of the slave node receives the Sync message and the second timestamp from the network module and analyzes the first timestamp from the Sync message;
the slave node sends the delay_req message, and a network module of the slave node obtains a third timestamp of the delay_req message after the delay_req message is separated and sends the third timestamp to a main control module of the slave node;
the master node receives the delay_req message, and a network module of the master node obtains a fourth timestamp of the delay_req message after the delay_req message is isolated;
the master node sends the delay_resq message, and a network module of the master node encapsulates the fourth timestamp in the delay_resq message;
the slave node receives the delay_resq message, a network module of the slave node receives the delay_resq message and sends the delay_resq message to the master control module, and the master control module analyzes the fourth timestamp from the delay_resq message;
and the master control module of the slave node calculates the time difference and the network delay between the master node and the slave node according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp.
4. The FPGA module of claim 3, wherein the master control module of the slave node predicts the time when the Sync message is sent by the master node, and controls the slave node to send the delay_req message according to the predicted time.
5. The FPGA module of claim 4, wherein the predetermined rule is: setting a calibration period, and acquiring a clock frequency difference once in each calibration period by the main control module.
6. The FPGA module of claim 5, wherein the master control module obtaining the clock frequency difference for each calibration cycle comprises:
setting a plurality of statistical periods in the calibration period, wherein the statistical periods comprise a plurality of synchronous periods; taking the time difference corresponding to the synchronization period with the minimum network delay in each statistical period as the preferred time difference in the statistical period;
and carrying out linear fitting on the optimal time difference of each statistical period and the corresponding synchronous time point to obtain the clock frequency difference in the calibration period.
7. The FPGA module of claim 5, wherein the master control module obtaining the clock frequency difference for each calibration cycle comprises:
the calibration period comprises a number of synchronization periods;
and selecting any two synchronous periods, and calculating the clock frequency difference according to the time difference corresponding to the selected synchronous periods and the synchronous time point.
8. The FPGA module of claim 6 or 7, wherein for any synchronization period, its corresponding synchronization time point is its first timestamp.
9. An audio conversion device, characterized in that the audio conversion device comprises an FPGA module as claimed in any one of claims 1 to 8.
10. The audio conversion device of claim 9, further comprising an analog-to-digital conversion module and a digital-to-analog conversion module, the analog-to-digital conversion module being coupled to the analog audio signal to convert the analog audio signal to a digital audio signal; the digital-to-analog conversion module converts the digital audio signal into an analog audio signal and outputs the analog audio signal; the FPGA module further comprises a coding and decoding module, the coding and decoding module realizes conversion between digital audio signals and IP audio streams, and the IP audio streams refer to the digital audio signals which can be transmitted in a network; and a network module in the FPGA module sends and receives the IP audio stream according to a network protocol.
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