CN114780469A - Clock frequency calibration device, data chip and clock frequency calibration method - Google Patents
Clock frequency calibration device, data chip and clock frequency calibration method Download PDFInfo
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- CN114780469A CN114780469A CN202210720656.5A CN202210720656A CN114780469A CN 114780469 A CN114780469 A CN 114780469A CN 202210720656 A CN202210720656 A CN 202210720656A CN 114780469 A CN114780469 A CN 114780469A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Abstract
The application provides a clock frequency calibration device, a data chip and a clock frequency calibration method, and belongs to the technical field of chip calibration. The device comprises: the device comprises an identification module, a calculation module, a clock oscillation module and a clock tree; the identification module is used for acquiring the mark data sent by the serializer; the calculation module is used for acquiring the data packet transmitted by the serializer and calculating the time length of the data packet after the identification module acquires the mark data, and performing mean value calculation and deviation processing according to the time length of the data packet to obtain an assignment result; and the clock oscillation module is used for receiving the assignment result sent by the calculation module and calibrating the clock frequency of the clock tree based on the assignment result. The method and the device can reduce the complexity of a circuit structure in the chip and reduce the working cost of the circuit.
Description
Technical Field
The application relates to the technical field of chip calibration, in particular to a clock frequency calibration device, a data chip and a clock frequency calibration method.
Background
In a chip, in order to guarantee the rate of information transmission and avoid delay, the clock frequency of a clock in a circuit needs to be calibrated.
In the prior art, a PLL (Phase Locked Loop) circuit and a CDR (Clock and Data Recovery) circuit are usually required to be disposed in a chip to achieve Clock frequency calibration.
However, the two circuits, especially the CDR circuit, are usually complex in structure, cannot be disposed inside the chip, and need to be disposed outside the chip, which results in more space required for implementing the clock frequency calibration by using the two circuits, and is not suitable for the chip with limited space, and also results in higher operation cost due to the complexity of the circuit itself.
Disclosure of Invention
The present application provides a clock frequency calibration apparatus, a data chip, and a clock frequency calibration method, which can reduce the complexity of a circuit structure in a chip and reduce the working cost of a circuit.
The embodiment of the application is realized as follows:
in one aspect of the embodiments of the present application, a clock frequency calibration apparatus is provided, including: the device comprises an identification module, a calculation module, a clock oscillation module and a clock tree; the calculation module is respectively connected with the identification module and the clock oscillation module, and the identification module is also in communication connection with the serial deserializer; the clock tree is respectively connected with the identification module, the calculation module, the clock oscillation module and the serial deserializer;
the identification module is used for acquiring the mark data sent by the serializer;
the calculation module is used for acquiring the data packet transmitted by the serializer and calculating the time length of the data packet after the identification module acquires the mark data, and performing mean value calculation and deviation processing according to the time length of the data packet to obtain an assignment result;
and the clock oscillation module is used for receiving the assignment result sent by the calculation module and calibrating the clock frequency of the clock tree based on the assignment result.
Optionally, the calculation module comprises: the device comprises a main body counting unit, a mean value calculating unit and a balancing control unit; the main counting unit is connected with the identification module, the mean value calculating unit is respectively connected with the balancing control unit and the main counting unit, and the balancing control unit is connected with the clock oscillation module;
the main body counting unit is used for acquiring a data packet transmitted by the serializer and calculating the time length of the data packet after the identification module acquires the mark data, and sending the time length of the data packet to the average value calculating unit;
the average value calculation unit is used for carrying out average value calculation based on the duration of the data packet and sending the result of the average value calculation to the balancing control unit;
and the balancing control unit is used for performing deviation calculation according to the result of the mean calculation and the length of the data packet configured in advance, determining an assignment result based on a preset deviation adjustment strategy, and sending the assignment result to the clock oscillation module.
Optionally, the flag data includes: a start mark and an end mark;
the main counting unit is specifically configured to start counting after the identification module acquires the start flag, end counting after the identification module acquires the end flag, and determine a duration of the data packet based on a counting result.
Optionally, the working state of the main body counting unit includes: a disabled identification state and an idle identification state;
when the data bus of the main counting unit carries out data transmission, the main counting unit is in a recognition forbidden state;
when the data bus of the main body counting unit does not carry out data transmission, the main body counting unit is in an idle identification state.
Alternatively, when the body counting unit enters the recognition disabled state, the body counting unit instructs the recognition module to stop recognizing the flag data.
Alternatively, when the body counting unit enters the idle recognition state, the body counting unit instructs the recognition module recognition flag data.
Optionally, the clock oscillation module is a clock oscillator; the clock oscillator is specifically used for receiving the assignment result sent by the calculation module and generating a new working clock based on the assignment result.
In another aspect of the embodiments of the present application, a data chip is provided, which includes: the identification module in the clock frequency calibration device is in communication connection with the serializer, and the identification module, the calculation module and the clock oscillation module in the clock frequency calibration device are connected with the serializer through a clock tree.
Optionally, the serializer is any one of: a single-channel serializer deserializer of a synchronous signal, a multi-channel serializer deserializer, or a single-channel serializer deserializer without clock synchronous signal interaction.
Optionally, the serdes comprises a serial to parallel circuit and a parallel to serial circuit, both of which are connected to the clock tree, and the serial to parallel circuit is further configured to send the identification flag to the clock frequency calibration apparatus.
In another aspect of the embodiments of the present application, a clock frequency calibration method is provided, where the method is applied to the clock frequency calibration apparatus, and the method includes:
acquiring mark data sent by a serial deserializer through an identification module;
after the identification module acquires the mark data, the calculation module acquires a data packet transmitted by the serializer and calculates the duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result;
and receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result.
Optionally, after the identification module obtains the flag data, the calculation module obtains a data packet transmitted by the serdes and calculates a duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result, where the method includes:
after the identification module acquires the mark data through the main counting unit, acquiring a data packet transmitted by the serializer and calculating the duration of the data packet, and sending the duration of the data packet to the mean value calculating unit;
carrying out mean value calculation based on the duration of the data packet through a mean value calculation unit, and sending the result of the mean value calculation to a balancing control unit;
and performing deviation calculation according to the result of the mean value calculation and the length of the data packet configured in advance through the balancing control unit, determining an assignment result based on a preset deviation adjustment strategy, and sending the assignment result to the clock oscillation module.
Optionally, the flag data includes: a start flag, an end flag; after the identification module acquires the mark data through the main body counting unit, acquiring a data packet transmitted by the serializer and calculating the time length of the data packet, wherein the method comprises the following steps:
counting is started after the identification module acquires the start mark through the main counting unit, counting is finished after the identification module acquires the end mark, and the duration of the data packet is determined based on the counting result.
Optionally, the clock oscillation module is a clock oscillator; receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result, wherein the calibration method comprises the following steps: and receiving the assignment result sent by the calculation module through a clock oscillator and generating a new working clock based on the assignment result.
The beneficial effects of the embodiment of the application include:
in the clock frequency calibration device, the data chip and the clock frequency calibration method provided by the embodiment of the application, the identification data sent by the serializer can be acquired through the identification module; after the identification module acquires the mark data, the calculation module acquires a data packet transmitted by the serializer and calculates the duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result; and receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result. The complexity of the whole chip can be reduced and the working cost of the circuit during working can be reduced in the process of realizing clock frequency calibration based on the identification module, the calculation module and the clock oscillation module.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a clock frequency calibration apparatus according to an embodiment of the present disclosure;
fig. 2 is another schematic structural diagram of a clock frequency calibration apparatus according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a data chip according to an embodiment of the present disclosure;
fig. 4 is another schematic structural diagram of a data chip according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of a clock frequency calibration method according to an embodiment of the present disclosure.
An icon: 100-clock frequency calibration means; 110-an identification module; 120-a calculation module; 121-a body counting unit; 122-mean calculation unit; 123-a trim control unit; 130-a clock oscillation module; 200-a serializer deserializer; 210-serial to parallel circuit; 220-parallel to serial circuit; 300-clock tree.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
The method can be used for calibrating the clock frequency of the serializer/deserializer, and in the prior art, when the clock frequency of the serializer/deserializer is calibrated, the clock frequency is calibrated by a PLL circuit and a CDR circuit additionally arranged in a chip (or outside the chip).
The prior art serdes can be connected to two devices in a master-slave relationship, for example: taking the main earphone and the auxiliary earphone as an example, the current conventional audio transmission code rates 44.1Khz, 48Khz, 96Khz, etc. have far speed differences compared with optical fiber communication or USB (Universal Serial Bus) protocol communication, etc. For the design of a chip where the serial deserializer is located, the CDR circuit design is adopted for interface design processing, the design complexity is improved, and meanwhile, the design cost and the production cost can be obviously improved through the design of the method.
Specifically, the main operating principle of the CDR circuit is to track the edge jump of the data signal line, adjust its own PLL (which may be an analog PLL or a digital PLL) in time, and finally achieve the calibration of the clock output of its own PLL and the clock frequency in the signal line transmission.
However, the CDR circuit design is adopted to perform interface design processing, which increases the design complexity, and meanwhile, the design of this method will also significantly increase the design cost and the production cost.
The following specifically explains the specific structural connection relationship of the clock frequency calibration apparatus in the embodiments of the present application and the corresponding operating principle thereof.
Fig. 1 is a schematic structural diagram of a clock frequency calibration device according to an embodiment of the present application, and referring to fig. 1, the clock frequency calibration device includes: the identification module 110, the calculation module 120, the clock oscillation module 130 and the clock tree 300; the calculation module 120 is respectively connected with the identification module 110 and the clock oscillation module 130, and the identification module 110 is further connected with the serializer/deserializer 200 in a communication way; the clock tree 300 is connected to the identification module 110, the calculation module 120, the clock oscillation module 130, and the serializer 200, respectively.
The identification module 110 may be a signal identification receiving circuit, and may acquire the flag data sent by the serializer 200 during operation. The flag data may be a set of easily recognizable data sequences, and may be a transition edge of a data signal line.
The calculation module 120 may be an integrated circuit having a calculation processing function, and after the identification module 110 acquires the flag data, the calculation module 120 may acquire the data packet transmitted by the serdes 200 and calculate the duration of the data packet, and perform an average calculation and a deviation processing according to the duration of the data packet to obtain an assignment result. The calculating module 120 may specifically perform operations such as counting calculation, mean calculation, deviation calculation, and assignment calculation, which are not limited specifically herein, and the calculating module may include a plurality of calculating units to respectively implement different calculating operations, or may also be an integral calculating unit to sequentially execute each calculating operation, which is not limited by a specific processing manner herein.
The clock oscillation module 130 may be a functional device that generates a clock signal, and may receive the assignment result sent by the calculation module 120 and calibrate the clock frequency of the clock tree 300 based on the assignment result.
The serializer/deserializer 200 may be an external system or an external circuit with a deserializing function, but is not limited herein, and the serializer/deserializer 200 may be a point-to-point and time division multiplexing communication technology, and the signals transmitted by the serializer/deserializer are in a differential mode, so that the high interference and noise resistance of the system is improved.
The clock tree 300 may be a clock tree connecting the entire clock frequency calibration device and the serializer 200, with clock synchronization of device modules under the same clock tree.
Alternatively, the data packet may specifically be a communication data packet generated according to actual communication contents in a communication process; the data packet can be sent circularly according to a fixed period in the transmission process; during each data packet transmission, an idle period may be set.
In the clock frequency calibration device provided by the embodiment of the application, the identification data sent by the serializer can be acquired through the identification module; after the identification module acquires the mark data, the calculation module acquires a data packet transmitted by the serializer and calculates the duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result; and receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result. The complexity of the whole chip can be reduced and the working cost of the circuit in working can be reduced in the process of realizing clock frequency calibration based on the identification module, the calculation module and the clock oscillation module.
The following specifically explains a specific structure of a calculation block of the clock frequency calibration device according to the embodiment of the present application.
Fig. 2 is another structural schematic diagram of the clock frequency calibration apparatus according to an embodiment of the present disclosure, please refer to fig. 2, in which the calculating module 120 includes: a subject counting unit 121, an average value calculating unit 122, and a trim control unit 123; the main body counting unit 121 is connected to the identification module 110, the average calculating unit 122 is respectively connected to the balancing control unit 123 and the main body counting unit 121, and the balancing control unit 123 is connected to the clock oscillation module 130.
Accordingly, the clock tree 300 may be connected to the subject counting unit 121, the average calculation unit 122, and the trim control unit 123, respectively.
Alternatively, the body counting unit 121 may be an integrated circuit having a counting function. After the identification module 110 acquires the flag data, the main body counting unit 121 may acquire the data packet transmitted by the serializer 200 and calculate the duration of the data packet, and send the duration of the data packet to the average value calculating unit 122.
Alternatively, the averaging unit 122 may be an integrated circuit having an averaging function. The averaging unit 122 may perform averaging based on the time length of the packet and send the result of the averaging to the trim control unit 123.
Alternatively, the trim control unit 123 may be an integrated circuit with offset calculation and assignment functions. The balancing control unit 123 may perform deviation calculation according to the result of the mean calculation and the preconfigured length of the data packet, determine an assignment result based on a preset deviation adjustment policy, and send the assignment result to the clock oscillation module 130.
The overall workflow of the calculation module 120 is as follows:
the main body counting unit 121 may start counting after receiving an instruction sent by the identification module 110 (specifically, after the identification module 110 acquires the flag data), and the content of counting is specifically the duration of the data packet transmitted by the serializer 200, and sends the result of counting to the mean value calculating unit 122 after the counting is completed.
After receiving the counting result, the average calculating unit 122 may perform an average calculation of the packet durations to obtain an average duration of each packet during transmission. The specific calculation process may be to configure the number of data packets in advance, perform average calculation on the durations of the data packets after receiving the number of data packets, obtain an average duration of the data packets during transmission, and send the average duration to the balancing control unit 123. For example: if the configured number is two data packets, the average value of the packet lengths of the two data packets may be calculated after the packet lengths of the two data packets are obtained.
The trim control unit 123, after receiving the average duration of the data packets, may compare the duration of the data packets based on the pre-configured duration to obtain an offset value of the current clock frequency from the expected transmission frequency, for example: it may be to calculate the difference between the average duration of received packets and the duration of preconfigured packets. And may determine an assignment result corresponding to the current offset according to a pre-configured mapping relationship (a mapping relationship between the offset value and the assignment result), and may send the assignment result to the clock oscillation module 130.
In the clock frequency calibration device provided by the embodiment of the application, after the identification module acquires the flag data, the main counting unit acquires the data packet transmitted by the serializer and calculates the duration of the data packet, and sends the duration of the data packet to the mean value calculating unit; carrying out mean value calculation based on the duration of the data packet through a mean value calculation unit, and sending the result of the mean value calculation to a balancing control unit; and performing deviation calculation according to the result of the mean value calculation and the length of the data packet configured in advance through the balancing control unit, determining an assignment result based on a preset deviation adjustment strategy, and sending the assignment result to the clock oscillation module. When the calculation is performed based on the main counting unit, the mean value calculating unit and the balancing control unit, the required calculation cost is low, and the required calculation amount can be realized with low cost, so that the final clock oscillation assignment result is obtained, that is, the cost required by the calculation can be reduced.
Optionally, the flag data includes: a start flag, an end flag; the body counting unit 121 is specifically configured to start counting after the identification module 110 obtains the start flag, end counting after the identification module obtains the end flag, and determine a duration of the data packet based on a counting result.
After the identification module 110 obtains the start flag, it may send a first flag enable to the main counting unit 121, so that the main counting unit 121 starts to obtain the duration of the data packet, that is, starts to count; after the identification module 110 obtains the end flag, it may send a second flag enable to the body counting unit 121, so that the body counting unit 121 ends the duration of obtaining the data packet.
Alternatively, the operation state of the body counting unit 121 includes: a disabled identification state and an idle identification state; when the data bus of the main body counting unit 121 performs data transmission, the main body counting unit 121 is in a recognition disabled state; when the data bus of the body counting unit 121 does not perform data transmission, the body counting unit 121 is in an idle recognition state.
The transmission condition of the data bus in the main counting unit 121 can be obtained in real time, and when there is data transmission in the data bus, it can be determined that the main counting unit 121 is in the identification prohibition state; accordingly, when there is no data transmission in the data bus, it may be determined that the body counting unit 121 is in the idle recognition state.
In the recognition disabled state, the main body counting unit 121 cannot perform counting; in the idle recognition state, the body counting unit 121 may perform counting.
Alternatively, when the body counting unit 121 enters the recognition disabled state, the body counting unit 121 instructs the recognition module 110 to stop recognizing the flag data. When the body counting unit 121 enters the idle recognition state, the body counting unit 121 instructs the recognition module 110 to recognize the flag data.
It should be noted that, when the data bus is transmitting data, the flag identification may be triggered by mistake, and to avoid this, the flag identification may be prohibited, and the main body counting unit 121 instructs the identification module 110 to stop identifying the flag data; in contrast, the recognition module 110 may be instructed to restore the recognition flag data when the body counting unit 121 enters the idle recognition state.
Optionally, the clock oscillation module 130 is a clock oscillator; the clock oscillator is specifically used for receiving the assignment result sent by the calculation module and generating a new working clock based on the assignment result.
It should be noted that the clock oscillator may generate, according to the assignment result, a clock signal matched with the assignment result to replace the existing clock signal, thereby implementing the calibration of the clock frequency. The clock oscillator may particularly be a clock oscillator built into a chip.
Optionally, the clock oscillation module 130 may specifically have a function of a "TRIM" function, where the "TRIM" function may specifically be used to remove blank characters or other predefined characters on two sides of the target character string, and the step of the "TRIM" function may be determined according to the actual precision of the whole device during the operation of the clock oscillation module. In particular, the "TRIM" function may be stepped less than the required accuracy of the entire device.
For example: the central value of the clock frequency of the clock oscillation module 130 may be 8 times or more of that of the data bus in the device, and the larger the central value of the clock frequency is, the more accurate the generated new working clock is.
The clock oscillator is only one implementation manner, and in the process of actual implementation, all circuits or devices that can generate corresponding clock signals may be used as the clock oscillation module 130, which is not limited in this respect.
The connection relationship of the data chip and the corresponding working principle provided in the embodiment of the present application are specifically explained below.
Fig. 3 is a schematic structural diagram of a data chip according to an embodiment of the present disclosure, and referring to fig. 3, the data chip includes: the identification module 110 in the clock frequency calibration device 100 is communicatively connected to the serializer 200, and the identification module 110, the calculation module 120 and the clock oscillation module 130 in the clock frequency calibration device 100 are connected to the serializer 200 through the clock tree 300.
In the data chip provided by the embodiment of the application, the identification data sent by the serializer can be acquired through the identification module; after the identification module acquires the mark data, the calculation module acquires a data packet transmitted by the serializer and calculates the duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result; and receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result. The identification module, the calculation module and the clock oscillation module are all circuit structures with small scales, so that the complexity of the whole chip can be reduced in the process of realizing clock frequency calibration, and the working cost of the circuit in working can be reduced.
Optionally, the serializer is any one of: a single-channel serializer deserializer of a synchronous signal, a multi-channel serializer deserializer, or a single-channel serializer deserializer without clock synchronous signal interaction.
The serializer/deserializer of the single channel of the synchronous signal can be only one signal transmission channel, and clock data is transmitted simultaneously along with the single channel; the multi-channel serializer/deserializer may be a serializer/deserializer having a plurality of communication transmission channels, wherein a clock may be transmitted along with data; the single-channel serializer/deserializer without clock synchronization signal interaction can be an 8B/10B serializer, and single-channel signals are transmitted, but clock signals are not sent synchronously with data and are transmitted in other modes.
The specific structure of the serializer and its corresponding operating principle will be explained in detail below.
Referring to fig. 4, a serializer 200 includes a serial-to-parallel circuit 210 and a parallel-to-serial circuit 220, the serial-to-parallel circuit 210 and the parallel-to-serial circuit 220 are both connected to a clock tree 300, and the serial-to-parallel circuit 210 is further configured to send an identification flag to the clock frequency calibration apparatus 100.
The structure of the serializer 200 shown in fig. 4 may be specifically the above-mentioned single-channel serializer (8B/10B SerDes) without clock synchronization signal interaction, and this type of deserializer may be applied to a high-speed communication system and a part of low-speed system applications, and because of the requirements of high interference resistance and system clock synchronization of the master and slave devices, the 8B/10B SerDes scheme is also adopted for system communication design, such as audio data transmission.
The devices connected to the serial-to-parallel circuit 210 and the parallel-to-serial circuit 220 are usually disposed in two different devices, and may specifically be devices having a master-slave relationship, for example: the serial-to-parallel circuit 210 can be connected with a circuit of a master device, the parallel-to-serial circuit 220 can be connected with a circuit of a slave device, clock synchronization between the master device and the slave device can be realized through clock calibration of the clock frequency calibration device 100, and the occurrence of conditions such as delay is avoided.
Fig. 5 is a flowchart illustrating a clock frequency calibration method according to an embodiment of the present application, please refer to fig. 5, in which the method includes:
s510: and acquiring the mark data sent by the serializer through the identification module.
S520: after the identification module acquires the mark data, the calculation module acquires a data packet transmitted by the serializer and calculates the duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result.
S530: and receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result.
Optionally, the main body of the method may be the clock frequency calibration apparatus, and the specific implementation process has been explained in the foregoing, which is not described herein again.
In the clock frequency calibration method provided by the embodiment of the application, the identification data sent by the serializer can be acquired through the identification module; after the identification module acquires the mark data, the calculation module acquires a data packet transmitted by the serializer and calculates the duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result; and receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result. The complexity of the whole chip can be reduced and the working cost of the circuit in working can be reduced in the process of realizing the clock frequency calibration based on the identification module, the calculation module and the clock oscillation module.
Optionally, after the identification module obtains the flag data, the calculation module obtains a data packet transmitted by the serializer and calculates a duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result, including:
after the identification module acquires the mark data through the main counting unit, acquiring a data packet transmitted by the serializer and calculating the duration of the data packet, and sending the duration of the data packet to the mean value calculating unit;
carrying out mean value calculation based on the duration of the data packet through a mean value calculation unit, and sending the result of the mean value calculation to a balancing control unit;
and performing deviation calculation according to the result of the mean value calculation and the length of the data packet configured in advance through the balancing control unit, determining an assignment result based on a preset deviation adjustment strategy, and sending the assignment result to the clock oscillation module.
Optionally, the flag data includes: a start mark and an end mark; after the identification module acquires the mark data through the main body counting unit, acquiring a data packet transmitted by the serializer and calculating the time length of the data packet, wherein the method comprises the following steps:
counting is started after the identification module acquires the start mark through the main counting unit, counting is finished after the identification module acquires the end mark, and the duration of the data packet is determined based on the counting result.
Optionally, the clock oscillation module is a clock oscillator; receiving the assignment result sent by the calculation module through the clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result, wherein the calibration method comprises the following steps: and receiving the assignment result sent by the calculation module through a clock oscillator and generating a new working clock based on the assignment result.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall cover the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (11)
1. A clock frequency calibration device, comprising: the device comprises an identification module, a calculation module, a clock oscillation module and a clock tree; the computing module is respectively connected with the identification module and the clock oscillation module, and the identification module is also in communication connection with a serial deserializer; the clock tree is respectively connected with the identification module, the calculation module, the clock oscillation module and the serial deserializer;
the identification module is used for acquiring the mark data sent by the deserializer;
the calculation module is used for acquiring the data packet transmitted by the deserializer and calculating the duration of the data packet after the identification module acquires the mark data, and performing mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result;
and the clock oscillation module is used for receiving the assignment result sent by the calculation module and calibrating the clock frequency of the clock tree based on the assignment result.
2. The clock frequency calibration device of claim 1, wherein the calculation module comprises: the device comprises a main body counting unit, a mean value calculating unit and a balancing control unit; the main counting unit is connected with the identification module, the average value calculating unit is respectively connected with the balancing control unit and the main counting unit, and the balancing control unit is connected with the clock oscillation module;
the main body counting unit is used for acquiring the data packet transmitted by the deserializer and calculating the time length of the data packet after the identification module acquires the mark data, and sending the time length of the data packet to the average value calculating unit;
the average value calculation unit is used for performing average value calculation based on the duration of the data packet and sending the result of the average value calculation to the balancing control unit;
and the balancing control unit is used for performing deviation calculation according to the result of the mean value calculation and the length of a data packet configured in advance, determining an assignment result based on a preset deviation adjustment strategy, and sending the assignment result to the clock oscillation module.
3. The clock frequency calibration apparatus of claim 2, wherein the flag data comprises: a start mark and an end mark;
the main counting unit is specifically configured to start counting after the identification module acquires the start flag, end counting after the identification module acquires the end flag, and determine the duration of the data packet based on a counting result.
4. The clock frequency calibration device of claim 2, wherein the operational state of the body count unit comprises: a disabled identification state and an idle identification state;
when the data bus of the main counting unit carries out data transmission, the main counting unit is in the identification prohibition state;
when the data bus of the main body counting unit does not transmit data, the main body counting unit is in the idle identification state.
5. The clock frequency calibration apparatus of claim 4, wherein the body counting unit instructs the identification module to stop identifying the flag data when the body counting unit enters the identification disabled state.
6. The clock frequency calibration apparatus of claim 4, wherein the body count unit instructs the identification module to identify the flag data when the body count unit enters the idle identification state.
7. The clock frequency calibration device of claim 1, wherein the clock oscillation module is a clock oscillator; the clock oscillator is specifically configured to receive an assignment result sent by the calculation module and generate a new working clock based on the assignment result.
8. A data chip, comprising: the clock frequency calibration device according to any one of claims 1 to 7, and a serializer, wherein the identification module in the clock frequency calibration device is communicatively connected to the serializer, and wherein the identification module, the calculation module and the clock oscillation module in the clock frequency calibration device are connected to the serializer through a clock tree.
9. The data chip of claim 8, wherein the serdes is any one of: a single-channel deserializer of the synchronization signal, a multi-channel deserializer, or a single-channel deserializer without clock synchronization signal interaction.
10. The data chip of claim 8, wherein the serializer comprises a serial-to-parallel circuit and a parallel-to-serial circuit, both connected to the clock tree, the serial-to-parallel circuit further configured to send an identification flag to the clock frequency calibration device.
11. A clock frequency calibration method applied to the clock frequency calibration apparatus according to any one of claims 1 to 7, the method comprising:
acquiring the mark data sent by the serializer through the identification module;
after the identification module acquires the mark data, a calculation module acquires a data packet transmitted by the serializer and calculates the duration of the data packet, and performs mean calculation and deviation processing according to the duration of the data packet to obtain an assignment result;
and receiving the assignment result sent by the calculation module through a clock oscillation module and calibrating the clock frequency of the clock tree based on the assignment result.
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