CN108011705B - Method and device for synchronizing channel clocks - Google Patents

Method and device for synchronizing channel clocks Download PDF

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Publication number
CN108011705B
CN108011705B CN201610930569.7A CN201610930569A CN108011705B CN 108011705 B CN108011705 B CN 108011705B CN 201610930569 A CN201610930569 A CN 201610930569A CN 108011705 B CN108011705 B CN 108011705B
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signal
clock
service
serial
analog
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CN108011705A (en
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李霞
游俊
何力
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ZTE Corp
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ZTE Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0087Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0091Transmitter details
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0018Arrangements at the transmitter end
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0024Carrier regulation at the receiver end

Abstract

The application provides a method and a device for synchronizing channel clocks, wherein the method comprises the following steps: respectively obtaining a clock signal and a service signal, and respectively processing the clock signal and the service signal by utilizing two paths of paths; and modulating the clock signal and the service signal into a path of signal for transmission. The method combines clock synchronization and other rate services together in a modulation mode, and a clock signal and other service signals are processed separately and transmitted by one line on the line.

Description

Method and device for synchronizing channel clocks
Technical Field
The invention relates to the field of clock synchronization, in particular to a method and a device for synchronizing channel clocks.
Background
With the continuous development of communication technology, higher requirements are put on clock synchronization performance, wherein a clock comprises frequency and/or time. For example, recently, a positioning service is provided by a base station, the time precision requirement is about ± 200ns, and the relative time precision between adjacent base stations is required to be about ± 500ns in a Coordinated Multiple point-point Processing (Coordinated multipoint transmission Joint Processing) key technology CoMP-JP of LTE-a (Long Term Evolution-Advanced); future 5G (5 th-Generation, fifth Generation mobile communication technology) systems may require ultra-high precision time synchronization requirements on the order of hundreds of ns; for another example, a quantum communication technology in a longer period needs a time measurement technology with extremely high precision to reduce the bit error rate of a quantum communication system and improve the bit rate of the quantum communication system, and may need time synchronization precision within hundred ns. At present, high-precision time synchronization realized based on a 1588v2 technology can only meet us-magnitude time synchronization requirements, but cannot meet the hundreds of ns or even higher-precision time synchronization requirements.
At present, research on high-precision clock synchronization of a GE (gigabit Ethernet) optical interface has made a certain progress, and theoretically, the synchronization precision of ns and even sub-ns can be achieved. The trans-driver implementation and recovery clock frequency of the higher-rate interface have certain difference with the GE interface, and the scheme of the GE optical interface cannot be directly used, so that a high-precision clock synchronization implementation scheme which is not influenced by the port rate is needed.
Disclosure of Invention
The invention provides a method and a device for synchronizing a channel clock, which can ensure that the realization of high-precision clock synchronization is not influenced by the port rate.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention is as follows:
a method of lane clock synchronization, comprising:
respectively obtaining a clock signal and a service signal, and respectively processing the clock signal and the service signal by utilizing two paths of paths;
and modulating the clock signal and the service signal into a path of signal for transmission.
Preferably, the obtaining a clock signal and a service signal respectively, and processing the clock signal and the service signal respectively by using two paths includes:
carrying out error correction and/or equalization processing on the obtained clock signal;
the obtained traffic signal is encoded.
Preferably, acquiring the clock signal comprises one of:
acquiring a clock signal generated by a timestamp signal generating module;
acquiring a clock signal sent by a master-slave synchronous system;
the clock signal is obtained in predefined encapsulated frames.
Preferably, modulating the clock signal and the service signal into a single signal for transmission includes:
converting the clock signal after error correction and/or equalization into a clock serial signal;
converting the coded service signal into a service serial signal;
and modulating the clock serial signal and the service serial signal into a path of signal for transmission.
Preferably, modulating the clock signal and the service signal into a single signal for transmission includes:
converting the clock signal and the service signal into a clock analog signal and a service analog signal;
modulating the clock analog signal and the service analog signal into a path of analog signal;
converting the analog signal into a digital signal;
and converting the digital signal into an optical signal for transmission.
Preferably, modulating the clock analog signal and the service analog signal into a single analog signal includes:
the modulated signal s (t) is represented as:
wherein n (t) is a clock analog signal, m (t) is a service analog signal, coswt is a carrier signal, and K is a proportionality coefficient.
The embodiment of the invention also provides a method for synchronizing the channel clock, which comprises the following steps:
restoring the obtained received signals into clock signals and service signals, and respectively processing the clock signals and the service signals by utilizing two paths of paths;
and carrying out clock synchronization on the obtained clock signal.
Preferably, recovering the obtained received signal into a clock signal and a service signal, and processing the clock signal and the service signal respectively by using two paths includes:
demodulating the obtained optical line signal to recover a clock signal and a service signal;
carrying out byte alignment and/or equalization decoding and/or error correction decoding on the clock signal to obtain a timestamp signal;
the traffic signal is decoded.
Preferably, recovering the obtained received signal into a clock signal and a service signal, and processing the clock signal and the service signal respectively by using two paths includes:
demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal;
converting the clock serial signal into a clock parallel signal; and converting the service serial signal into a service parallel signal.
Preferably, the clock synchronization of the obtained clock signal comprises:
and performing clock synchronization according to the obtained timestamp signals.
Preferably, the method further comprises at least one of:
performing service packet receiving on the service parallel signal,
sending the timestamp signals after clock synchronization to a master-slave synchronization system;
and de-encapsulating the timestamp signals after clock synchronization to obtain timestamp information in a predefined frame.
Preferably, demodulating the obtained optical line signal to recover the clock serial signal and the service serial signal includes:
converting the obtained optical line signal into an electronic circuit signal;
converting the electronic circuit signal into an electronic circuit analog signal;
demodulating the electronic circuit analog signal to recover a clock analog signal and a service analog signal;
and converting the clock analog signal and the service analog signal into a clock serial signal and a service serial signal.
Preferably, decapsulating the clock-synchronized timestamp signals to obtain timestamp information in a predefined frame further includes:
and adjusting the time deviation of the time stamp information of the predefined frame obtained by de-encapsulation according to the local time stamp information of the predefined frame.
Preferably, the time offset adjusting the time stamp information of the predefined frame obtained by decapsulation according to the local time stamp information of the predefined frame includes:
the time offset is expressed as:
offset=T2-T1-TC1-TC2-delay
wherein, T1 is local timestamp information of a fixed frame, TC1 is a time delay from a timestamp recording position to a position where a conversion is made into an optical signal for transmission, T2 is timestamp information of the fixed frame obtained by decapsulation, and TC2 is a time delay from a position where an optical line signal is obtained to a timestamp recording position;
and adjusting the time according to the time offset.
The embodiment of the present invention further provides a device for synchronizing a channel clock, including:
the first processing module is arranged to respectively obtain a clock signal and a service signal and respectively process the clock signal and the service signal by utilizing two paths of paths;
and the transmission module is configured to modulate the clock signal and the service signal into a path of signal for transmission.
Preferably, the obtaining, by the first processing module, the clock signal and the service signal, and processing, by using two paths, the clock signal and the service signal respectively means:
carrying out error correction and/or equalization processing on the obtained clock signal;
the obtained traffic signal is encoded.
Preferably, the acquiring of the clock signal by the first processing module comprises one of:
acquiring a clock signal generated by a timestamp signal generating module;
acquiring a clock signal sent by a master-slave synchronous system;
the clock signal is obtained in predefined encapsulated frames.
Preferably, the step of modulating the clock signal and the service signal into a signal by the transmission module for transmission includes:
converting the clock signal after error correction and/or equalization into a clock serial signal;
converting the coded service signal into a service serial signal;
and modulating the clock serial signal and the service serial signal into a path of signal for transmission.
Preferably, the step of modulating the clock signal and the service signal into a signal by the transmission module for transmission includes:
converting the clock signal and the service signal into a clock analog signal and a service analog signal;
modulating the clock analog signal and the service analog signal into a path of analog signal;
converting the analog signal into a digital signal;
and converting the digital signal into an optical signal for transmission.
Preferably, the modulating, by the transmission module, the clock analog signal and the service analog signal into one analog signal refers to:
the modulated signal s (t) is represented as:
wherein n (t) is a clock analog signal, m (t) is a service analog signal, coswt is a carrier signal, and K is a proportionality coefficient.
The embodiment of the present invention further provides a device for synchronizing a channel clock, including:
the second processing module is used for recovering the obtained received signal into a clock signal and a service signal and respectively processing the clock signal and the service signal by utilizing two paths of paths;
and the synchronization module is used for carrying out clock synchronization on the obtained clock signal.
Preferably, the recovering, by the second processing module, the obtained received signal into a clock signal and a service signal, and respectively processing the clock signal and the service signal by using two paths means:
demodulating the obtained optical line signal to recover a clock signal and a service signal;
carrying out byte alignment and/or equalization decoding and/or error correction decoding on the clock signal to obtain a timestamp signal;
the traffic signal is decoded.
Preferably, the recovering, by the second processing module, the obtained received signal into a clock signal and a service signal, and respectively processing the clock signal and the service signal by using two paths means:
demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal;
converting the clock serial signal into a clock parallel signal; and converting the service serial signal into a service parallel signal.
Preferably, the clock synchronization of the obtained clock signal by the synchronization module includes:
and performing clock synchronization according to the obtained timestamp signals.
Preferably, the apparatus further comprises a third processing module configured to at least one of:
performing service packet receiving on the service parallel signal,
sending the timestamp signals after clock synchronization to a master-slave synchronization system;
and de-encapsulating the timestamp signals after clock synchronization to obtain timestamp information in a predefined frame.
Preferably, the demodulating, by the second processing module, the obtained optical line signal, and recovering the clock serial signal and the service serial signal refer to:
converting the obtained optical line signal into an electronic circuit signal;
converting the electronic circuit signal into an electronic circuit analog signal;
demodulating the line analog signal to recover a clock analog signal and a service analog signal;
and converting the clock analog signal and the service analog signal into a clock serial signal and a service serial signal.
Preferably, the third processing module is further configured to:
and adjusting the time deviation of the time stamp information of the predefined frame obtained by de-encapsulation according to the local time stamp information of the predefined frame.
Preferably, the performing, by the third processing module, a time offset adjustment on the timestamp information of the predefined frame obtained by decapsulation according to the local timestamp information of the predefined frame refers to:
the time offset is expressed as:
offset=T2-T1-TC1-TC2-delay
wherein, T1 is the local timestamp information of the framing, TC1 is the time delay from the timestamp recording position to the position where the optical signal is converted for transmission, T2 is the timestamp information of the framing obtained by decapsulation, and TC2 is the time delay from the position where the optical line signal is obtained to the timestamp recording position;
and adjusting the time according to the time offset.
Compared with the prior art, the invention has the following beneficial effects:
the technical scheme of the invention combines clock synchronization and other rate services together in a modulation mode, and the clock signal and other service signals are processed separately and transmitted by one line on the line.
Drawings
FIG. 1 is a flow chart of a method for lane clock synchronization according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for lane clock synchronization according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a device for lane clock synchronization according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a device for lane clock synchronization according to an embodiment of the present invention;
FIG. 5 is a diagram of an apparatus for lane clock synchronization according to embodiment 1 of the present invention;
FIG. 6 is a diagram of an apparatus for lane clock synchronization according to embodiment 2 of the present invention;
fig. 7 is a schematic diagram of a modem module according to embodiment 1 of the present invention;
FIG. 8 is a diagram of an apparatus for lane clock synchronization according to embodiment 3 of the present invention;
fig. 9 is a schematic structural diagram of a predefined encapsulation frame according to embodiment 3 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description of the embodiments of the present invention with reference to the accompanying drawings is provided, and it should be noted that, in the case of conflict, features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other.
As shown in fig. 1, an embodiment of the present invention provides a method for synchronizing lane clocks, including:
respectively obtaining a clock signal and a service signal, and respectively processing the clock signal and the service signal by utilizing two paths of paths;
and modulating the clock signal and the service signal into a path of signal for transmission.
Preferably, the obtaining a clock signal and a service signal respectively, and processing the clock signal and the service signal respectively by using two paths includes:
carrying out error correction and/or equalization processing on the obtained clock signal;
the obtained traffic signal is encoded.
The clock signal and the service signal obtained in the embodiment of the invention can be in the forms of serial signals, parallel signals, analog signals, digital signals and the like, and the clock signal is required to be subjected to error correction and/or equalization processing to perform coding processing on the service signal.
Preferably, acquiring the clock signal comprises one of:
acquiring a clock signal generated by a timestamp signal generating module;
acquiring a clock signal sent by a master-slave synchronous system;
the clock signal is obtained in predefined encapsulated frames.
The step of modulating the clock signal and the service signal into a path of signal for transmission includes:
performing parallel-serial conversion on the clock signals subjected to error correction and/or equalization processing to convert the clock signals into clock serial signals;
carrying out parallel-serial conversion on the coded service signals, and converting the coded service signals into service serial signals;
and modulating the clock serial signal and the service serial signal into a path of signal for transmission.
Or, modulating the clock signal and the service signal into a signal for transmission includes:
performing digital-to-analog conversion on the clock signal and the service signal to convert the clock signal and the service signal into a clock analog signal and a service analog signal;
modulating the clock analog signal and the service analog signal into a path of analog signal;
performing analog-to-digital conversion on the analog signal to convert the analog signal into a digital signal;
and performing electro-optical conversion on the path of digital signal, and converting the path of digital signal into an optical signal for transmission.
In the embodiment of the invention, one or more of serial-parallel conversion, analog-to-digital conversion and photoelectric conversion are carried out on different forms of the obtained clock signal and the obtained service signal.
The complete process can be expressed in the following form:
s101, carrying out error correction and/or equalization processing on the obtained clock parallel signals, and converting the clock parallel signals into clock serial signals;
s102, coding the service parallel signals obtained in the service packet sending, and converting the service parallel signals into service serial signals;
s103, modulating the clock serial signal and the service serial signal into a path of signal for transmission.
In the embodiment of the invention, S101 and S102 are not limited by time sequence, and are performed simultaneously in most embodiments. In the sending direction, the embodiment of the invention carries out error correction coding, balanced coding and parallel-serial conversion on the clock parallel signals; coding and parallel-serial converting the service parallel signal; and modulating the clock serial signal and the service serial signal, and modulating the signals to one line for transmission.
The step of modulating the clock analog signal and the service analog signal into a path of analog signal comprises:
the modulated signal s (t) is represented as:
wherein n (t) is a clock analog signal, m (t) is a service analog signal, coswt is a carrier signal, and K is a proportionality coefficient.
Because the transmission rates of the clock analog signal and the service analog signal may be different, the clock analog signal and the service analog signal need to be modulated into one path of signal in a frequency modulation and amplitude modulation manner. In the embodiment of the invention, K represents the frequency sensitivity of the modulator, and the size is determined according to actual requirements.
As shown in fig. 2, an embodiment of the present invention further provides a method for synchronizing lane clocks, including:
restoring the obtained received signals into clock signals and service signals, and respectively processing the clock signals and the service signals by utilizing two paths of paths;
and carrying out clock synchronization on the obtained clock signal.
Preferably, recovering the obtained received signal into a clock signal and a service signal, and processing the clock signal and the service signal respectively by using two paths includes:
demodulating the obtained optical line signal to recover a clock signal and a service signal;
carrying out byte alignment and/or equalization decoding and/or error correction decoding on the clock signal to obtain a timestamp signal;
the traffic signal is decoded.
Preferably, recovering the obtained received signal into a clock signal and a service signal, and processing the clock signal and the service signal respectively by using two paths includes:
demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal;
converting the clock serial signal into a clock parallel signal; and converting the service serial signal into a service parallel signal.
Preferably, the clock synchronization of the obtained clock signal comprises:
and performing clock synchronization according to the obtained timestamp signals.
The method further comprises, after the step, at least one of:
performing service packet receiving on the service parallel signal,
sending the timestamp signals after clock synchronization to a master-slave synchronization system;
and de-encapsulating the timestamp signals after clock synchronization to obtain timestamp information in a predefined frame.
Preferably, demodulating the obtained optical line signal to recover the clock serial signal and the service serial signal includes:
performing photoelectric conversion on the obtained optical line signal to convert the optical line signal into an electronic line signal;
performing digital-to-analog conversion on the electronic circuit signal to convert the electronic circuit signal into an electronic circuit analog signal;
demodulating the line analog signal to recover a clock analog signal and a service analog signal;
and performing analog-to-digital conversion on the clock analog signal and the service analog signal to convert the clock analog signal and the service analog signal into a clock serial signal and a service serial signal.
The complete process can be expressed in the following form:
s201, demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal;
s202, the clock serial signal and the service serial signal are converted into a clock parallel signal and a service parallel signal in a serial-parallel mode;
s203, carrying out byte alignment and/or equalization decoding and/or error correction decoding on the clock parallel signals to obtain timestamp signals;
and S204, performing clock synchronization according to the obtained timestamp signals.
In the receiving direction, the embodiment of the invention demodulates the received line signal, recovers two paths of data of a clock signal and a service signal, respectively performs serial-parallel conversion and other processing, wherein the clock signal needs to be subjected to byte alignment, decoding and error correction to obtain a correct timestamp signal, and finally performs clock synchronization.
After the timestamp signals after clock synchronization are de-encapsulated to obtain timestamp information in a predefined frame, the method further comprises the following steps:
and adjusting the time deviation of the time stamp information of the predefined frame obtained by de-encapsulation according to the local time stamp information of the predefined frame.
Wherein the time deviation adjustment of the time stamp information of the predefined frame obtained by decapsulation according to the local time stamp information of the predefined frame comprises:
the time offset is expressed as:
offset=T2-T1-TC1-TC2-delay
wherein, T1 is the local timestamp information of the framing, TC1 is the time delay from the timestamp recording position to the position where the optical signal is converted for transmission, T2 is the timestamp information of the framing obtained by decapsulation, and TC2 is the time delay from the position where the optical line signal is obtained to the timestamp recording position;
and adjusting the time according to the time offset.
As shown in fig. 3, an embodiment of the present invention further provides an apparatus for synchronizing lane clocks, including:
the first processing module is arranged to respectively obtain a clock signal and a service signal and respectively process the clock signal and the service signal by utilizing two paths of paths;
and the transmission module is configured to modulate the clock signal and the service signal into a path of signal for transmission.
The first processing module respectively obtains a clock signal and a service signal, and respectively processes the clock signal and the service signal by using two paths of paths, namely:
carrying out error correction and/or equalization processing on the obtained clock signal;
the obtained traffic signal is encoded.
The first processing module acquiring the clock signal comprises one of the following:
acquiring a clock signal generated by a timestamp signal generating module;
acquiring a clock signal sent by a master-slave synchronous system;
the clock signal is obtained in predefined encapsulated frames.
The transmission module modulates the clock signal and the service signal into a signal for transmission, which means that:
performing parallel-serial conversion on the clock signals subjected to error correction and/or equalization processing to convert the clock signals into clock serial signals;
carrying out parallel-serial conversion on the coded service signals, and converting the coded service signals into service serial signals;
and modulating the clock serial signal and the service serial signal into a path of signal for transmission.
The transmission module modulates the clock signal and the service signal into a signal for transmission, which means that:
performing digital-to-analog conversion on the clock signal and the service signal to convert the clock signal and the service signal into a clock analog signal and a service analog signal;
modulating the clock analog signal and the service analog signal into a path of analog signal;
performing analog-to-digital conversion on the analog signal to convert the analog signal into a digital signal;
and performing electro-optical conversion on the path of digital signal, and converting the path of digital signal into an optical signal for transmission.
The transmission module modulates the clock analog signal and the service analog signal into a path of analog signal, which means that:
the modulated signal s (t) is represented as:
wherein n (t) is a clock analog signal, m (t) is a service analog signal, coswt is a carrier signal, and K is a proportionality coefficient.
As shown in fig. 4, an embodiment of the present invention further provides an apparatus for synchronizing lane clocks, including:
the second processing module is used for recovering the obtained received signal into a clock signal and a service signal and respectively processing the clock signal and the service signal by utilizing two paths of paths;
and the synchronization module is used for carrying out clock synchronization on the obtained clock signal.
The second processing module recovers the obtained received signal into a clock signal and a service signal, and respectively processes the clock signal and the service signal by using two paths of paths, namely:
demodulating the obtained optical line signal to recover a clock signal and a service signal;
carrying out byte alignment and/or equalization decoding and/or error correction decoding on the clock signal to obtain a timestamp signal;
the traffic signal is decoded.
The second processing module recovers the obtained received signal into a clock signal and a service signal, and respectively processes the clock signal and the service signal by using two paths of paths, namely:
demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal;
converting the clock serial signal into a clock parallel signal; and converting the service serial signal into a service parallel signal.
The clock synchronization of the obtained clock signal by the synchronization module comprises:
and performing clock synchronization according to the obtained timestamp signals.
The apparatus further comprises a third processing module configured to at least one of:
performing service packet receiving on the service parallel signals;
sending the timestamp signals after clock synchronization to a master-slave synchronization system;
and de-encapsulating the timestamp signals after clock synchronization to obtain timestamp information in a predefined frame.
The second processing module demodulates the obtained optical line signal, and the recovery of the optical line signal into a clock serial signal and a service serial signal means that:
performing photoelectric conversion on the obtained optical line signal to convert the optical line signal into an electronic line signal;
performing digital-to-analog conversion on the electronic circuit signal to convert the electronic circuit signal into an electronic circuit analog signal;
demodulating the line analog signal to recover a clock analog signal and a service analog signal;
and performing analog-to-digital conversion on the clock analog signal and the service analog signal to convert the clock analog signal and the service analog signal into a clock serial signal and a service serial signal.
The third processing module is further configured to:
and adjusting the time deviation of the time stamp information of the predefined frame obtained by de-encapsulation according to the local time stamp information of the predefined frame.
The third processing module performs time offset adjustment on the time stamp information of the predefined frame obtained by decapsulation according to the local time stamp information of the predefined frame, where the time offset adjustment is performed by:
the time offset is expressed as:
offset=T2-T1-TC1-TC2-delay
wherein, T1 is the local timestamp information of the framing, TC1 is the time delay from the timestamp recording position to the position where the optical signal is converted for transmission, T2 is the timestamp information of the framing obtained by decapsulation, and TC2 is the time delay from the position where the optical line signal is obtained to the timestamp recording position;
and adjusting the time according to the time offset.
Example 1
As shown in fig. 5, in the sending direction, the timestamp information generating module is responsible for generating a clock signal, and sending the clock signal to the error correction coding module for error correction coding; the information after error correction coding is sent to a balanced coding module for balanced coding, and a balanced circuit transmits current; after balanced coding, parallel-serial conversion is carried out on PMA2 (physical medium attribute, which realizes serial-parallel and parallel-serial conversion); other service modules send service signals to a PCS (physical coding repeater, so as to realize balanced coding and Ethernet protocol)/PMA 1 for coding and parallel-serial conversion; and the serial data of the clock signal and the serial data of the service signal are simultaneously sent to a modulation module and modulated to a line for transmission.
As shown in fig. 5, in the receiving direction, the line signal is firstly demodulated in the demodulation module to recover two serial data of the clock signal and the service signal, and the two serial data are respectively sent to PCS/PMA1 and PMA2 for serial-to-parallel conversion, and PCS/PMA1 finishes processing the two serial data and sends the processed two serial data to other service receiving modules; the PMA2 parallel data is byte aligned first, then decoded by the equalizing decoding module, and the decoded data is sent to the error correction decoding module for error correction to obtain correct time stamp information, and finally processed by the time stamp processing module for clock synchronization.
The block diagram of the modem module is shown in fig. 7. After receiving the 10G and 1G digital signals of the PMA1 and PMA2, the modulation module firstly converts the digital signals into analog signals through the DAC, then the analog signals enter the modulator to be modulated into 1-path analog signals, then the analog signals are converted into digital signals through the ADC, and finally the digital signals are converted into optical signals to be sent to a line.
The demodulation module receives an optical signal, converts the optical signal into a digital electric signal firstly, converts the digital electric signal into an analog signal through the DAC, enters the demodulator for demodulation to obtain two paths of analog signals of 10G and 1G, and finally converts the analog signal into a digital signal through the ADC and sends the digital signal to the PMA1 and the PMA 2.
The am and fm principle is briefly introduced as follows: assuming that the clock signal is n (t), other service signals are m (t), and the carrier is coswt, the modulated signal s (t) can be expressed as:
wherein K is a proportionality coefficient.
The scheme provided by the embodiment of the invention can ensure the clock synchronization among the devices.
Example 2
As shown in fig. 6, the clock signal of the apparatus of the present invention is carried by 1588 packet, and performs clock synchronization between the apparatuses at both ends, where the transmission rate of the clock signal is 1Gbps, and the transmission rate of other service signals is 10 Gbps.
Other service signals can be modulated to the line in an amplitude modulation mode, and 1588 data can be modulated to the line in a frequency modulation mode. Error codes can be introduced into the FM signals transmitted in the line, so error correction coding is added into the 1588 line in the transmitting direction, and error correction decoding is added into the receiving direction to correct the error codes introduced in the line transmission process.
Example 3
Another embodiment of the present invention is shown in fig. 8, the sending direction sends the timestamp directly, the encapsulation structure is customized, as shown in fig. 9, the predefined encapsulation frame uses ethernet mode, and encapsulates the timestamp and local delay by 7 pieces 55 and 1 piece d 5.
When the clock synchronization is carried out in the transmitting direction and the receiving direction, the local timestamp T1 and the time delay TC1 from the time stamp recording position to the position of the outlet of the electro-optical conversion module are firstly transmitted, packaged, encoded and then subjected to parallel-serial conversion, and serial data is converted into an analog signal, then modulated together with analog signals of other service channels and transmitted to a line.
After receiving the modulation signal, the receiving direction firstly demodulates to separate the time channel data from other service data, converts the data into digital signals, and after a series of processing such as serial-parallel conversion, byte alignment, decoding, decapsulation and the like, the timestamp frame obtains T1 and TC1, records the timestamp T2 corresponding to the first byte sof after d5, and measures the delay TC2 from the first bit of the sof entering the inlet of the electro-optical conversion module to the timestamp recording position.
The line delay is measured by a line delay tester, for example, an optical fiber can be measured by an OTDR meter. The time offset of the receiving direction relative to the transmitting direction can then be calculated as follows:
offset=T2-T1-TC1-TC2-delay 。
the frequency synchronization of the present embodiment is realized by the clock circuit in fig. 8, and since the time and the traffic signal are derived from the same device, the frequency information carried by the data is the same, so the frequency can be synchronized with the traffic channel.
Although the embodiments of the present invention have been described above, the contents thereof are merely embodiments adopted to facilitate understanding of the technical aspects of the present invention, and are not intended to limit the present invention. It will be apparent to persons skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of lane clock synchronization, comprising:
respectively obtaining a clock signal and a service signal, and respectively processing the clock signal and the service signal by utilizing two paths of paths;
modulating the clock signal and the service signal into a path of signal for transmission;
modulating the clock signal and the service signal into a path of signal for transmission, wherein the clock signal after error correction and/or equalization is converted into a clock serial signal; converting the coded service signal into a service serial signal; modulating the clock serial signal and the service serial signal into a path of signal for transmission;
modulating the clock signal and the service signal into a path of signal for transmission, wherein the clock signal and the service signal are converted into a clock analog signal and a service analog signal; modulating the clock analog signal and the service analog signal into a path of analog signal; converting the analog signal into a digital signal; and converting the digital signal into an optical signal for transmission.
2. The method of claim 1, wherein acquiring a clock signal comprises one of:
acquiring a clock signal generated by a timestamp signal generating module;
acquiring a clock signal sent by a master-slave synchronous system;
the clock signal is obtained in predefined encapsulated frames.
3. The method of claim 1, wherein: modulating the clock analog signal and the service analog signal into a path of analog signal comprises:
the modulated signal s (t) is represented as:
wherein n (t) is a clock analog signal, m (t) is a service analog signal, coswt is a carrier signal, and K is a proportionality coefficient.
4. A method of lane clock synchronization, comprising:
restoring the obtained received signals into clock signals and service signals, and respectively processing the clock signals and the service signals by utilizing two paths of paths;
performing clock synchronization on the obtained clock signal;
recovering the obtained received signal into a clock signal and a service signal, and respectively processing the clock signal and the service signal by utilizing two paths of paths, wherein the demodulation of the obtained optical line signal is carried out to recover the clock signal and the service signal into a clock serial signal and a service serial signal; carrying out byte alignment and/or equalization decoding and/or error correction decoding on the clock serial signal to obtain a timestamp signal; decoding the service serial signal;
demodulating the obtained optical line signal, and recovering the optical line signal into a clock serial signal and a service serial signal; converting the electronic circuit signal into an electronic circuit analog signal; demodulating the electronic circuit analog signal to recover a clock analog signal and a service analog signal; and converting the clock analog signal and the service analog signal into a clock serial signal and a service serial signal.
5. The method of claim 4, wherein: recovering the obtained received signal into a clock signal and a service signal, and respectively processing the clock signal and the service signal by using two paths of paths comprises:
demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal;
converting the clock serial signal into a clock parallel signal; and converting the service serial signal into a service parallel signal.
6. The method of claim 4, wherein: clock synchronizing the obtained clock signal comprises:
and performing clock synchronization according to the obtained timestamp signals.
7. The method of claim 5, wherein: the method further comprises, after the step, at least one of:
performing service packet receiving on the service parallel signal,
sending the timestamp signals after clock synchronization to a master-slave synchronization system;
and de-encapsulating the timestamp signals after clock synchronization to obtain timestamp information in a predefined frame.
8. The method of claim 7, wherein: after the timestamp signals after clock synchronization are de-encapsulated to obtain timestamp information in a predefined frame, the method further comprises the following steps:
and adjusting the time deviation of the time stamp information of the predefined frame obtained by de-encapsulation according to the local time stamp information of the predefined frame.
9. The method of claim 8, wherein: the time deviation adjustment of the time stamp information of the predefined frame obtained by de-encapsulation according to the local time stamp information of the predefined frame comprises the following steps:
the time offset is expressed as:
wherein, T1 is local timestamp information of the fixed frame, TC1 is a time delay from a timestamp recording position to a position where the timestamp is converted into an optical signal for transmission, T2 is timestamp information of the fixed frame obtained by decapsulation, and TC2 is a time delay from a position where the optical line signal is obtained to the timestamp recording position;
and adjusting the time according to the time offset.
10. An apparatus for lane clock synchronization, comprising:
the first processing module is configured to obtain a clock signal and a service signal, and process the clock signal and the service signal by using two paths, respectively, and includes: carrying out error correction and/or equalization processing on the obtained clock signal; encoding the obtained service signal;
the transmission module is used for modulating the clock signal and the service signal into a path of signal to be transmitted;
the transmission module modulates the clock signal and the service signal into a signal for transmission, which means that: converting the clock signal after error correction and/or equalization into a clock serial signal; converting the coded service signal into a service serial signal; modulating the clock serial signal and the service serial signal into a path of signal for transmission;
the transmission module modulates the clock signal and the service signal into a signal for transmission, which means that: converting the clock signal and the service signal into a clock analog signal and a service analog signal; modulating the clock analog signal and the service analog signal into a path of analog signal; converting the analog signal into a digital signal; and converting the digital signal into an optical signal for transmission.
11. The apparatus of claim 10, wherein the first processing module to obtain a clock signal comprises one of:
acquiring a clock signal generated by a timestamp signal generating module;
acquiring a clock signal sent by a master-slave synchronous system;
the clock signal is obtained in predefined encapsulated frames.
12. The apparatus of claim 10, wherein: the transmission module modulates the clock analog signal and the service analog signal into a path of analog signal, which means that:
the modulated signal s (t) is represented as:
wherein n (t) is a clock analog signal, m (t) is a service analog signal, coswt is a carrier signal, and K is a proportionality coefficient.
13. An apparatus for lane clock synchronization, comprising:
the second processing module is used for recovering the obtained received signal into a clock signal and a service signal and respectively processing the clock signal and the service signal by utilizing two paths of paths;
a synchronization module configured to perform clock synchronization on the obtained clock signal;
the second processing module recovers the obtained received signal into a clock signal and a service signal, and respectively processes the clock signal and the service signal by using two paths of paths, namely: demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal; carrying out byte alignment and/or equalization decoding and/or error correction decoding on the clock signal to obtain a timestamp signal; decoding the service signal;
the second processing module demodulates the obtained optical line signal, and the recovery of the optical line signal into a clock serial signal and a service serial signal means that: converting the obtained optical line signal into an electronic circuit signal; converting the electronic circuit signal into an electronic circuit analog signal; demodulating the line analog signal to recover a clock analog signal and a service analog signal; and converting the clock analog signal and the service analog signal into a clock serial signal and a service serial signal.
14. The apparatus of claim 13, wherein: the second processing module recovers the obtained received signal into a clock signal and a service signal, and respectively processes the clock signal and the service signal by using two paths of paths, namely:
demodulating the obtained optical line signal to recover a clock serial signal and a service serial signal;
converting the clock serial signal into a clock parallel signal; and converting the service serial signal into a service parallel signal.
15. The apparatus of claim 13, wherein: the clock synchronization of the obtained clock signal by the synchronization module comprises:
and performing clock synchronization according to the obtained timestamp signals.
16. The apparatus of claim 14, wherein: the system also comprises a third processing module which is set to be at least one of the following modules:
performing service packet receiving on the service parallel signal,
sending the timestamp signals after clock synchronization to a master-slave synchronization system;
and de-encapsulating the timestamp signals after clock synchronization to obtain timestamp information in a predefined frame.
17. The apparatus of claim 16, wherein: the third processing module is further configured to:
and adjusting the time deviation of the time stamp information of the predefined frame obtained by de-encapsulation according to the local time stamp information of the predefined frame.
18. The apparatus of claim 17, wherein: the third processing module performs time offset adjustment on the time stamp information of the predefined frame obtained by decapsulation according to the local time stamp information of the predefined frame, where the time offset adjustment is performed by:
the time offset is expressed as:
wherein, T1 is local timestamp information of the fixed frame, TC1 is a time delay from a timestamp recording position to a position where the timestamp is converted into an optical signal for transmission, T2 is timestamp information of the fixed frame obtained by decapsulation, and TC2 is a time delay from a position where the optical line signal is obtained to the timestamp recording position;
and adjusting the time according to the time offset.
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