CN115858235B

CN115858235B - Cyclic redundancy check processing method and device, circuit, electronic equipment and medium

Info

Publication number: CN115858235B
Application number: CN202310050514.7A
Authority: CN
Inventors: 段庆熙; 郑文明; 刘禄仁; 卢士鹏
Original assignee: Tianyi Cloud Technology Co Ltd
Current assignee: Tianyi Cloud Technology Co Ltd
Priority date: 2023-02-01
Filing date: 2023-02-01
Publication date: 2023-04-21
Anticipated expiration: 2043-02-01
Also published as: WO2024159956A1; CN115858235A

Abstract

The application provides a cyclic redundancy check processing method and device, a circuit, electronic equipment and a medium, and relates to the technical field of communication, wherein the method comprises the following steps: writing each bit of data in the original data to be transmitted into a first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail end of the original data to be transmitted; controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multi-round exclusive OR operation, and generating a redundancy check code of original data to be transmitted at the position of a blank check code; and obtaining the data to be transmitted according to the original data to be transmitted and the redundancy check code. According to the method and the device, the operation of the cyclic redundancy check algorithm is completed in the memristor array by utilizing the memory-calculation integrated characteristic or the calculation capability of the memristor array, so that data carrying can be reduced, further the requirement on memory bandwidth can be reduced, meanwhile, the efficiency of generating the redundancy check code of data is improved, and the processing power consumption is reduced.

Description

Cyclic redundancy check processing method and device, circuit, electronic equipment and medium

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a cyclic redundancy check processing method and apparatus, a circuit, an electronic device, and a medium.

Background

The CRC (Cyclic redundancy check ) algorithm is widely used in data communication and storage devices as a powerful method of handling data errors. It is also used in many other fields, such as testing of integrated circuits and detection of logic faults. The basic principle of the CRC algorithm is based on long division of serial data transmission, namely, information to be transmitted is shifted left by a plurality of bits, and then modulo-2 division is carried out on the information and a generator polynomial, namely, exclusive-or calculation is carried out according to the bits, and the obtained remainder is CRC check information; the generated check code is added behind the original data to form new binary data, and finally the new binary data are transmitted together.

As the amount of data continues to rise, the processing efficiency of CRC algorithms by software is severely limited. Since the data stored in the memory is usually read into the CPU (Central Processing Unit ) during the process of generating the redundancy check code by the software processing CRC algorithm, the redundancy check code is calculated by the arithmetic unit. Therefore, all data are required to be read from the memory to the CPU end and then calculated by the arithmetic unit, and the memory and the arithmetic unit are frequently carried, so that larger power consumption is generated, and the efficiency is greatly reduced.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

In view of the foregoing, the present application has been developed to provide a cyclic redundancy check processing method and apparatus, a circuit, an electronic device, and a medium that overcome or at least partially solve the foregoing, including:

a cyclic redundancy check processing method applied to a transmitting end, the method comprising:

writing each bit of data in the original data to be transmitted into a first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail end of the original data to be transmitted;

controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multi-round exclusive OR operation, and generating a redundancy check code of the original data to be transmitted at the position of the blank check code;

and obtaining the data to be transmitted according to the original data to be transmitted and the redundancy check code.

A cyclic redundancy check processing method applied to a receiving end, the method comprising:

Writing each bit of data in the data to be received into a first memristor array according to columns, wherein the data to be received comprises original data to be received and redundancy check codes of a first preset bit number;

controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multiple exclusive OR operations so as to obtain a cyclic redundancy check result;

and determining whether to receive the original data to be received according to the cyclic redundancy check result.

A cyclic redundancy check processing apparatus applied to a transmitting end, the apparatus comprising:

the first data writing module is used for writing each bit of data in the original data to be transmitted into the first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail end of the original data to be transmitted;

the first data operation module is used for controlling the input voltage of the first memristor array according to a preset check polynomial coefficient so as to perform multi-round exclusive-or operation and generate a redundancy check code of the original data to be transmitted at the position of the blank check code;

and the encrypted data generation module is used for obtaining the data to be transmitted according to the original data to be transmitted and the redundancy check code.

A cyclic redundancy check processing apparatus for use at a receiving end, the apparatus comprising:

the second data writing module is used for writing each bit of data in the data to be received into the first memristor array according to columns, wherein the data to be received comprises the original data to be received and redundancy check codes of a first preset bit number;

the second data operation module is used for controlling the input voltage of the first memristor array according to a preset check polynomial coefficient so as to perform multiple exclusive OR operations and obtain a cyclic redundancy check result;

and the checking result determining module is used for determining whether to receive the original data to be received according to the cyclic redundancy checking result.

A cyclic redundancy check processing circuit, the circuit comprising a first memory cell and a second memory cell respectively connected with an arithmetic unit;

the first storage unit comprises a second memristor array, and a second word line controller, a second bit line controller and a second analog-to-digital conversion module which are respectively connected with the second memristor array, wherein the second word line controller is used for controlling gating of word lines in the second memristor array, the second bit line controller is used for controlling gating of bit lines in the second memristor array, the second memristor array is used for storing a preset test polynomial coefficient, and the second analog-to-digital conversion module is used for converting an analog value output by the second memristor array into a digital value;

The second storage unit comprises a third memristor array, a third word line controller, a third bit line controller and a third analog-to-digital conversion module, wherein the third word line controller, the third bit line controller and the third analog-to-digital conversion module are respectively connected with the third memristor array, the third word line controller is used for controlling gating of word lines in the third memristor array, the third bit line controller is used for controlling gating of bit lines in the third memristor array, the third memristor array is used for storing original data to be sent, and the third analog-to-digital conversion module is used for converting analog values output by the third memristor array into digital values;

the operation unit comprises a first memristor array, a first word line controller, a first bit line controller, a first analog-to-digital conversion module and a control circuit module, wherein the first word line controller, the first bit line controller and the first analog-to-digital conversion module are respectively connected with the first memristor array, the control circuit module is connected with the first analog-to-digital conversion module, the first word line controller is used for controlling gating of word lines in the first memristor array, the first bit line controller is used for controlling gating of bit lines in the first memristor array, the first analog-to-digital conversion module is used for converting analog values output by the first memristor array into digital values, the control circuit module is used for reading to-be-transmitted original data stored by the third memristor array, writing the to-be-transmitted original data into the first memristor array according to preset check polynomial coefficients stored by the second memristor array, and controlling input voltage of the first memristor array through controlling the first word line controller, so that the first memristor array performs redundancy code operation on the first memristor array to generate redundancy code to be transmitted by the first memristor array.

An electronic device comprising a processor, a memory and a computer program stored on the memory and capable of running on the processor, which when executed by the processor, performs the steps of the cyclic redundancy check processing method as described above.

A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of a cyclic redundancy check processing method as described above.

The application has the following advantages:

in the embodiment of the application, writing each bit of data in original data to be sent into a first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail of the original data to be sent; controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multi-round exclusive OR operation, and generating a redundancy check code of original data to be transmitted at the position of a blank check code; and obtaining the data to be transmitted according to the original data to be transmitted and the redundancy check code. According to the method and the device, the operation of the cyclic redundancy check algorithm is completed in the memristor array by utilizing the integral memory-calculation characteristic or calculation capability of the memristor array, so that data is not required to be sent to a CPU for calculation of the cyclic redundancy check code and then sent back to the register, therefore, data carrying can be reduced, further, the requirement on memory bandwidth can be reduced, meanwhile, the efficiency of generating the redundancy check code of the data is improved, and the processing power consumption is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the description of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a flow chart of steps of a cyclic redundancy check processing method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memristor structure;

FIG. 3 is a graph of current-voltage characteristics of a memristor under voltage;

FIG. 4 is a logic definition for a logic implementation using memristors;

FIG. 5 is a schematic diagram of a specific method of implementing exclusive OR logic for a memristor in an example of the present disclosure;

FIG. 6 is a schematic diagram of a circuit implementing exclusive OR logic for a memristor array in an example of the present application;

FIG. 7 is a circuit diagram of a CRC processing circuit according to an example of the present application;

FIG. 8 is a schematic diagram of an input voltage for each round of XOR operations in an example of the present application;

FIG. 9 is a flow chart illustrating steps of another CRC processing method according to an embodiment of the present application;

FIG. 10 is a block diagram of a cyclic redundancy check processing apparatus according to an embodiment of the present application;

fig. 11 is a block diagram of another cyclic redundancy check processing apparatus according to an embodiment of the present application.

Detailed Description

In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. It will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

CRC algorithm is a very common data checking method in software and specific hardware structures. However, as the amount of data increases, the processing efficiency of the CRC algorithm by software processing is severely limited. Since the data stored in the memory is usually read into the CPU and calculated by the arithmetic unit to generate the redundancy check code in the software processing CRC algorithm. Therefore, all data are required to be read from the memory to the CPU end and then calculated by the arithmetic unit, and the memory and the arithmetic unit are frequently carried, so that larger power consumption is generated, and the efficiency is greatly reduced.

The processor and the memory of the traditional von neumann architecture are separated, data are required to be frequently carried between the memory and the arithmetic unit in the working process of the computer, larger power consumption can be generated, and meanwhile, the processing speed of the processor is faster than the access speed of the data, so that the efficiency of the computer is severely restricted. Therefore, the implementation of the CRC algorithm is limited by the speed of the system CPU, and the communication efficiency of the system is greatly reduced.

Memristors have gained widespread attention and found potential applications in non-volatile memories and in-memory computing due to their computationally integrated nature and good performance. The method has the performances of high speed, high expandability, non-volatility, parallelism calculation, integration of memory calculation, low power consumption and the like, and becomes a strong candidate of non-volatile logic. The memristor is a simple metal-insulator-metal sandwich structure, and the resistance of the memristor can be switched between two digital states of a low-resistance state and a high-resistance state, so that a foundation is laid for logic operation.

One of the main technical ideas of the embodiments of the present application is that the operation of the cyclic redundancy check algorithm is completed in the memristor array by utilizing the characteristics of the memory integration and the capability of exclusive-or calculation of the memristor array, so as to improve the processing efficiency of the cyclic redundancy check algorithm and reduce the processing power consumption of the cyclic redundancy check algorithm.

Referring to fig. 1, a step flow chart of a cyclic redundancy check processing method provided in an embodiment of the present application is shown, where in the embodiment of the present application, the method is applied to a transmitting end, so as to implement fast generation of a redundancy check code of original data to be transmitted at the transmitting end, and obtain corresponding data to be transmitted. The method may comprise the steps of:

step 101, writing each bit of data in original data to be transmitted into a first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail of the original data to be transmitted;

step 102, controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multiple exclusive OR operations, and generating a redundancy check code of the original data to be transmitted at the position of the blank check code;

and step 103, obtaining the data to be transmitted according to the original data to be transmitted and the redundancy check code.

According to the method, each bit of data in the original data to be sent is written into the first memristor array according to columns, and blank check codes with first preset bits are filled at the tail of the original data to be sent; controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multi-round exclusive OR operation, and generating a redundancy check code of original data to be transmitted at the position of a blank check code; according to the original data to be sent and the redundancy check code, the data to be sent is obtained, the operation of a cyclic redundancy check algorithm is completed in the memristor array, so that the data is not required to be sent to a CPU for calculation of the cyclic redundancy check code and then sent back to a register, data carrying can be reduced, the requirement on access bandwidth can be further reduced, meanwhile, the efficiency of generating the redundancy check code of the data is improved, and the processing power consumption is reduced.

Next, the cyclic redundancy check processing method in the present exemplary embodiment will be further described.

Memristors, collectively known as memristors (memristors), are resistors with a memory resistance function. FIG. 2 is a schematic diagram of a memristor, which is a bipolar device including a top electrode T1 and a bottom electrode T2, wherein the resistance change process of the memristor is related to the polarity of an input voltage.

Referring to fig. 3, fig. 3 shows a current-voltage characteristic diagram of the memristor under the action of voltage, abbreviated as I-V diagram. When a first threshold voltage Vset is applied at the top electrode T1, the memristor may be transitioned from a high resistance state (low conductance state) to a low resistance state (high conductance state); when a second threshold voltage Vreset is applied at the bottom electrode T2, the memristor may be turned from a low resistance state to a high resistance state, and thus has two stably transitioned resistance states.

The logic definition for a logic implementation with memristors is defined as shown in fig. 4. Defining a high voltage as logic "1", and a low voltage as logic "0"; the low resistance state (high conductance state) is defined as a logic "1" and the high resistance state (low conductance state) is defined as a logic "0".

As shown in FIG. 5, a specific method schematic diagram of implementing exclusive OR logic for a memristor in an example of the present disclosure is shown. When the exclusive OR logic is realized, taking the initial state of the memristor as an input voltage p, reading an initial resistance state Z, and if the initial resistance state Z is a high resistance state '0', inputting another input voltage q from the end of a top electrode T1, and placing a bottom electrode T2 at 0 voltage; if the initial resistance state is the low resistance state "1", another input voltage q is input from the end of the bottom electrode T2, the top electrode T1 is set at 0 voltage, and the last resistance Z' is taken as output. When p and q are the same, the output last state resistance is 0, and when p and q are different, the output last state resistance is 1, so that exclusive OR logic is realized.

Memristor arrays may be considered as devices in the form of a matrix formed by the arrangement of a plurality of memristors.

As shown in FIG. 6, a schematic diagram of a circuit implementing exclusive OR logic for a memristor array in an example of the present application is shown. The original data can be stored in a single memristor corresponding to the memristor array according to bits and arranged in a diagonal manner in the memristor array, in this example, the original data stored in the memristor array is 110101, the input data is 10110, the control circuit configures voltage information corresponding to the input data for the input data by combining the specific method shown in fig. 5 through a first step of reading operation, and the calculation and storage of the data can be realized through an exclusive or operation of the memristor array, namely, a second step of writing operation is realized. For example, the original data stored in the memristor in the sixth row of the first column is 1, the corresponding input data is 1, it can be determined in conjunction with fig. 5 that the voltage corresponding to the input data, that is, the negative voltage, is input to the bottom electrode T2 end of the memristor in the sixth row of the first column, the value is 1, the corresponding output last state resistance is 0, and at this time, the value stored in the memristor in the sixth row of the first column is changed from 1 to 0; if the original data stored by the memristor of the second column and the fifth row is 1, the corresponding input data is 0, and it can be determined by combining fig. 5 that the voltage corresponding to the input data, namely the negative voltage, is input to the bottom electrode T2 end of the memristor of the second column and the fifth row, the value is 0, the corresponding output final resistance is 1, at this time, the value stored by the memristor of the second column and the fifth row is still 1, and so on, the calculation and storage of the data can be realized in the memristor array.

And step 101, writing each bit of data in the original data to be transmitted into a first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail of the original data to be transmitted.

The original data to be sent is binary, the number of columns of the first memristor array is larger than the number of bits of the original data to be sent, and specifically, the number of columns of the first memristor array is larger than or equal to the sum of the number of bits of the original data to be sent and a first preset number of bits. Illustratively, when the original data to be transmitted is 6 bits and the first preset number of bits is 4 bits, the number of columns of the first memristor array is greater than or equal to 10. Generally, in order to improve the utilization of the device, the number of columns of the first memristor array is equal to the sum of the number of bits of the original data to be transmitted and the first preset number of bits.

Each bit of data in the original data to be sent is written into the first memristor array according to columns, and it can be understood that after the original data to be sent is written into the first memristor array, data on different bits of the original data are stored in different columns of the first memristor array, and data on adjacent bits are stored in adjacent columns of the first memristor array. For example, a target memristor corresponding to each bit of data of original data to be sent may be determined first, specifically, the first memristor array may be gated by a first word line controller and a first bit line controller of the first memristor array, and the target memristor voltage and polarity are controlled according to the data corresponding to the target memristor, so that writing (also referred to as storing) of the data into the corresponding target memristor is implemented, where each bit of data corresponds to one target memristor.

The blank check code refers to a check code in which the data on all bits is 0. Each memristor in the first memristor array stores data of 0 in an initial state. Filling the blank check code with the first preset bit number at the end of the original data to be transmitted can be understood as reserving the columns with the number corresponding to the first preset bit number at the right side of the column where the data with the lowest bit of the original data to be transmitted is located.

In some optional embodiments of the present application, the original data to be sent includes a second preset number of bits; writing each bit of data in the original data to be sent into the first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail of the original data to be sent, which may include:

writing the highest-order data of the original data to be sent into memristors of a first column of the first memristor array, and writing adjacent-order data of the original data to be sent into memristors of an adjacent column of the first memristor array;

and filling blank check codes with a first preset bit number in the remaining columns of the first memristor array in a left-to-right sequence.

In this embodiment, the number of columns of the first memristor array may be equal to a sum of the first preset number of bits and the second preset number of bits. In the process of writing the original data to be transmitted into the first memristor array, the highest data of the original data to be transmitted is stored in the memristor corresponding to the first column of the first memristor array, the next highest data is stored in the memristor corresponding to the second column of the first memristor array, and so on. After the original data to be sent is written into the first memristor array, since the data stored by the memristors in the first memristor array in the initial state is 0, blank check codes with a first preset bit number can be automatically filled.

In one example, to reduce the size of the memristor array, the original data to be transmitted and the first preset number of bits of blank check code are located in the same row in the first memristor array.

In other optional embodiments of the present application, the original data to be sent includes a second preset number of bits; writing each bit of data in the original data to be sent into the first memristor array according to columns, and filling a blank check code with a first preset bit number at the tail of the original data to be sent, which may include:

writing the highest-order data of the original data to be sent into memristors of a first column of the first memristor array, and writing adjacent-order data of the original data to be sent into memristors of adjacent columns of the first memristor array, wherein the original data to be sent is diagonally arranged in the first memristor array;

and filling blank check codes with a first preset bit number in the remaining columns of the first memristor array according to the sequence from left to right, wherein the blank check codes and the original data to be sent are arranged in a diagonal line in the first memristor array.

In this embodiment, the number of columns of the first memristor array may be equal to a sum of the first preset number of bits and the second preset number of bits. In the process of writing the original data to be transmitted into the first memristor array, the highest data of the original data to be transmitted is stored in the memristor corresponding to the first column of the first memristor array, the next highest data is stored in the memristor corresponding to the second column of the first memristor array, and so on. After the original data to be sent is written into the first memristor array, since the data stored by the memristors in the first memristor array in the initial state is 0, blank check codes with a first preset bit number can be automatically filled; and the original data to be transmitted and the blank check codes with the first preset bit number are arranged in a diagonal line in the first memristor array. For example, the highest order bits of the original data to be transmitted are stored in memristors of a first column and a first row of a first memristor array, the next highest order bits are stored in memristors of a second column and a second row of the first memristor array, and so on, the original data to be transmitted and the blank check code are arranged along a diagonal line from the upper left corner to the lower right corner of the first memristor array. Or, as shown in fig. 7, fig. 7 shows a circuit schematic diagram of a cyclic redundancy check processing circuit in an example of the present application, where original data to be sent is 110101, the highest bit of the original data to be sent is stored in the memristor of the n-th row of the first column of the first memristor array, next highest bit data is stored in the memristor of the n-1 th row of the second column of the first memristor array, and so on, so as to implement diagonal arrangement of the original data to be sent and blank check codes from the lower left corner to the upper right corner of the first memristor array, where n is equal to the sum of the first preset bit number and the second preset bit number, that is, the last row of the first memristor array.

By writing the original data to be transmitted and the blank check code into the first memristor array in a diagonal arrangement mode, parallel exclusive OR operation of a plurality of data bits can be achieved, and therefore the generation efficiency of the redundancy check code is improved.

In some optional embodiments of the present application, a plurality of original data to be sent may be stored in a third memristor array in rows, each bit of data in the original data to be sent is written in a first memristor array in columns, the original data to be sent may be obtained by performing a read operation on the third memristor array, and then each bit of data in the obtained original data to be sent is written in the first memristor array in columns. The voltage and polarity of memristors in the third memristor array may be read by gating the third memristor array by the third word line controller and the third bit line controller of the third memristor array to obtain the original data to be transmitted stored by the third memristor array.

And 102, controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multiple exclusive OR operations, and generating a redundancy check code of the original data to be transmitted at the position of the blank check code.

The redundancy check code is a remainder obtained by dividing two bit metadata streams by modulo-2 division, wherein the modulo-2 division is similar to arithmetic division, but the result of each bit division does not affect other bits, i.e. the previous bit is not borrowed, i.e. exclusive-or operation is performed according to the bits. The dividend is obtained by adding 0 of a first preset bit number at the end of the original data to be transmitted, the divisor is a preset check polynomial coefficient which is pre-agreed by the transmitting end and the receiving end, and the divisor can be set according to different check requirements. The number of bits of the preset check polynomial coefficient is 1 more than the first preset number of bits.

According to the embodiment, the input voltage of the first memristor array is controlled according to the preset check polynomial coefficient so as to perform multiple exclusive OR operation, namely the divisor formed by the original data to be transmitted and the blank check code is subjected to modulo-2 division with the preset check polynomial coefficient. In the operation process, the result of each round of exclusive-or operation is stored in the first memristor array by utilizing the integral storage and calculation characteristic of the memristor array so as to participate in the next round of exclusive-or operation, thereby realizing cyclic redundancy check calculation.

In some optional embodiments of the present application, a preset check polynomial coefficient may be stored in the second memristor array, and the controlling the input voltage of the first memristor array according to the preset check polynomial coefficient to perform a multiple-round exclusive-or operation, and generating, at a position of the blank check code, a redundancy check code of the original data to be sent may include:

Reading the voltage of the second memristor array, and determining the preset check polynomial coefficient according to the voltage of the second memristor array;

and controlling the input voltage of the first memristor array according to the preset check polynomial coefficient to perform multiple exclusive OR operations, and generating a redundancy check code of the original data to be transmitted at the position of the blank check code.

In this embodiment, the preset check polynomial coefficient may be stored through the second memristor array, and the preset check polynomial coefficient may be obtained by performing a read operation on the second memristor array, that is, the voltage and the polarity of the memristors in the second memristor array are read by gating the second word line controller and the second bit line controller of the second memristor array, so as to obtain the preset check polynomial coefficient, and then the input voltage of the first memristor array is controlled according to the preset check polynomial coefficient, so as to perform multiple exclusive or operations, and obtain the redundancy check code. The preset check polynomial coefficients may be arranged in rows or diagonal form in the second memristor array.

Further, the controlling the input voltage of the first memristor array according to the preset check polynomial coefficient to perform a multiple-round exclusive-or operation, and generating the redundancy check code of the original data to be sent at the position of the blank check code may include:

Controlling the input voltage of the corresponding memristor in the target column of the first memristor array according to the highest bit data of the preset check polynomial coefficient, and controlling the input voltage of the memristor in the corresponding adjacent column of the first memristor array according to the adjacent bit data of the preset check polynomial coefficient so as to perform exclusive-or operation of the current round; wherein, when the current round is 1, the target column is the first column;

updating the data stored in the first memristor array according to the result of the exclusive-or operation of the current round;

adding 1 to the current round, adding 1 to the column number corresponding to the target column, continuously executing the control of the input voltage of the memristor corresponding to the target column of the first memristor array according to the highest bit data of the preset check polynomial coefficient, and controlling the input voltage of the memristor corresponding to the adjacent column of the first memristor array according to the adjacent bit data of the preset check polynomial coefficient, so as to perform exclusive-or operation of the current round;

when the current round reaches a preset round, acquiring data stored in the position of the blank check code, and determining the data stored in the position of the blank check code as the redundancy check code of the original data to be transmitted.

In this embodiment, the original data to be transmitted and the blank check code are stored in the first memristor array in a diagonal form, the most significant bit of the original data to be transmitted is stored in the first column of the first memristor array, the data with the same number of bits as the preset check polynomial coefficient is selected to remove the preset check polynomial coefficient from the most significant bit of the original data to be transmitted according to the calculation principle of modulo 2 division, and after each removal, one bit is moved backwards (i.e. to the right) until the number of bits of the remainder is smaller than the divisor, and the remainder is the final remainder.

Therefore, when the first round of exclusive-or operation is performed, the voltage of the memristor corresponding to the first column of the first memristor is controlled according to the highest-order data of the preset check polynomial coefficient, the voltages of the memristors corresponding to the other columns of the first memristor are respectively controlled according to the other-order data of the preset check polynomial coefficient, the first round of exclusive-or operation is realized, the result of the first round of exclusive-or operation is directly reserved in the first memristor array, and the original value stored by the corresponding memristor in the first memristor array is replaced. After the first round of exclusive-or operation is finished, one bit is moved backwards, namely, when the second round of exclusive-or operation is finished, the target column is the second column, the voltage of the memristor corresponding to the second column of the first memristor is controlled according to the highest bit data of the preset check polynomial coefficient, the voltages of the memristors corresponding to other columns of the first memristor are respectively controlled according to other bit data of the preset check polynomial coefficient, the second round of exclusive-or operation is realized, the result of the second round of exclusive-or operation is directly reserved in the first memristor array, after the second round of exclusive-or operation is finished, one bit is moved backwards, the third round of exclusive-or operation is continuously performed until the number of bits of the remainder is smaller than the number of bits of the preset polynomial coefficient, namely, when the current round reaches the preset round, the data stored at the position of the blank check code are acquired, and the data stored at the position of the blank check code are determined to be the redundancy check code of the original data to be transmitted. The preset round is equal to the difference of the sum of the first preset number of bits and the second preset number of bits minus the third preset number of bits.

As shown in fig. 7, the original data to be transmitted is 110101 written into the first memristor array, and the preset check polynomial coefficient is 10110, so that the number of bits of the redundancy check code can be determined to be 4, that is, the first preset number of bits is 4. Because the initial state of the first memristor array is 0, 4 0 s are automatically filled at the tail of the original data to be sent, which are stored in the first memristor array, so that the original data to be sent and blank check codes are written into the first memristor array.

The first control circuit controls the position and the polarity of the input voltage of the word line of the first memristor array according to the preset check polynomial coefficient and the specific method for realizing the exclusive-or logic of the memristor shown in fig. 5, and performs multiple exclusive-or operations.

In this example, generating the redundancy check code requires five exclusive-or operations, each of which has an input voltage as shown in fig. 8. The first round of exclusive-or operation input voltage corresponds to the first column of fig. 8, and the row position of fig. 8 corresponds to the row position of the first memristor array shown in fig. 7, that is, the negative voltage with the memristor input value of 1 of the tenth row of the first memristor array, that is, the negative voltage with the memristor input value of 1 of the tenth row of the first column of the first memristor array; the voltage with the memristor input value of 0 is the voltage with the memristor input value of 0 of the ninth row of the first memristor array, namely the voltage with the memristor input value of 0 of the ninth row of the second column of the first memristor array; the positive voltage with the memristor input value of 1 for the eighth row of the first memristor array is the positive voltage with the memristor input value of 1 for the eighth row of the third column of the first memristor array; a negative voltage with a memristor input value of 1 for a seventh row of the first memristor array is a negative voltage with a memristor input value of 1 for a seventh column of the fourth column of the first memristor array; and the voltage with the memristor input value of 0 is the voltage with the memristor input value of 0 of the sixth row of the first memristor array, namely the voltage with the memristor input value of 0 of the sixth row of the fifth column of the first memristor array. By reading the resistance of the memristors on the diagonal of the memristor array at this time, a first round of exclusive-or operation result 0110010000 can be obtained, and the first round of exclusive-or operation result is directly stored in the memristors on the diagonal of the memristor array.

Similarly, the second round of xor operation input voltage corresponds to the second column of fig. 8, and is xored with the first round of xor operation result 0110010000, so as to obtain a second round of xor operation result 0011110000. The third round of exclusive-or operation input voltage corresponds to the third column of fig. 8, and is exclusive-or operated with the second round of exclusive-or operation result 0011110000, so as to obtain a third round of exclusive-or operation result of 0001000000. The fourth round of xor operation input voltage corresponds to the fourth column of fig. 8, and is xored with the third round of xor operation result 0001000000, so as to obtain a fourth round of xor operation result 0000011000. Since the first five bits in the fourth round of xor operation result are 0, the xor operation will not be performed any more, it can be understood that after the fourth round of xor operation, the xor operation with the quotient of 0 is performed once, and since the result of 0 and any number of xor is equal to any number when the quotient is 0, the xor operation of this round can be omitted, and therefore, the input voltage of the fifth round of xor operation can directly correspond to the fifth column of fig. 8, and the xor operation is performed with the fourth round of xor operation result 0000011000, so that the fifth round of xor operation result is 0000001110, that is, the redundancy check code is 1110.

After the redundancy check code is obtained, the redundancy check code is added to the tail end of the original data to be transmitted, so that the data to be transmitted can be generated, and the data to be transmitted can be understood as the data obtained by encrypting the original data to be transmitted through a CRC algorithm.

Further, in some optional embodiments of the present application, after the data to be sent is obtained, the data to be sent may be stored in the third memristor array. For example, an input voltage of the third memristor array may be controlled according to each bit of the data to be transmitted, so as to store the data to be transmitted in the third memristor array. Wherein the data to be transmitted may be stored in the same row of the third memristor array.

In other alternative embodiments of the present application, the third memristor array may store the raw data to be transmitted, as shown in fig. 7, where the raw data 110101 to be transmitted is stored in the third memristor array from left to right in columns. After the redundancy check code is obtained, the redundancy check code can be directly stored at the tail end of the corresponding original data to be transmitted in the third memristor array, the original data to be transmitted and the corresponding redundancy check code are stored in the same row of the third memristor array, and the data stored in the row are the data to be transmitted.

According to the method, each bit of data in the original data to be sent is written into the same row of the first memristor array according to columns, and blank check codes with first preset bits are filled at the tail of the original data to be sent; controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multi-round exclusive OR operation, and generating a redundancy check code of original data to be transmitted at the position of a blank check code; according to the original data to be sent and the redundancy check code, the data to be sent is obtained, the operation of a cyclic redundancy check algorithm is completed in the memristor array, so that the data is not required to be sent to a CPU for calculation of the cyclic redundancy check code and then sent back to a register, data carrying can be reduced, the requirement on access bandwidth can be further reduced, meanwhile, the efficiency of generating the redundancy check code of the data is improved, and the processing power consumption is reduced.

Referring to fig. 9, another cyclic redundancy check processing method according to an embodiment of the present application is shown, and the method is applied to a receiving end, so as to implement fast verification of a cyclic redundancy check result of data to be received at the receiving end. The method may comprise the steps of:

Step 901, writing each bit of data in the data to be received into a first memristor array according to columns, wherein the data to be received comprises original data to be received and redundancy check codes with a first preset bit number.

The data to be received can be considered as encrypted data obtained after the sending end encrypts the original data to be sent by the CRC algorithm. The data to be received can be called as data to be transmitted at the transmitting end, and is obtained by splicing the original data to be transmitted and the corresponding redundancy check code, namely, the redundancy check code is added at the tail end of the original data to be transmitted. The original data to be transmitted may be referred to as original data to be received at the receiving end.

After receiving the data to be received, the receiving end may write each bit of data in the data to be received into the first memristor array in columns, and in some optional embodiments of the present application, writing each bit of data in the data to be received into the first memristor array in columns may include:

and writing the highest bit data of the data to be received into memristors of a first column of the first memristor array, and writing the adjacent bit data of the data to be received into memristors of an adjacent column of the first memristor array.

In other optional embodiments of the present application, writing each bit of data in the data to be received into the first memristor array in columns may include:

and writing the highest data of the data to be received into memristors in a first column of the whole column of the first memristors, and writing the adjacent bit data of the data to be received into memristors in adjacent columns of the first memristor array, wherein the data to be received is diagonally arranged in the first memristor array.

Since the implementation process of step 901 is similar to the process of writing the original data to be transmitted and the blank check code into the first memristor array in columns, the description is relatively simple, and the relevant points are described in the section of step 101.

And step 902, controlling the input voltage of the first memristor array according to a preset check polynomial coefficient so as to perform multiple exclusive OR operations and obtain a cyclic redundancy check result.

According to the embodiment, the input voltage of the first memristor array is controlled according to the preset check polynomial coefficient to perform multi-round exclusive OR operation, namely, the mode 2 division is performed between the data to be received serving as the divisor and the preset check polynomial coefficient. In the operation process, the result of each round of exclusive-or operation is stored in the first memristor array by utilizing the integral storage and calculation characteristic of the memristor array so as to participate in the next round of exclusive-or operation, thereby realizing cyclic redundancy check calculation.

In some optional embodiments of the present application, the preset check polynomial coefficient is stored in the second memristor array, and the controlling the input voltage of the first memristor array according to the preset check polynomial coefficient to perform multiple exclusive-or operations, to obtain a cyclic redundancy check result includes:

and controlling the input voltage of the first memristor array according to the preset check polynomial coefficient so as to perform multiple exclusive OR operations and obtain a cyclic redundancy check result. The cyclic redundancy check result is data stored in the position of the redundancy check code in the first memristor array after multiple exclusive OR operations are carried out.

In some optional embodiments of the present application, the preset check polynomial coefficient includes a third preset bit number, and the third preset bit number is smaller than the bit number of the data to be received, and the controlling the input voltage of the first memristor array according to the preset check polynomial coefficient to perform multiple exclusive-or operation, to obtain a cyclic redundancy check result includes:

and when the current round reaches a preset round, acquiring data stored in the position of the redundancy check code, and determining the data stored in the position of the redundancy check code as a cyclic redundancy check result.

Since step 902 is similar to step 102 previously described, the description is relatively simple, and the relevant points are described in the section of step 102.

And step 903, determining whether to receive the original data to be received according to the cyclic redundancy check result.

After the cyclic redundancy check result is obtained, whether the original data to be received in the data to be received changes in the transmission process can be judged according to the cyclic redundancy check result, and whether the original data to be received is received or not can be further determined.

For example, when the crc result is 0, which indicates that the original data to be received has no transmission change during the transmission, the original data to be received in the data to be received may be considered to be correct, and at this time, the receiving end may receive the original data to be received.

When the cyclic redundancy check result is not 0, it indicates that the original data to be received has sent a change in the transmission process, and it can be considered that the original data to be received in the data to be received is wrong at this time, and at this time, the receiving end may not receive the original data to be received.

Further, in some optional embodiments of the present application, the process of receiving the raw data to be received may include:

And extracting data with a second preset bit number from the data to be received from left to right, and determining the data as the original data to be received, wherein the second preset bit number is equal to the difference between the bit number of the data to be received and the first preset bit number.

In this embodiment, when the crc result is 0, data with a second preset number of bits may be extracted from the data to be received from left to right, that is, the original data to be received.

According to the method, each bit of data in the data to be received is written into the first memristor array according to columns, and the data to be received comprises original data to be received and redundancy check codes with first preset bits; controlling the input voltage of the first memristor array according to a preset check polynomial coefficient to perform multiple exclusive OR operations so as to obtain a cyclic redundancy check result; and determining whether to receive the original data to be received according to the cyclic redundancy check result. According to the method and the device, the operation of the cyclic redundancy check algorithm is completed in the memristor array by utilizing the integral memory-calculation characteristic or calculation capability of the memristor array, so that data is not required to be sent to a CPU for calculation of the cyclic redundancy check code and then sent back to a register, therefore, data carrying can be reduced, further the requirement on memory bandwidth can be reduced, meanwhile, the efficiency of cyclic redundancy check on the data is improved, and processing power consumption is reduced.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments and that the acts referred to are not necessarily required by the embodiments of the present application.

Referring to fig. 10, a block diagram of a cyclic redundancy check processing apparatus provided in an embodiment of the present application is shown, where the cyclic redundancy check processing apparatus is applied to a transmitting end, and corresponds to the foregoing embodiment of a cyclic redundancy check processing method applied to the transmitting end, the apparatus may include the following modules:

a first data writing module 1001, configured to write each bit of data in original data to be sent into a first memristor array in columns, and fill a blank check code with a first preset bit number at the end of the original data to be sent;

the first data operation module 1002 is configured to control an input voltage of the first memristor array according to a preset check polynomial coefficient, perform multiple exclusive or operations, and generate a redundancy check code of the original data to be sent at the position of the blank check code;

And the encrypted data generating module 1003 is configured to obtain data to be sent according to the original data to be sent and the redundancy check code.

Optionally, the first data writing module 1001 includes:

the first original data writing sub-module is used for writing the highest-order data of the original data to be sent into memristors of a first column of the first memristor array, and writing the adjacent-order data of the original data to be sent into memristors of an adjacent column of the first memristor array;

and the first blank check code filling submodule is used for filling blank check codes with a first preset bit number in the rest columns of the first memristor array according to the sequence from left to right.

Optionally, the first data writing module 1001 includes:

the second original data writing sub-module is used for writing the highest-order data of the original data to be sent into memristors of a first column of the first memristor array, and writing the adjacent-order data of the original data to be sent into memristors of the adjacent column of the first memristor array, wherein the original data to be sent is arranged in a diagonal line in the first memristor array;

And the second blank check code filling sub-module is used for filling blank check codes with a first preset bit number in the rest columns of the first memristor array according to the sequence from left to right, and the blank check codes and the original data to be sent are arranged in a diagonal line in the first memristor array.

Optionally, the preset check polynomial coefficients are stored in a second memristor array, and the first data operation module 1002 includes:

the polynomial coefficient acquisition sub-module is used for reading the voltage of the second memristor array and determining the preset check polynomial coefficient according to the voltage of the second memristor array;

and the polynomial coefficient-based operation module is used for controlling the input voltage of the first memristor array according to the preset check polynomial coefficient so as to perform multi-round exclusive OR operation and generate a redundancy check code of the original data to be transmitted at the position of the blank check code.

Optionally, the first data operation module 1002 includes:

the first voltage input sub-module is used for controlling the input voltage of the corresponding memristor in the target column of the first memristor array according to the highest bit data of the preset check polynomial coefficient, and controlling the input voltage of the memristor in the corresponding adjacent column of the first memristor array according to the adjacent bit data of the preset check polynomial coefficient so as to carry out exclusive OR operation of the current round; wherein, when the current round is 1, the target column is the first column;

A first result updating sub-module, configured to update data stored in the first memristor array according to a result of the exclusive-or operation of the current round;

the first iteration submodule is used for adding 1 to the current round and adding 1 to the column number corresponding to the target column, and returning to the first voltage input submodule;

and the first ending submodule is used for acquiring the data stored in the position of the blank check code when the current round reaches the preset round, and determining the data stored in the position of the blank check code as the redundancy check code of the original data to be transmitted.

Optionally, the apparatus further comprises:

and the data writing module to be transmitted is used for storing the data to be transmitted into the third memristor array.

Optionally, the data writing module to be sent is specifically configured to control an input voltage of the third memristor array according to each bit of data of the data to be sent, so as to store the data to be sent into the third memristor array.

Optionally, the apparatus further comprises:

the original data acquisition module is used for acquiring original data to be transmitted from the third memristor array.

Optionally, the apparatus further comprises:

And the redundancy check code adding module is used for storing the redundancy check code into the tail of the original data to be transmitted, which corresponds to the third memristor array.

Referring to fig. 11, there is shown a block diagram of another cyclic redundancy check processing apparatus provided in an embodiment of the present application, where the cyclic redundancy check processing apparatus is applied to a receiving end, and corresponds to the foregoing embodiment of the cyclic redundancy check processing method applied to the receiving end, the apparatus may include the following modules:

A second data writing module 1101, configured to write each bit of data in data to be received into the first memristor array by columns, where the data to be received includes original data to be received and a redundancy check code of a first preset bit number;

the second data operation module 1102 is configured to control an input voltage of the first memristor array according to a preset check polynomial coefficient, so as to perform multiple exclusive-or operations, and obtain a cyclic redundancy check result;

a check result determining module 1103 is configured to determine whether to receive the original data to be received according to the cyclic redundancy check result.

Optionally, the second data writing module 1101 is specifically configured to write the highest-order data of the data to be received into memristors of the first column of the first memristor array, and write the adjacent-order data of the data to be received into memristors of the adjacent column of the first memristor array.

Optionally, the second data writing module 1101 is specifically configured to write the highest data of the data to be received into memristors in a first column of the first memristor whole column, and write the adjacent bit data of the data to be received into memristors in an adjacent column of the first memristor array, where the data to be received is diagonally arranged in the first memristor array.

Optionally, the preset check polynomial coefficient is stored in a second memristor array, and the second data operation module 1102 includes:

and the first verification result determining submodule is used for controlling the input voltage of the first memristor array according to the preset verification polynomial coefficient so as to perform multiple exclusive OR operations and obtain a cyclic redundancy verification result.

Optionally, the second data operation module 1102 includes:

the second voltage input sub-module is used for controlling the input voltage of the corresponding memristor in the target column of the first memristor array according to the highest bit data of the preset check polynomial coefficient, and controlling the input voltage of the memristor in the corresponding adjacent column of the first memristor array according to the adjacent bit data of the preset check polynomial coefficient so as to perform exclusive OR operation of the current round; wherein, when the current round is 1, the target column is the first column;

a second result updating sub-module, configured to update data stored in the first memristor array according to a result of the exclusive-or operation of the current round;

The second iteration submodule is used for adding 1 to the current round and adding 1 to the column number corresponding to the target column, and returning to the second voltage input submodule;

and the second ending submodule is used for acquiring the data stored in the position of the data to be received when the current round reaches the preset round, and determining the data stored in the position of the data to be received as a cyclic redundancy check result.

Optionally, the verification result determining module 1103 includes:

and the receiving sub-module is used for determining that the original data to be received in the data to be received is correct when the cyclic redundancy check result is 0, and receiving the original data to be received.

Optionally, the receiving sub-module includes:

and the data extraction unit extracts data with a second preset bit number from the data to be received from left to right, and determines the data as the original data to be received, wherein the second preset bit number is equal to the difference between the bit number of the data to be received and the first preset bit number.

For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.

Referring to fig. 7, a circuit schematic diagram of a cyclic redundancy check processing circuit in an example of the present application is shown, the circuit including a first storage unit and a second storage unit respectively connected to an operation unit;

The operation unit comprises a first memristor array, a first word line controller, a first bit line controller, a first analog-to-digital conversion module and a control circuit module, wherein the first word line controller, the first bit line controller and the first analog-to-digital conversion module are respectively connected with the first memristor array, the control circuit module is connected with the first analog-to-digital conversion module, the first word line controller is used for controlling gating of word lines in the first memristor array, the first bit line controller is used for controlling gating of bit lines in the first memristor array, the first analog-to-digital conversion module is used for converting analog values output by the first memristor array into digital values, the control circuit module is used for reading to-be-transmitted original data stored by the third memristor array, writing each bit of to-be-transmitted original data into the first memristor array according to preset check multinomial coefficients stored by the second memristor array, and controlling the first memristor array to carry out redundancy code transmission operation on the first memristor array by controlling the first word line controller and the first bit line controller.

The process that the control circuit module reads the original data to be sent stored in the third memristor array and writes the original data to be sent into the first memristor array may refer to the description of the foregoing step 101, and the control circuit module controls the input voltage of the first memristor array by controlling the first word line controller and the first bit line controller according to the preset check polynomial coefficient stored in the second memristor array, so that the first memristor array performs multiple exclusive-or operation, and the redundant check code for generating the original data to be sent may refer to the description of the foregoing step 102, which is not repeated herein.

It should be noted that, the number, the rows and the columns of memristors in the first memristor array, the second memristor array and the third memristor array may be set according to actual requirements, for example, the number of rows and the number of columns of the first memristor array may be equal to the sum of the number of bits of the original data to be sent and the number of bits of the redundancy check code. The number of rows and columns of the second memristor array may be equal to the number of bits of the redundancy check plus 1. The number of columns of the third memristor array may be equal to a sum of the number of bits of the original data to be transmitted and the number of bits of the redundancy check code, and the number of rows may be set according to the number of original data to be transmitted that is actually required to be stored.

According to the cyclic redundancy check processing circuit, through utilizing the memory integrated characteristic of the memristor array and the capability of exclusive OR calculation, the operation of a cyclic redundancy check algorithm is completed in the memristor array, when the cyclic redundancy check processing circuit is applied to a data sending end or a data receiving end, data can be sent back to a register without being sent to a CPU for calculation of the cyclic redundancy check code, therefore, data carrying can be reduced, further the requirement on memory access bandwidth can be reduced, meanwhile, the efficiency of cyclic redundancy check on the data is improved, and processing power consumption is reduced.

The embodiment of the application also discloses an electronic device, which comprises a processor, a memory and a computer program stored on the memory and capable of running on the processor, wherein the computer program realizes the steps of the cyclic redundancy check processing method when being executed by the processor.

Embodiments of the present application also disclose a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the cyclic redundancy check processing method as described above.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

Embodiments of the present application may relate to the use of user data, and in practical applications, user-specific personal data may be used in the schemes described herein within the scope allowed by applicable laws and regulations under conditions that meet applicable legal and regulatory requirements of the country where the application is located (e.g., the user explicitly agrees, practical notification to the user, etc.).

It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, the present embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present embodiments have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the present application.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The above detailed description of a cyclic redundancy check processing method and apparatus, a circuit, an electronic device and a medium provided in the present application applies specific examples to illustrate the principles and embodiments of the present application, where the above description of the examples is only used to help understand the method and core idea of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A cyclic redundancy check processing circuit, characterized in that the circuit comprises a first storage unit and a second storage unit which are respectively connected with an operation unit;

the second storage unit comprises a third memristor array, a third word line controller, a third bit line controller and a third analog-to-digital conversion module, wherein the third word line controller, the third bit line controller and the third analog-to-digital conversion module are respectively connected with the third memristor array, the third word line controller is used for controlling gating of word lines in the third memristor array, the third bit line controller is used for controlling gating of bit lines in the third memristor array, the third memristor array is used for storing original data to be sent or data to be received, and the third analog-to-digital conversion module is used for converting analog values output by the third memristor array into digital values;

The operation unit comprises a first memristor array, a first word line controller, a first bit line controller, a first analog-to-digital conversion module and a control circuit module, wherein the first word line controller, the first bit line controller and the first analog-to-digital conversion module are respectively connected with the first memristor array, the first word line controller is used for controlling gating of word lines in the first memristor array, the first bit line controller is used for controlling gating of bit lines in the first memristor array, the first analog-to-digital conversion module is used for converting analog values output by the first memristor array into digital values, the control circuit module is used for reading to-be-transmitted original data or to-be-received data stored by the third memristor array, writing each bit of to-be-transmitted original data or to-be-received data into the first memristor array according to a preset check polynomial coefficient stored by the second memristor array, and generating redundancy code to be transmitted by the first memristor array through controlling the first word line controller and the first memristor array.

2. A cyclic redundancy check processing method applied to a transmitting end including the cyclic redundancy check processing circuit according to claim 1, the method comprising:

3. The method of claim 2, wherein writing each bit of data in the original data to be transmitted into the first memristor array by columns and filling a blank check code of a first preset number of bits at the end of the original data to be transmitted comprises:

4. The method of claim 2, wherein writing each bit of data in the original data to be transmitted into the first memristor array by columns and filling a blank check code of a first preset number of bits at the end of the original data to be transmitted comprises:

5. The method of claim 4, wherein the predetermined check polynomial coefficients are stored in a second memristor array, wherein the controlling the input voltage of the first memristor array according to the predetermined check polynomial coefficients to perform a multiple round exclusive-or operation, and generating a redundancy check code of the original data to be transmitted at the position of the blank check code, comprises:

6. The method of claim 5, wherein controlling the input voltage of the first memristor array according to the preset check polynomial coefficient to perform a multiple round exclusive-or operation, and generating a redundancy check code of the original data to be transmitted at the position of the blank check code, comprises:

7. The method according to claim 2, wherein the method further comprises:

and storing the data to be sent into a third memristor array.

8. The method of claim 7, wherein storing the data to be transmitted in the third memristor array comprises:

and controlling the input voltage of the third memristor array according to each bit of data of the data to be sent so as to store the data to be sent into the third memristor array.

9. The method of claim 2, wherein prior to writing each bit of data in the original data to be transmitted in columns into the first memristor array and filling the end of the original data to be transmitted with a first preset number of bits of blank check code, the method further comprises:

and acquiring the original data to be transmitted from the third memristor array.

10. The method according to claim 9, wherein the method further comprises:

and storing the redundancy check code into the tail of the original data to be transmitted, which corresponds to the third memristor array.

11. A cyclic redundancy check processing method applied to a receiving end including the cyclic redundancy check processing circuit according to claim 1, the method comprising:

12. A cyclic redundancy check processing apparatus for use on a transmitting end including the cyclic redundancy check processing circuit of claim 1, the apparatus comprising:

13. A cyclic redundancy check processing apparatus for use in a receiver comprising the cyclic redundancy check processing circuit of claim 1, said apparatus comprising:

14. An electronic device comprising a processor, a memory and a computer program stored on the memory and capable of running on the processor, which computer program, when executed by the processor, implements the cyclic redundancy check processing method of any one of claims 2-11.

15. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the cyclic redundancy check processing method according to any one of claims 2-11.