CN114333943A - Writing operation method and system of resistive random access memory - Google Patents

Abstract

The embodiment of the invention provides a write operation method and a write operation system of a resistive random access memory, and belongs to the technical field of storage. The method comprises the following steps: acquiring data to be written, and writing the data to be written into each target unit of the memory array based on preset reference time; acquiring the required writing time of each target unit, determining the target unit with the required writing time larger than the preset reference time as a detection unit, and executing the following steps: 1) respectively carrying out self-reading of each detection unit; 2) determining whether a detection unit with a storage error exists in each detection unit according to a self-reading result, and acquiring an error bit of the detection unit with the storage error; 3) rewriting data into the detection unit with storage error according to the error bit; and repeatedly executing the steps 1) -3) until the detection unit with the storage error is determined to be not existed. The scheme of the invention shortens the writing time of the whole resistive random access memory system and improves the writing efficiency.

Description

Writing operation method and system of resistive random access memory

Technical Field

The invention relates to the technical field of storage, in particular to a write operation method and a write operation system of a resistive random access memory.

Background

The resistive random access memory is increasingly favored by a memory system because of the advantages of simple structure, compatibility with the existing CMOS process, high scalability, multi-value storage, easy 3D integration and the like. When the memory is written, voltages with different polarities are applied to the two polar plates of the memristor, and the memristor can be switched between different states.

However, due to the limitation of the process and the use environment, the process properties of the resistive random access memory devices have large fluctuation, for write operation, the write operation success time of different resistive random access memory device units is inconsistent, the write time difference between the unit with the shortest write time and the unit with the longest write time can reach more than two orders of magnitude, and the overall trend is that the longer the write operation time is, the higher the write operation success probability is. When the writing time is long, the speed of increasing the operation success probability is reduced along with the increase of the writing time, so that each resistive random access memory has a required writing time, and if the writing time is lower than the required writing time, a fault is easily generated in the writing process.

In the existing writing method, the longest unit writing time is taken as a reference, that is, the writing time of all the resistive random access memories needs to meet the longest unit writing time, so that the whole writing time is extremely long, and the writing efficiency is low. Based on this, it is necessary to create a new writing operation method of the resistive random access memory.

Disclosure of Invention

The invention aims to provide a writing operation method and a writing operation system of a resistive random access memory, which are used for at least solving the problems of long writing time and low writing efficiency of the conventional resistive random access memory.

In order to achieve the above object, a first aspect of the present invention provides a write operation method of a resistive random access memory, the method including: acquiring data to be written, and writing the data to be written into each target unit of the memory array based on preset reference time; acquiring the required writing time of each target unit, determining the target unit with the required writing time larger than the preset reference time as a detection unit, and executing the following steps: 1) respectively carrying out self-reading of each detection unit; 2) determining whether a detection unit with a storage error exists in each detection unit according to a self-reading result, and acquiring an error bit of the detection unit with the storage error; 3) rewriting data into the detection unit with storage error according to the error bit; and repeatedly executing the steps 1) -3) until the detection unit with the storage error is determined to be not existed.

Optionally, the data to be written includes: a data body and a write check bit; the method further comprises the following steps: and carrying out ECC (error correction code) encoding on the data to be written to obtain the data body and the write check bit.

Optionally, the method further includes: acquiring preset reference time, including: respectively simulating the required writing time of each target unit of the memory array, and drawing a time distribution curve of each required writing time; filtering out the required writing time exceeding the deviation threshold on the time distribution curve; and selecting the truncation requirement writing time on the filtered time distribution curve as the preset reference time.

Optionally, in step 1), performing self-reading of each detection unit respectively includes: for each detection unit: positioning the position of the detection unit, and providing a required reading voltage corresponding to the detection unit for data self-reading of the detection unit; and carrying out decoding operation on the self-read data to obtain a read data body and a corresponding decoding check bit.

Optionally, in step 2), determining whether there is a detection unit with a storage error in each detection unit according to the self-reading result, including: and comparing the decoding check bit and the writing check bit of the detection unit, and determining the detection unit with the inconsistent decoding check bit and writing check bit as a detection unit of the storage error.

Optionally, in step 2), obtaining the error bit of the detection unit storing the error includes: and determining the error bit of the detection unit for storing the error according to the difference relation between the decoding check bit and the writing check bit.

Optionally, in step 3), the rewriting data to the detection unit with storage error according to the error bit includes: comparing the error bit with a preset correct bit, and obtaining a correction scheme for correcting the error bit to the preset correct bit according to the comparison result; and rewriting the corresponding detection line according to the write bit indicated by the correction scheme.

Optionally, the method further includes: before performing step 3): acquiring a real-time operation load of a storage system; if the real-time operation load is larger than or equal to the preset safe operation load, keeping the write circuit locked, and forbidding data rewriting; otherwise, the open write circuit rewrites data to the detection unit with the storage error.

Optionally, the method further includes: if the detection unit without the storage error is determined within the preset repetition frequency range of the steps 1) -3), outputting storage completion information; otherwise, alarm information containing information of the detection unit with the storage error is output.

A second aspect of the present invention provides a write operation system of a resistive random access memory, the system including: the acquisition unit is used for acquiring data to be written and acquiring the required writing time of each target unit; a processing unit to: writing the data to be written into each target unit of the memory array based on preset reference time; determining a target unit with the required writing time larger than the preset reference time as a detection unit; the self-reading unit is used for respectively carrying out self-reading of each detection unit; the processing unit is further to: determining whether a detection unit with a storage error exists in each detection unit according to a self-reading result, and acquiring an error bit of the detection unit with the storage error; and rewriting data to the detection unit storing the error according to the error bit.

Optionally, the acquisition unit is further configured to acquire a real-time operation load of the storage system; the processing unit is also used for judging whether the real-time operation load of the storage system is greater than the preset safe operation load; if the real-time operation load is larger than or equal to the preset safe operation load, keeping the write circuit locked, and forbidding data rewriting; otherwise, the open write circuit rewrites data to the detection unit with the storage error.

In another aspect, the present invention provides a computer-readable storage medium having instructions stored thereon, which, when run on a computer, cause the computer to perform the above-described method of writing the resistive random access memory.

According to the technical scheme, the writing time of the target row with extremely long writing time is eliminated by comparing the required writing time of each target row, and the system is written on the basis of accurate writing of most target rows on the premise of operating a certain fault tolerance rate. That is, the writing time of this system is based not on the longest writing time but on the writing time with the widest coverage. And then, the target line with the writing error is positioned through data self-reading, and is correspondingly written again, so that the writing time of the whole resistive random access memory system is shortened, and the writing efficiency is improved.

Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:

fig. 1 is a flowchart illustrating steps of a write operation method of a resistive random access memory according to an embodiment of the present invention;

FIG. 2 is a diagram of a data writing procedure provided in accordance with one embodiment of the present invention;

fig. 3 is a system configuration diagram of a write operation system of a resistive random access memory according to an embodiment of the present invention.

Description of the reference numerals

10-an acquisition unit; 20-a processing unit; 30-self-reading unit.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

A Resistive Random Access Memory (RRAM) is a novel Memory based on the operation principle of a memristor. The resistive random access memory has the advantages of simple structure, compatibility with the existing CMOS process, high micro-shrinkage, multi-value storage, easiness in 3D integration and the like. When the memory is written, voltages with different polarities are applied to the two polar plates of the memristor, and the memristor can be switched between different states. The change of the resistance-change layer from the low resistance state to the high resistance state is called RESET operation (RESET), and the change from the high resistance state to the low resistance state is called SET operation (SET). In addition, a high voltage operation greater than the set voltage is required to activate the RRAM before the ReRAM is normally programmed, and this operation is called a Forming operation (Forming). For example, in a SET operation, when a large voltage is applied to the upper plate of the memristor and the lower plate is grounded, a "conductive filament" is generated inside the memristor, a conductive channel of electrons is generated inside the memristor, so that a current passes through, and the memristor exhibits a Low Resistance State (LRS) characteristic. However, due to the limitation of the process and the use environment, the process properties of the resistive random access memory devices greatly fluctuate. For writing operation, writing operation of different resistive random access memory units is not consistent when used successfully, the difference between the writing time of the unit with the shortest time and the writing time of the unit with the longest time can reach more than two orders of magnitude, and the overall trend is that the longer the writing operation time is, the higher the writing operation success probability is. When the write time is long, the speed of increasing the probability of successful operation becomes slower with the increase of the write time, and if a system with high fault tolerance rate can be designed, the write time can be reduced by half an order of magnitude. In order to ensure the write success probability, the existing write operation needs to ensure that the storage cells corresponding to all bits of one datum are stored correctly respectively, i.e. the write time depends on the slowest cell. And the writing time of the longest unit is taken as a reference, and the total writing operation time of the resistive random access memory array is seriously increased. In addition, the mismatch of the write operation will result in a smaller sensing margin and a large amount of time consumption, thereby compromising output reliability. The invention provides a method for improving the writing operation speed of a resistive random access memory by adopting an error correcting code, which selects proper rather than longest memory cell writing time as a reference, and can correct errors through an error correcting code encoding and decoding circuit if a slower memory cell writes errors under a shorter writing continuous potential. The system adopts the error correcting code, has certain fault-tolerant rate, ensures the accuracy of data, and writes the corrected data into the storage array when the system is idle, thereby improving the writing speed and reducing the writing power consumption. The invention can improve the problem of low speed of the current writing circuit of the resistive random access memory and improve the reliability of data storage of the resistive random access memory.

Fig. 3 is a system configuration diagram of a write operation system of a resistive random access memory according to an embodiment of the present invention. As shown in fig. 3, an embodiment of the present invention provides a write operation system of a resistive random access memory, where the system includes: the acquisition unit 10 is used for acquiring data to be written and acquiring the required writing time of each target unit; a processing unit 20 for: writing the data to be written into each target unit of the memory array based on preset reference time; determining a target unit with the required writing time larger than the preset reference time as a detection unit; a self-reading unit 30 for performing self-reading of data in each detection unit; the processing unit 20 is further configured to: determining whether a detection unit with a storage error exists in the detection unit according to the self-reading result, and acquiring an error bit of the detection unit with the storage error; and rewriting data to the detection unit storing the error according to the error bit.

Fig. 1 is a flowchart of a method for writing a resistive random access memory according to an embodiment of the present invention. As shown in fig. 1, an embodiment of the present invention provides a write operation method of a resistive random access memory, where the method includes:

step S10: and acquiring data to be written, and writing the data to be written into each target unit of the memory array based on preset reference time.

Specifically, for write operation of the conventional resistive random access memory, write operations of different resistive random access memory cells are not consistent when used successfully, the write time difference between the shortest cell used and the longest cell used can reach more than two orders of magnitude, and the overall trend is that the longer the write operation time is, the higher the write operation success probability is. In order to ensure the writing success probability, the conventional writing operation needs to ensure that the storage units corresponding to all bits of one datum are respectively stored correctly, namely the writing time depends on the slowest unit, and the total writing time of the resistive random access memory array is seriously increased by taking the longest writing time as a reference. The mismatch of the write operation will result in a smaller sensing margin and a large amount of time consumption, thereby compromising output reliability. The method is to get rid of the mode that the writing time depends on the slowest unit, and the writing time of the proper and longest storage unit is taken as a reference, so that a certain fault tolerance rate is allowed in the writing process, the efficiency of the whole writing is ensured, a small part of storage lines with errors are repaired in a targeted manner, and the whole writing process is not influenced. Therefore, it is necessary to obtain a preset reference time first and then perform writing according to the reference time. Specifically, as shown in fig. 2, the method includes the following steps:

step S101: and acquiring a preset reference time.

Specifically, the preset reference time needs to be constant, and if the preset reference time is too short, only a small part of storage rows exist, and writing can be accurately completed; if the preset reference time is too long, the effect of improving the efficiency is not obvious. Therefore, it is necessary to set a predetermined reference time in a targeted manner according to the characteristics of the resistance change memory array. Namely, on the premise of ensuring that most of the memory lines are accurately stored, the writing time is shortened as much as possible. Preferably, the required write time of each storage target unit is obtained first, and the required write time is the time required for each target unit to complete accurate writing. In a two-dimensional coordinate axis system, the sequence number of a target unit is used as an abscissa, the required writing time is used as an ordinate, and a distribution curve is drawn, so that most of the required writing time range and a small part of the target unit with long required writing time can be known. And after the distribution curve is obtained, calculating a deviation value between the required writing time of each target unit and the distribution curve, if the deviation value is smaller than a preset threshold value, judging that the corresponding target unit belongs to a range for ensuring accurate writing, and if the deviation value is larger than the preset threshold value, judging that the corresponding target unit is a target unit which allows storage errors. The target units with long required writing time are not guaranteed to be accurately stored, and based on the fact that the required writing time is the longest in the accurate writing range, namely the lowest truncation required writing time on the filtered distribution curve is selected as the preset reference time. For example, a plurality of target units with the required write time greater than 80ns are filtered out, and the longest write time among the reserved write times is 80ns, so that the truncation time is the final reference write time. In the conventional writing method, the overall writing time must be greater than 80ns based on the longest writing time, and with the method, the overall writing time is equal to 80ns when the selected reference time is 80ns, which is faster than the conventional writing method.

Step S102: and carrying out data writing.

Specifically, the resistive random access memory array structure comprises a power line, a bit line, a word line and a resistive random access memory unit. The storage matrix is a main body for storing information and is formed by arranging a plurality of storage units, wherein each storage unit internally comprises a plurality of storage elements, each storage element stores a bit of binary code (0 or 1), and the plurality of storage units form a word (also called an information unit). The address decoder has n address input lines A0An-1, 2n decode output lines W0W2n-1, each of which is called a "word line" and corresponds to a "word" in the memory matrix. Thus, whenever a given set of input addresses is given, only one output word line Wi of the decoder is selected, which word line can find a corresponding "word" in the memory matrix and supply the m bits of information Dm-1D0 in the word to the output buffer. Each data output line Di that reads Dm-1D0 is also referred to as a "bit line" and the number of bits of information in each word is referred to as the "word length". For SET operation, controlling a word line to gate a row required to be selected, applying a write voltage to a bit line of a target resistive random access memory, and setting a source line of a memory unit to be 0; for the RESET operation, the word line is controlled to gate the row required to be selected, a write voltage is applied to the source line of the target resistive random access memory unit, and the bit line is set to be 0. The above operations are all completed within a preset reference time.

Step S20: and acquiring the required writing time of each target unit, and determining the target unit with the required writing time larger than the preset reference time as a detection unit.

Specifically, when writing is performed, it cannot be guaranteed that target units requiring a writing time longer than a preset reference time are completely and accurately written, that is, after writing is completed, writing errors may exist in the target units. Although a certain error rate exists, most target units have accurate storage results, and the overall writing speed is improved. And then, error correction needs to be carried out on the target units with write errors, so that double guarantee of write efficiency and write accuracy is realized. Therefore, the required writing time of each target unit is firstly obtained and compared with the preset reference time, and possible writing error target units with the required writing time larger than the preset reference time are screened out to be used as detection units. Then, targeted error detection and correction are performed subsequently based on these detection units.

Step S30: and respectively carrying out data self-reading of each detection unit, determining whether the detection unit with the storage error exists in each detection unit according to the self-reading result, and acquiring the error bit of the detection unit with the error.

Specifically, in the writing process, data is written according to requirements, and resistance states of the resistive random access memory at different moments are different. For example, if the data to be written is "0", the memory needs to be in a high resistance state, and if the data is written in a low resistance state due to the shortened time, an error occurs in the corresponding bit. And in the coded data, the data characteristics are associated with check bits, and if an odd number of data bits including the check bits are changed in the transmission process, the parity bits will be in error to indicate that an error occurs in the transmission process. For parity checking of a memory, it is assumed that from the bit concept, a bit (bit) is the smallest unit in the memory, also called "bit", and only two states thereof are represented by 1 and 0, respectively. We call 8 consecutive bits a byte. Each byte of the non-parity memory has only 8 bits, and if a bit of the non-parity memory stores an erroneous value, the corresponding data stored therein is changed, which may cause an error in the application program. In addition to each byte (8 bits) in the parity, an additional bit is added for error detection. For example, a byte stores a value (1, 0, 1, 0), and each bit is added up (1+0+0+1+1+1+ 0 equals 5). If the result is an odd number, the parity bit is defined as 1, otherwise it is 0. When the CPU returns to read the stored data, it will add the data stored in the previous 8 bits again, and the calculation result is consistent with the check bit. Therefore, the storage data needs to be read, and the storage data decoding operation is performed through the decoding circuit to obtain the storage data and the decoding check bits. And comparing the decoding check bit with the writing check bit, wherein if the decoding check bit and the writing check bit are different, the difference of '0' or '1' is shown, namely the data bit stored in the memory is '0', and the corresponding data bit is '1' due to the error writing. And comparing the decoding check bit and the writing check bit of each detection unit to judge whether a storage error exists. And extracts the detection cells where the storage error exists as the detection cells for the final rewriting, and then in these detection cells for the rewriting, it is necessary to locate the bit of the error. Parity errors occur in the bits, and after the positions of the bits are located, error correction can be performed efficiently and specifically.

The method carries out error correction based on ECC coding, for example, 2 bits of data bits and the check bit of the last bit, and the check algorithm is directly XOR operation. If a bit, which may be 001,010 or 100, is changed, neither check can be passed. If 2 bits are changed, 011, the rule can be checked. I.e., 2-bit errors, this method cannot check for errors. The application is 4 bits of information, and the code is 7 bits, namely Hamming (7,4) code. Through the actual value of the check code, the position of the error code can be known, namely, the position of the error code can be positioned after the error occurs in the decoding check bit relative to the writing check bit.

Step S40: and rewriting the detection unit with the error according to the error bit until the writing result has no storage error.

Specifically, after the detection units with the wrong storage are screened out, the detection units need to be corrected in error, the wrong bits of the detection units are correspondingly obtained, the written check bits are preset ideal check bits which limit the identity of the written data, and preset correct bits exist correspondingly. The decoding check bit is the check bit of the actual stored data, when the storage has an error, the decoding check bit of the stored data is different from the ideal check bit thereof, namely the writing check bit, and the error bit is obtained by positioning based on the difference of the decoding check bit and the ideal check bit. And performing write data recovery according to the error bit, namely generating a recovery scheme from actual stored data to write data. Preferably, the operation load of the memory module caused by repeated writing is avoided, so that the actual operation requirement of the memory unit is influenced. And rewriting the corresponding detection unit under the condition that the storage unit is idle. When the memory unit executes a high-load read-write task, if the detection unit needs to be synchronously rewritten, the memory unit is bound to operate at a higher load, which affects the service life of the memory unit on one hand and the ongoing read-write task on the other hand. Therefore, after the rewrite scheme is generated, the real-time operation load of the storage system needs to be judged, and the current operation load is compared with the preset safe operation load. And if the current operation load is greater than the preset safe operation load, the current operation load of the storage system is too high, and the detection unit is not suitable for rewriting. The write circuit of the corresponding detection unit is locked to avoid the error write of the corresponding detection unit, which results in the increase of the load of the storage unit. And if the current operation load is smaller than the preset safe operation load and indicates that the current storage unit is in a relatively idle state, opening a write circuit of the corresponding detection unit, correcting errors based on the generated write scheme, and performing secondary write. After the second writing is completed, the determination of the written data in step S30 is repeated to determine whether the corresponding detection cell still has an error. And the judgment is to judge whether the decoding check bit after the second writing is different from the initial writing check bit based on the comparison between the decoding check bit after the second writing and the initial writing check bit, if the decoding check bit still has the difference, the second writing still has errors, the third writing is needed, and then the decoding check bit written for the third time is compared with the initial writing check bit. And repeating the steps until the corresponding detection unit has no storage error, and outputting a signal with correct storage.

Preferably, the predetermined number of times of repeated writing, for example, the predetermined number of times of repeated writing is 5 times, after the 5 th repeated writing is completed, the 5 th decoded check bit and the written check bit are compared, and if a difference still exists between the decoded check bit and the written check bit, it may be because the writing circuit or the resistive random access memory itself has a failure, and even if the repeated number of times is more, correct writing cannot be performed. And outputting alarm information instead of the 6 th repeated writing, reminding relevant personnel of troubleshooting the resistive random access memory, wherein the alarm information comprises fault detection unit information, providing a basis for the relevant personnel to perform targeted troubleshooting, and improving troubleshooting efficiency.

In the embodiment of the invention, the proper and longest memory cell writing time is selected as a reference, and if the slower memory cell writes errors under the shorter writing continuous potential, the error correction can be carried out by an error correction code encoding and decoding circuit. The system adopts the error correcting code, has certain fault-tolerant rate, ensures the accuracy of data, and writes the corrected data into the storage array when the system is idle, thereby improving the writing speed and reducing the writing power consumption. The invention can improve the problem of low speed of the current writing circuit of the resistive random access memory and improve the reliability of data storage of the resistive random access memory.

In one possible embodiment, an error correction code is used to improve the writing speed of the resistive random access memory 200. The four resistive random access memories are Resistive Random Access Memories (RRAM) 201, 202, 203 and 204 are Resistive Random Access Memories (RRAM), each RRAM stores 1-bit numerical value in a high resistance state or a low resistance state, and in this embodiment, the four RRAM are a group of memories storing one data (one data occupies 4 bits in this embodiment); 205. 206, 207 and 208 are transistors, wherein 201 and 205, 202 and 206, 203 and 207, 204 and 208 respectively form a 1T1R (1 transistor and one resistive random access memory) memory cell structure. In this embodiment, for the conventional write operation, taking the written data as 1001 as an example, and 203 as one resistive random access memory with the longest write time, the conventional write operation will take the write time of 203 as the total write time, and in the actual operation, the write unit with the longest write time in the entire resistive random access memory array will be taken as the reference write time. Since the write operation is performed for a long enough time, the four memories are all successfully written after the write operation is completed, and since 203 should write "0", the 203 resistive random access memory will be in a High Resistance State (HRS). For this embodiment of the present invention, after using the error correction code, an appropriate write time may be selected as the reference write time instead of the write time of the cell that takes the longest write operation. The method comprises the steps of firstly, respectively obtaining the required writing time of each resistive random access memory, drawing a writing time distribution curve, and then determining the preset reference time. Among them, 209 is a resistance change memory cell whose write operation is the slowest, and since an error correction code is used, it is not necessary to take the write operation time thereof as a reference write time. Due to the fact that the writing time is shortened, the writing speed is improved, errors can occur in the writing operation with a certain probability 209, the written data of 209 is '0', and the written data should be in a high-resistance state, but the written data is in a low-resistance state (LRS) due to insufficient writing time. For the write-in error caused by insufficient write-in time, the ECC decoding circuit finishes judgment and error correction operation, finds out the data bit with the stored error, and writes the correct result into the resistive random access memory array when the system is idle.

The invention also provides a computer-readable storage medium, which stores instructions that, when executed on a computer, cause the computer to execute the method for writing the resistive random access memory.

Those skilled in the art will appreciate that all or part of the steps in the method for implementing the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.

In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.

Claims (12)

1. A write operation method of a resistive random access memory, the method comprising:

acquiring data to be written, and writing the data to be written into each target unit of the memory array based on preset reference time;

acquiring the required writing time of each target unit, determining the target unit with the required writing time larger than the preset reference time as a detection unit, and executing the following steps:

1) respectively carrying out data self-reading of each detection unit;

2) determining whether a detection unit with a storage error exists in each detection unit according to a self-reading result, and acquiring an error bit of the detection unit with the storage error;

3) rewriting data into the detection unit with storage error according to the error bit;

and repeatedly executing the steps 1) -3) until the detection unit with the storage error is determined to be not existed.

2. The method of claim 1, wherein the data to be written comprises:

a data body and a write check bit;

the method further comprises the following steps:

and carrying out ECC (error correction code) encoding on the data to be written to obtain the data body and the write check bit.

3. The method of claim 2, further comprising:

acquiring preset reference time, including:

respectively simulating the required writing time of each target unit of the memory array, and drawing a time distribution curve of each required writing time;

filtering out the required writing time exceeding the deviation threshold on the time distribution curve;

and selecting the truncation requirement writing time on the filtered time distribution curve as the preset reference time.

4. The method according to claim 3, wherein the step 1) of performing self-reading of data of each detection unit respectively comprises:

for each detection unit:

positioning the position of the detection unit, and providing a required reading voltage corresponding to the detection unit for data self-reading of the detection unit;

and carrying out decoding operation on the self-read data to obtain a read data body and a corresponding decoding check bit.

5. The method of claim 4, wherein the step 2) of determining whether the detection unit with the storage error exists in each detection unit according to the self-reading result comprises:

and comparing the decoding check bit and the writing check bit of the detection unit, and determining the detection unit with the inconsistent decoding check bit and writing check bit as a detection unit of the storage error.

6. The method of claim 5, wherein the step 2) of obtaining the error bits of the detection unit storing the error comprises:

and determining the error bit of the detection unit for storing the error according to the difference relation between the decoding check bit and the writing check bit.

7. The method according to claim 6, wherein in step 3), the rewriting data into the detection unit storing errors according to the error bits comprises:

comparing the error bit with a preset correct bit, and obtaining a correction scheme for correcting the error bit to the preset correct bit according to the comparison result;

and rewriting the corresponding detection line according to the write bit indicated by the correction scheme.

8. The method of claim 1, further comprising: before performing step 3):

acquiring a real-time operation load of a storage system;

if the real-time operation load is larger than or equal to the preset safe operation load, keeping the write circuit locked, and forbidding data rewriting; otherwise, the open write circuit rewrites data to the detection unit with the storage error.

9. The method of claim 1, further comprising:

if the detection unit without the storage error is determined within the preset repetition frequency range of the steps 1) -3), outputting storage completion information;

otherwise, alarm information containing information of the detection unit with the storage error is output.

10. A write operation system of a resistive random access memory, the system comprising:

the acquisition unit is used for acquiring data to be written and acquiring the required writing time of each target unit;

a processing unit to:

writing the data to be written into each target unit of the memory array based on preset reference time; determining a target unit with the required writing time larger than the preset reference time as a detection unit;

the self-reading unit is used for respectively carrying out self-reading of each detection unit;

the processing unit is further to:

determining whether a detection unit with a storage error exists in each detection unit according to a self-reading result, and acquiring an error bit of the detection unit with the storage error;

and rewriting data to the detection unit storing the error according to the error bit.

11. The system of claim 10, wherein the acquisition unit is further configured to obtain a real-time operating load of the storage system;

the processing unit is also used for judging whether the real-time operation load of the storage system is greater than the preset safe operation load; if the real-time operation load is larger than or equal to the preset safe operation load, keeping the write circuit locked, and forbidding data rewriting; otherwise, the open write circuit rewrites data to the detection unit with the storage error.

12. A computer-readable storage medium having instructions stored thereon, which when executed on a computer, cause the computer to perform the method of write operation of a resistive-switching memory according to any one of claims 1 to 10.

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