CN112182495B - Binary domain matrix operation circuit based on memristor - Google Patents
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Abstract
The application discloses a binary domain matrix operation circuit based on a memristor, which belongs to the field of microelectronic devices, and comprises: the processor is used for acquiring a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, generating a switch control signal based on a processing algorithm, wherein the processing algorithm is an encoding algorithm or a decoding algorithm; a pulse generator coupled to the processor for generating a logic level signal based on the values of the elements in the binary data sequence; the switch array is used for enabling the connected processor and the pulse generator to be correspondingly switched on under the action of a switch control signal; the memristor array is connected with the processor, the pulse generator and the switch array, and is used for receiving the written binary check matrix and outputting a target sequence under the actions of the accessed direct current pulse signal and the logic level signal. According to the scheme, a large amount of data is not required to be moved in a memory and an arithmetic unit in the calculation process, so that the calculation rate can be improved, the energy consumption can be reduced, and the time delay can be reduced.
Description
Technical Field
The invention belongs to the field of microelectronic devices, and particularly relates to a binary domain matrix operation circuit based on a memristor.
Background
In the processing, transmission and storage of information, a large number of encoding and decoding operations and error correction operations exist, the nature and core of the encoding and decoding operations and the matrix vector multiplication of binary fields and the solution of non-homogeneous linear equation sets are adopted, each encoding mode has a generating matrix and a check matrix, a signal sequence is a binary vector, the encoding process can be completed through the multiplication of the generating matrix and an original signal sequence, and a new binary vector is obtained through operation, and the binary vector is the information sequence after encoding.
When decoding, the coded sequence is multiplied by a check matrix, check and error correction are performed first, and decoding can be performed after the error correction is completed. The decoding process is the process of solving the equation set, the coding sequence and the generating matrix form an augmentation matrix, and the augmentation matrix is subjected to Gaussian elimination, so that the original signal can be solved.
When matrix vector multiplication operation and non-homogeneous equation set solving in encoding and decoding operations are performed in a CPU, a great amount of time, energy consumption and hardware overhead are often required, and especially when the signal sequence scale is large, the delay is serious.
Disclosure of Invention
Aiming at the defects or improvement demands of the prior art, the invention provides a binary domain matrix operation circuit based on a memristor, which aims to rapidly carry out coding operation and decoding operation, improve operation efficiency, reduce memory and reduce delay, thereby solving the technical problems of low coding operation and decoding operation efficiency, large occupied memory and serious time delay in the prior art.
To achieve the above object, according to one aspect of the present invention, there is provided a memristor-based binary domain matrix operation circuit including:
The processor is used for acquiring a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, and generating a switch control signal based on a processing algorithm, wherein the processing algorithm is an encoding algorithm or a decoding algorithm;
a pulse generator, connected with the processor, for generating a logic level signal based on the element values in the binary data sequence;
The switch array is connected with the processor and the pulse generator and is used for conducting the corresponding switch under the action of the switch control signal so as to conduct the link of the direct current pulse signal output by the processor and the link of the logic level signal output by the pulse generator;
The memristor array is correspondingly connected with the processor, the pulse generator and the switch array, is used for receiving the binary check matrix written by the processor and outputting a target sequence under the action of the accessed direct current pulse signal and the logic level signal,
When the processing algorithm is a coding algorithm, the target sequence is a coding sequence corresponding to the binary data sequence; when the processing algorithm is a decoding algorithm, the target sequence decodes the corresponding original code sequence for the binary data sequence.
In one embodiment, when the memristor-based binary domain matrix arithmetic circuit is used to execute an encoding algorithm of the binary data sequence,
The pulse generator is used for generating a logic level signal according to the element value in the original code sequence x T, outputting a low level when the element 0 and outputting a high level when the element 1;
The memristor array is used for receiving the check matrix A written by the processor, wherein the element 0 is written into a high-resistance state, and the element 1 is written into a low-resistance state; the positive electrode of the memristor corresponding to the on switch is connected with the logic level signal, the negative electrode of the memristor corresponding to the on switch is connected with the direct current pulse signal so as to output the target sequence, and the target sequence is a coding sequence Ax T of the binary data sequence x T.
In one embodiment, when the memristor-based binary domain matrix arithmetic circuit is used to perform a decoding algorithm for the binary data sequence,
The memristor array is used for storing an augmentation matrix composed of a check matrix A and a coding sequence y, the word lines of all memristors in the memristor array are connected with the logic level signals to execute exclusive OR operation between rows of the memristor array so as to output the target sequence x T, and the target sequence decodes a corresponding original code sequence x T for the coding sequence y, wherein x T is a solution of a non-homogeneous equation Ax T =y.
In one embodiment, the processor is further configured to,
When the elements in the binary check matrix and the elements in the binary data sequence are subjected to multiplication operation, the switch control signal is set as a conduction signal;
and when the elements in the binary check matrix and the elements in the binary data sequence are subjected to addition operation, setting the switch control signals corresponding to the two overlapped elements as conduction signals.
In one embodiment, the switch array comprises:
The row switch array comprises a plurality of row switches, and the row switches are respectively connected with word lines of memristors in the memristor array one by one;
the array of column switches comprises a plurality of column switches, and the plurality of column switches are respectively connected with bit lines of all memristors in the memristor array one by one;
when a row switch and a column switch which are correspondingly connected with any memristor in the memristor array are in a conducting state, any memristor in the memristor array receives the direct-current pulse signal.
In one embodiment, the memristor array is structured as a cross-bar structure, a transistor-memristor cascade structure, a single transistor-multi-memristor cascade structure, or a three-dimensional stacked structure, wherein the memristors are binary devices.
In one embodiment, the memristors in the memristor array are resistive random access memories, phase change memories, self-select transfer moment-magnetic random access memories, NOR Flash devices, or NAND FLASH devices.
In general, the above technical solutions conceived by the present invention, compared with the prior art, comprise the following beneficial effects:
1. Because the check matrix corresponding to the coding algorithm or the decoding algorithm is stored in the memristor array, and the sequence to be coded or decoded is input into the memristor array in a voltage form, the memristor array directly outputs the target sequence without carrying out a large amount of data back and forth in a memory and an arithmetic unit, and compared with the prior art of executing the coding algorithm and the decoding algorithm by using a CPU (Central processing unit) and the like, the calculation rate can be improved, the energy consumption can be reduced, and the time delay can be reduced;
2. as the vector sum matrix of the binary domain is equivalent to multiplication and exclusive OR is equivalent to addition, the binary matrix is stored in the memristor array, and then the binary vector is input into the memristor array in a voltage form, so that the binary domain matrix vector multiplication and binary non-homogeneous equation solution can be rapidly realized.
Drawings
FIG. 1 is a schematic diagram of a memristor-based binary domain matrix operation circuit in accordance with an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of AND logic operation of a single memristor in accordance with an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of an exclusive OR operation of three memristors in an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a memristor array performing AND logic operations in accordance with one embodiment of the present disclosure;
FIG. 5 is a schematic diagram of performing an exclusive OR accumulation operation in bulk in a memristor array in accordance with an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating the operation of solving a system of equations by row exclusive OR in a memristor array in accordance with an embodiment of the present disclosure.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The application provides a binary domain matrix operation circuit based on memristors, which comprises: a processor, a pulse generator, a switch array, and a memristor array. As shown in fig. 1, the processor refers to a combination of a computer system and a read-write control/circuit, and is configured to obtain a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, and generate a switch control signal based on a processing algorithm, where the processing algorithm is an encoding algorithm or a decoding algorithm. The pulse generator is connected with the processor and used for generating a logic level signal based on element values in the binary data sequence, and the switch array is connected with the processor and the pulse generator and used for conducting corresponding switches under the action of a switch control signal so that the processor can control and output a direct current pulse signal and the pulse generator can output the logic level signal to the memristor array; the memristor array is correspondingly connected with the processor, the pulse generator and the switch array, and is used for receiving the binary check matrix written by the processor and outputting a target sequence under the action of the accessed direct current pulse signal and the logic level signal.
Specifically, the processor acquires a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence. That is, the processor acquires the original sequence to be encoded and the corresponding encoding check matrix, or the processor acquires the encoded sequence to be decoded and the corresponding decoding check matrix. The encoding check matrix and the decoding check matrix may be the same or different, and are not limited herein. In one embodiment, the processor is further configured to set the switch control signal to be a conducting signal and transmit the conducting signal to the switch array when the elements in the binary check matrix and the elements in the binary data sequence are multiplied (and operated); when the elements in the binary check matrix and the elements in the binary data sequence are subjected to addition operation (exclusive or operation), the switch control signals corresponding to the two overlapped elements are set as conducting signals and transmitted to the switch array.
Further, the processor controls the pulse generator to generate a voltage sequence according to the element values of the binary data sequence. When the element 0 in the binary data sequence is the corresponding low level in the voltage sequence; when element 1 in the binary data sequence, the corresponding high level in the voltage sequence. The processor writes a resistance state into the memristor array according to the middle element value of the check matrix, and writes a low resistance state into the memristor at the corresponding position when the middle element value of the check matrix is 1; when the element value in the check matrix is 0, writing a high-resistance state into the memristor at the corresponding position. The switch array is conducted or cut off under the action of a switch signal, and memristors in the memristor array can be controlled to participate in work. In one embodiment, a switch array includes: the row switch array comprises a plurality of row switches, and the row switches are respectively connected with word lines of memristors in the memristor array one by one; the array of column switches comprises a plurality of column switches, and the plurality of column switches are respectively connected with bit lines of memristors in the memristor array one by one; when a row switch and a column switch which are correspondingly connected with any memristor in the memristor array are in a conducting state, any memristor in the memristor array receives a direct-current pulse signal.
And finally, inputting a direct current pulse signal and a logic level signal corresponding to the binary data sequence into the memristor array written into the check matrix, so that the memristor at the corresponding position can work, and the memristor array outputs a target sequence. When the processing algorithm is a coding algorithm, the target sequence is a coding sequence corresponding to the binary data sequence; when the processing algorithm is a decoding algorithm, the target sequence is a binary data sequence and decodes the corresponding original code sequence.
In one embodiment, when the memristor-based binary domain matrix arithmetic circuit is used to execute the encoding algorithm of the binary data sequence, the pulse generator is used to generate a logic level signal according to the element value in the original code sequence x T, when the element 0 outputs a low level, and when the element 1 outputs a high level; the memristor array is used for receiving the check matrix A written by the processor, writing the element 0 into a high-resistance state, and writing the element 1 into a low-resistance state; the positive electrode of the memristor corresponding to the on switch is connected with a logic level signal, the negative electrode of the memristor is connected with a direct current pulse signal so as to output a target sequence, and the target sequence is a coding sequence Ax T of a binary data sequence x T.
For example, the procedure for the memristor-based binary domain matrix arithmetic circuit to perform the encoding algorithm of binary data sequence x T (i.e., multiplication of binary matrix a and vector x T) is as follows:
S101, writing a first input variable A into a memristor array, writing a high-resistance state if the first input variable A is 0, and writing a low-resistance state if the first input variable A is 1;
S102, converting a second input variable x T into a corresponding logic level, wherein the logic level is low if 0, the logic level is represented by ground, and the logic level is high if 1, and the logic level is represented by VDD/2;
S103, the logic level x and a VDD pulse are simultaneously applied to the positive electrode and the negative electrode of the device respectively to finish AND operation.
FIG. 2 is a schematic diagram of a memristor implementing logical AND operation in the present disclosure; when the element in A and the element in x T are 0 at the same time, negative pressure larger than the threshold voltage is reduced in the high-resistance state, the resistance state is not changed, the high-resistance state is maintained unchanged, and 0 is output; when a=0 and x T =1, the negative pressure drop smaller than the threshold voltage exists on the high resistance state, the device maintains the high resistance state unchanged, and 0 is output; when a=1 and x T =0, the negative pressure with the amplitude larger than the second threshold voltage is reduced on the low-resistance state, the device is converted from the low-resistance state to the high-resistance state, and 0 is output; when a=1 and x T =1, the negative pressure drop smaller than the second threshold voltage exists on the low-resistance state, the resistance state of the device cannot be changed, the low-resistance state is maintained unchanged, and 1 is output; the above four combinations correspond to logical AND operations.
Additionally, it should be added that the multiplication of the binary matrix a and the vector x T may be:
s201, writing an M multiplied by N matrix A into an array with a corresponding scale;
S202, converting the vector x T into a corresponding logic voltage sequence;
s203, simultaneously applying a voltage sequence to the bit line of the array where A is located, and applying a VDD pulse to the word line;
s204, performing exclusive OR accumulation on the array after the AND operation is performed, wherein the accumulated result is y;
Each exclusive-or operation is divided into two steps, and as shown by the column exclusive-or of fig. 3, the method can simultaneously perform parallel operation on elements in a column. As shown in fig. 4, a voltage vector is applied to the word line of the memristor. The accumulation step is shown in fig. 5, in which the first column and the second column are subjected to first exclusive-or operation to obtain m1, the first column with the intermediate result area is present, the second column and m1 are subjected to exclusive-or operation for the second time to obtain m2, and the second column with the intermediate result area is present until the matrix after the whole and operation is subjected to N-1 exclusive-or accumulation to obtain y.
In one embodiment, when the binary domain matrix operation circuit based on memristors is used for executing a decoding algorithm of a binary data sequence, the memristor array is used for storing an augmentation matrix formed by a check matrix a and a coding sequence y, logic level signals are connected to word lines of all memristors in the memristor array to execute exclusive or operation between rows of the memristor array so as to output a target sequence x T, and the target sequence decodes a corresponding original code sequence x T for the coding sequence y, wherein x T is a solution of a non-homogeneous equation Ax T =y.
For example, the procedure for the memristor-based binary domain matrix arithmetic circuit to perform the decoding algorithm of the binary data sequence x T (i.e., binary domain non-homogeneous linear equation set Ax T =y solving) is as follows:
When performing the binary field matrix vector multiplication operation Ax T =y, the operation steps are as follows:
S301, writing an augmentation matrix A|y of a binary domain non-homogeneous linear equation set to be solved into a memristor array of a corresponding scale;
s302, loading Gao Sixiao-element algorithm programs of a binary domain matrix into a processor connected with the memristor array;
S303, performing gaussian elimination through parallel row xoring, where row xoring refers to an exclusive-or operation between rows, as shown in the middle part of fig. 3.
The Gao Sixiao bits of the binary field are not multiplied, and can be executed in parallel when the exclusive OR between the rows in the array is performed, so that the calculation speed is improved, as shown in fig. 6. The uppermost is an augmentation matrix which consists of ①～④ row vectors, the first step is to execute row exclusive OR on ③ and ④ to obtain two more 1 s in the found coefficients in ⑤,⑤, and the two 1 s are respectively in the first and third positions; continuing to find 1's for both locations at ①～②, xoring the row vectors for 1's greater than 2 (at least 3 1's), reading ① and ②'s word line end current by applying a read voltage to 4 bit lines, if greater than 3, continuing to apply a read voltage to the first and third strips, determining if 1's are present at both locations, finding a satisfactory ①, xoring ① and ⑤ to obtain ⑥, applying a read voltage to four bit lines, reading ⑥'s word line end current, finding only 1's remaining in 4 coefficients, indicating ⑥ has completed the elimination, continuing to determine 1's location, and ⑥'s last element is 1, thus solving for x 4 =1; and continuing to find a row vector with bit 4 being 1 in ①-⑤, applying a read voltage to the bit 4, determining that the fourth bit of ②-④ is 1, performing exclusive or on ⑥ and ②-④ respectively to obtain ⑦,⑧,⑨, reading hamming weights of coefficient vectors to be 1, determining that ⑦,⑧,⑨ is completed, checking whether all solutions are obtained, searching 1 positions of the coefficient vectors in ⑦,⑧,⑨ respectively, wherein x 2,x3,x1 is the last element of the row vector, x 2＝0,x3＝1,x1 =1, x 4 =1 is already solved for 6, and solving is finished.
In one embodiment, the memristor array is structured as a cross-bar structure, a transistor-memristor cascade structure, a single transistor-multi-memristor cascade structure, or a three-dimensional stacked structure, wherein the memristors are binary devices.
In one embodiment, the memristors in the memristor array are resistive random access memories, phase change memories, self-select transfer torque-magnetic random access memories, NOR Flash devices, or NAND FLASH devices.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (5)
1. A memristor-based binary domain matrix arithmetic circuit, comprising:
The processor is used for acquiring a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, and generating a switch control signal based on a processing algorithm, wherein the processing algorithm is an encoding algorithm or a decoding algorithm;
a pulse generator, connected with the processor, for generating a logic level signal based on the element values in the binary data sequence;
The switch array is connected with the processor and the pulse generator and is used for conducting the corresponding switch under the action of the switch control signal so as to conduct the link of the direct current pulse signal output by the processor and the link of the logic level signal output by the pulse generator;
The memristor array is correspondingly connected with the processor, the pulse generator and the switch array, and is used for receiving the binary check matrix written by the processor and outputting a target sequence under the action of the accessed direct current pulse signal and the logic level signal;
When the processing algorithm is a coding algorithm, the target sequence is a coding sequence corresponding to the binary data sequence; when the processing algorithm is a decoding algorithm, the target sequence decodes a corresponding original code sequence for the binary data sequence;
When the memristor-based binary domain matrix operation circuit is used for executing the encoding algorithm of the binary data sequence, the pulse generator is used for generating a logic level signal according to the element value in the original code sequence x T, outputting a low level when the element 0, and outputting a high level when the element 1; the memristor array is used for receiving the check matrix A written by the processor, wherein the element 0 is written into a high-resistance state, and the element 1 is written into a low-resistance state; the positive electrode of the memristor corresponding to the on switch is connected with the logic level signal, the negative electrode of the memristor is connected with the direct current pulse signal so as to output the target sequence, and the target sequence is a coding sequence Ax T of the binary data sequence x T;
When the memristor-based binary domain matrix operation circuit is used for executing the decoding algorithm of the binary data sequence, the memristor array is used for storing an augmentation matrix composed of a check matrix A and a coding sequence y, and after the logic level signals are accessed to word lines of all memristors in the memristor array, exclusive OR operation between rows of the memristor array is executed to output the target sequence x T, wherein the target sequence is a solution of a non-homogeneous equation Ax T =y, and the coding sequence y decodes the corresponding original code sequence x T.
2. The memristor-based binary domain matrix operation circuit of claim 1, wherein the processor is further configured to,
When the elements in the binary check matrix and the elements in the binary data sequence are subjected to multiplication operation, the switch control signal is set as a conduction signal;
and when the elements in the binary check matrix and the elements in the binary data sequence are subjected to addition operation, setting the switch control signals corresponding to the two overlapped elements as conduction signals.
3. The memristor-based binary domain matrix operation circuit of claim 1, wherein the switch array comprises:
The row switch array comprises a plurality of row switches, and the row switches are respectively connected with word lines of memristors in the memristor array one by one;
the array of column switches comprises a plurality of column switches, and the plurality of column switches are respectively connected with bit lines of all memristors in the memristor array one by one;
when a row switch and a column switch which are correspondingly connected with any memristor in the memristor array are in a conducting state, any memristor in the memristor array receives the direct-current pulse signal.
4. The memristor-based binary domain matrix operational circuit of any one of claims 1-3, wherein the memristor array structure is a cross-bar structure, a transistor-memristor cascade structure, a single transistor-multi-memristor cascade structure, or a three-dimensional stacked structure, wherein the memristor is a binary device.
5. The memristor-based binary domain matrix operation circuit of any one of claims 1-3, wherein memristors in the memristor array are resistive random access memories, phase change memories, self-select transfer moment-magnetic random access memories, NOR Flash devices, or NAND FLASH devices.
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