CN112182495A - Binary domain matrix operation circuit based on memristor - Google Patents
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Abstract
The invention discloses a binary domain matrix operation circuit based on a memristor, which belongs to the field of microelectronic devices and comprises the following components: the processor is used for acquiring a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, and generating a switch control signal based on a processing algorithm, wherein the processing algorithm is an encoding algorithm or a decoding algorithm; a pulse generator coupled to the processor for generating a logic level signal based on the value of an element in the binary data sequence; the switch array is used for enabling the corresponding switches of the connected processor and the pulse generator to be conducted under the action of the switch control signal; and the memristor array is connected with the processor, the pulse generator and the switch array, is used for receiving the written binary check matrix, and outputs a target sequence under the action of the accessed direct-current pulse signal and the logic level signal. According to the scheme, a large amount of data do not need to be moved in the memory and the arithmetic unit in the calculation process, the calculation rate can be improved, the energy consumption can be reduced, and the time delay can be reduced.
Description
Technical Field
The invention belongs to the field of microelectronic devices, and particularly relates to a binary domain matrix operation circuit based on a memristor.
Background
In the information processing, transmission and storage, a large amount of encoding and decoding and error correction operations exist, the nature and the core of the encoding and decoding and error correction operations, matrix vector multiplication of a binary domain and the solution of a non-homogeneous linear equation system are adopted, each encoding mode has a generating matrix and a check matrix, a signal sequence is a binary vector, the encoding process can be completed through the multiplication of the generating matrix and an original signal sequence, a new binary vector is obtained through operation, and the binary vector is an information sequence after encoding.
In decoding, the encoded sequence needs to be multiplied by a check matrix, check and error correction are performed first, and decoding can be performed after error correction is completed. The decoding process is the process of solving the equation set, the coding sequence and the generating matrix form an augmentation matrix, and the original signal can be solved by performing Gaussian elimination on the augmentation matrix.
When matrix vector multiplication operation and heterogeneous equation system solution in encoding and decoding operation are performed in a CPU, a large amount of time, energy consumption and hardware overhead are consumed, and particularly when the signal sequence scale is large, the time delay is serious.
Disclosure of Invention
Aiming at the defects or the improvement requirements of the prior art, the invention provides a memristor-based binary domain matrix operation circuit, which aims to quickly perform encoding operation and decoding operation, improve the operation efficiency, reduce the memory and reduce the time delay, thereby solving the technical problems that the encoding operation and the decoding operation efficiency are low and the memory is occupied and the time delay is seriously avoided in the prior art.
To achieve the above object, according to one aspect of the present invention, there is provided a memristor-based binary domain matrix operation circuit, including:
the processor is used for acquiring a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, and generating a switch control signal based on a processing algorithm, wherein the processing algorithm is an encoding algorithm or a decoding algorithm;
the pulse generator is connected with the processor and is used for generating a logic level signal based on the element numerical values in the binary data sequence;
the switch array is connected with the processor and the pulse generator and is used for enabling the corresponding switch to be conducted under the action of the switch control signal so as to enable a link for controlling the processor to output the direct current pulse signal and a link for controlling the pulse generator to output the logic level signal to be conducted;
the memristor array is correspondingly connected with the processor, the pulse generator and the switch array, is used for receiving the binary check matrix written by the processor and outputting a target sequence under the action of the accessed direct current pulse signal and the logic level signal,
when the processing algorithm is a coding algorithm, the target sequence is a coding sequence corresponding to the binary data sequence; when the processing algorithm is a decoding algorithm, the target sequence is an original code sequence corresponding to the binary data sequence decoding.
In one embodiment, when the memristor-based binary domain matrix arithmetic circuit is used to perform an encoding algorithm for the binary data sequence,
the pulse generator is used for generating a pulse sequence x according to the original code sequenceTThe numerical value of the middle element generates a logic level signal, when the element 0 outputs a low level, and when the element 1 outputs a high level;
the memristor array is used for receiving a check matrix A written by the processor, wherein element 0 is written into a high-resistance state, and element 1 is written into a low-resistance state; the positive electrode of a memristor corresponding to the conducting switch is connected with the logic level signal, the negative electrode of the memristor is connected with the direct current pulse signal, so as to output the target sequence, and the target sequence is the binary data sequence xTOf (a) a coding sequence AxT。
In one embodiment, when the memristor-based binary domain matrix arithmetic circuit is used to perform a decoding algorithm for the binary data sequence,
the memristor array is used for storing an augmentation matrix composed of a check matrix A and a coding sequence y, the logic level signal is accessed to the word line of each memristor in the memristor array to execute the exclusive OR operation between the rows of the memristor array so as to output the aimTargeting sequence xTThe target sequence decodes the corresponding original code sequence x for the coding sequence yTWherein x isTIs a non-homogeneous equation AxTThe solution of y.
In one embodiment, the processor is further configured to,
when the element in the binary check matrix and the element in the binary data sequence carry out multiplication operation, setting the switch control signal as a conducting signal;
and when the elements in the binary check matrix and the elements in the binary data sequence are subjected to addition operation, setting the switch control signals corresponding to the two superposed elements as conducting signals.
In one embodiment, the switch array comprises:
the row switch array comprises a plurality of row switches, and the row switches are respectively connected with word lines of all memristors in the memristor array one by one;
the column switch array comprises a plurality of column switches, and the column switches are respectively connected with bit lines of all memristors in the memristor array one by one;
when a row switch and a column switch which are correspondingly connected with any memristor in the memristor array are both in a conducting state, any memristor in the memristor array receives the direct current pulse signal.
In one embodiment, the structure of the memristor array is a crossbar structure, a transistor-memristor cascade structure, a single transistor-multiple memristor cascade structure, or a three-dimensional stacked structure, wherein the memristor is a binary device.
In one embodiment, the memristor in the memristor array is a resistive random access memory, a phase change memory, a self-selection transfer torque-magnetic random access memory, a NOR Flash device or a NAND Flash device.
Generally, compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. because the check matrix corresponding to the coding algorithm or the decoding algorithm is stored in the memristor array, and the sequence to be coded or decoded is input into the memristor array in a voltage mode, the memristor array directly outputs the target sequence without moving a large amount of data back and forth in the memory and the arithmetic unit, compared with the coding algorithm and the decoding algorithm executed by the prior art such as a CPU (central processing unit), the calculation speed can be improved, the energy consumption can be reduced, and the time delay can be reduced;
2. as for the vector sum matrix of the binary domain, the operation of the sum is equivalent to multiplication, and the exclusive or is equivalent to addition, the binary matrix is stored in the memristor array, and then the binary vector is input into the memristor array in a voltage mode, so that the multiplication of the vector sum of the binary domain matrix and the solution of the binary heterogeneous equation can be quickly realized.
Drawings
FIG. 1 is a schematic diagram of a memristor-based binary domain matrix operation circuit in an embodiment of the present application;
FIG. 2 is a schematic diagram of an AND logic operation of a single memristor in an embodiment of the present application;
FIG. 3 is a schematic diagram of an XOR logic operation performed by three memristors according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a memristor array performing an AND logic operation in an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating a batch execution of XOR accumulation operations in a memristor array in an embodiment of the present application;
FIG. 6 is an operation diagram illustrating solution of an equation set by row XOR in a memristor array in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The application provides binary field matrix arithmetic circuit based on recall and hinder ware includes: the device comprises a processor, a pulse generator, a switch array and a memristor array. As shown in fig. 1, the processor refers to a combination of a computer system and a read/write control/circuit, and is configured to obtain a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, and generate a switch control signal based on a processing algorithm, where the processing algorithm is an encoding algorithm or a decoding algorithm. The pulse generator is connected with the processor and used for generating a logic level signal based on element numerical values in the binary data sequence, and the switch array is connected with the processor and the pulse generator and used for enabling the corresponding switch to be conducted under the action of a switch control signal so that the processor controls the output of a direct current pulse signal and the pulse generator outputs the logic level signal to the memristor array; and the memristor array is correspondingly connected with the processor, the pulse generator and the switch array, is used for receiving the binary check matrix written by the processor, and outputs a target sequence under the action of the accessed direct-current pulse signal and the logic level signal.
Specifically, the processor obtains a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence. Namely, the processor obtains an original sequence to be coded and a corresponding coding check matrix, or the processor obtains a coding sequence to be decoded and a corresponding decoding check matrix. The encoding check matrix and the decoding check matrix may be the same or different, and are not limited herein. In one embodiment, the processor is further configured to set the switch control signal as a turn-on signal and transmit the turn-on signal to the switch array when the element in the binary check matrix and the element in the binary data sequence are multiplied (and operated); when the elements in the binary check matrix and the elements in the binary data sequence are subjected to addition operation (exclusive or operation), the switch control signals corresponding to the two superimposed elements are set as conducting signals and transmitted to the switch array.
Further, the processor controls the pulse generator to generate the voltage sequence according to the numerical value of the middle element of the binary data sequence. When the element 0 in the binary data sequence is 0, the corresponding low level in the voltage sequence; when element 1 in the binary data sequence, the corresponding high level in the voltage sequence. The processor writes a resistance state into the memristor array according to the middle element value of the check matrix, and writes a low resistance state into the memristor at the corresponding position when the middle element value of the check matrix is 1; and when the value of the middle element of the check matrix is 0, writing a high-resistance state into the memristor at the corresponding position. The switch array is turned on or turned off under the action of the switch signal, and the memristor in the memristor array can be controlled to participate in work. In one embodiment, the switch array comprises: the row switch array comprises a plurality of row switches, and the row switches are respectively connected with word lines of all memristors in the memristor array one by one; the column switch array comprises a plurality of column switches, and the column switches are respectively connected with bit lines of all memristors in the memristor array one by one; when a row switch and a column switch which are correspondingly connected with any memristor in the memristor array are both in a conducting state, any memristor in the memristor array receives a direct current pulse signal.
And finally, inputting a direct-current pulse signal and a logic level signal corresponding to the binary data sequence into the memristor array written into the check matrix, so that the memristor at the corresponding position can work, and the memristor array outputs a target sequence. When the processing algorithm is a coding algorithm, the target sequence is a coding sequence corresponding to the binary data sequence; when the processing algorithm is a decoding algorithm, the target sequence is a binary data sequence and decodes a corresponding original code sequence.
In one embodiment, when the memristor-based binary domain matrix arithmetic circuit is used for executing an encoding algorithm of a binary data sequence, the pulse generator is used for generating a pulse code sequence x according to the original code sequenceTThe numerical value of the middle element generates a logic level signal, when the element 0 outputs a low level, and when the element 1 outputs a high level; the memristor array is used for receiving a check matrix A written by the processor, wherein element 0 is written into a high-resistance state, and element 1 is written into a low-resistance state; the positive electrode of a memristor corresponding to the conducting switch is connected with a logic level signal, the negative electrode of the memristor is connected with a direct current pulse signal, and a target sequence is output and is a binary data sequence xTOf (a) a coding sequence AxT。
For example, memristor-based binary domain matrix operation circuit is used for performing binary data sequence xTCoding algorithm (i.e. binary matrix a and vector x)TMultiplication) as follows:
s101, writing a first input variable A into a memristor array, writing a high-resistance state if the first input variable A is 0, and writing a low-resistance state if the first input variable A is 1;
s102, inputting a second variable xTSwitching to a corresponding logic level, low if 0, here represented by ground, and high if 1, here represented by VDD/2;
and S103, simultaneously and respectively applying the logic level x and a VDD pulse to the anode and the cathode of the device to complete AND operation.
FIG. 2 is a schematic diagram of a memristor in the present invention to implement a logical AND operation; when the elements in A and xTWhen the elements in the high-resistance state are 0 at the same time, the negative voltage drop larger than the threshold voltage exists in the high-resistance state, the resistance state is not changed, the high-resistance state is maintained unchanged, and 0 is output; when A is 0, xTWhen the resistance is 1, the negative voltage drop smaller than the threshold voltage exists in the high resistance state, the device maintains the high resistance state unchanged, and 0 is output; when A is 1, xTWhen the resistance is equal to 0, negative pressure drop with amplitude larger than the second threshold voltage exists in the low resistance state, the device is changed from the low resistance state to the high resistance state, and 0 is output; when A is 1, xTWhen the resistance state is equal to 1, the negative voltage drop smaller than the second threshold voltage exists in the low resistance state, the resistance state of the device cannot be changed, the low resistance state is maintained unchanged, and 1 is output; the above four combinations correspond to logical and operations.
In addition, it is complementary that the binary matrix a and the vector xTThe process of multiplication of (a) may also be:
s201, writing an M multiplied by N matrix A into an array with a corresponding scale;
s202, converting the vector xTConverting into a corresponding logic voltage sequence;
s203, simultaneously applying a voltage sequence to the bit lines of the array where A is located, and applying a VDD pulse to the word lines;
s204, continuing to perform exclusive or accumulation on the array after the AND operation is performed, wherein the accumulated result is y;
each xor operation is divided into two steps, as shown in the column xor of fig. 3, and the method can perform parallel operations on elements in one column at the same time. As shown in fig. 4, a voltage vector is applied to a word line of the memristor. The step of accumulating is shown in fig. 5, where m1 is obtained by performing a first xor operation on the first column and the second column, where the first column of the intermediate result region exists, m2 is obtained by performing a second xor operation on the second column and m1, and the second column of the intermediate result region exists, until y is obtained by performing N-1 xor accumulation on the matrix after the whole and operation.
In one embodiment, when the memristor-based binary domain matrix operation circuit is used for executing a decoding algorithm of a binary data sequence, the memristor array is used for storing an augmentation matrix formed by a check matrix A and a coding sequence y, and a logic level signal is connected to a word line of each memristor in the memristor array to execute an exclusive-or operation between rows of the memristor array so as to output a target sequence xTThe target sequence is an encoding sequence y for decoding a corresponding original code sequence xTWherein x isTIs a non-homogeneous equation AxTThe solution of y.
For example, memristor-based binary domain matrix operation circuit is used for performing binary data sequence xTDecoding algorithm (i.e. the system of two-dimensional non-homogeneous linear equations Ax)TSolving for y) as follows:
in performing a binary field matrix vector multiplication operation AxTWhen the value is y, the operation steps are as follows:
s301, writing an augmentation matrix A | y of a binary domain non-homogeneous linear equation set to be solved into a memristor array of a corresponding scale;
s302, loading a Gaussian elimination algorithm program of a binary domain matrix into a processor connected with the memristor array;
s303, gaussian elimination is performed by parallel row xor, which refers to the xor operation between rows, as shown in the middle part of fig. 3.
The gaussian elimination of the binary field is improved because multiplication is not needed and the exclusive or between rows in the array can be performed in parallel, as shown in fig. 6. The top is an augmentation matrix which is composed of (4) row vectors, and the first step isPerforming exclusive or on the third and the fourth to obtain 0, finding two 1 in the coefficients, and respectively taking the first and the third as positions; continuously searching for 1 in the two positions in the first to the second, performing exclusive OR on the row vectors of which the number of 1 is more than 2 (at least 3 1), applying reading voltage to 4 bit lines, reading the end current of the word lines of the first to the second, if the number of 1 is more than 3, continuously applying reading voltage to the first to the third to determine whether the two positions have 1, finding out the qualified first, performing exclusive OR on the first and the fifth to obtain the fourth 1, applying reading voltage to the four bit lines, reading the end current of the word line of the fourth 2, finding that only one 1 is left in the 4 coefficients, showing that the fourth 3 has been completed with elimination, continuously determining the position of the 1, and that the last element of the fourth 4 is 1, therefore, obtaining x41 is ═ 1; continuously searching a 4 th bit of a row vector with the value of 1 in the fifth place, applying a reading voltage to the 4 th bit line, determining that the fourth bit of the fourth place is 1, performing exclusive or with the fourth place respectively to obtain the values of 0, 1 and 2, reading the hamming weight of the coefficient vector with the value of 1, determining that the values of 3, 4 and 5 are all zero, checking whether all solutions are obtained, searching the positions of 1 of the coefficient vector with the values of x, x and y respectively2，x3，x1The value is the last element of the row vector, x2＝0,x3＝1,x1X has been solved for 1,64And (5) ending the solution when the value is 1.
In one embodiment, the structure of the memristor array is a crossbar structure, a transistor-memristor cascade structure, a single transistor-multiple memristor cascade structure, or a three-dimensional stacked structure, wherein the memristors are binary devices.
In one embodiment, the memristor in the memristor array is a resistive random access memory, a phase change memory, a self-selection transfer torque-magnetic random access memory, a NOR Flash device or a NAND Flash device.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A memristor-based binary domain matrix arithmetic circuit, comprising:
the processor is used for acquiring a binary data sequence to be processed and a binary check matrix corresponding to the binary data sequence, and generating a switch control signal based on a processing algorithm, wherein the processing algorithm is an encoding algorithm or a decoding algorithm;
the pulse generator is connected with the processor and is used for generating a logic level signal based on the element numerical values in the binary data sequence;
the switch array is connected with the processor and the pulse generator and is used for enabling the corresponding switch to be conducted under the action of the switch control signal so as to enable a link for controlling the processor to output the direct current pulse signal and a link for controlling the pulse generator to output the logic level signal to be conducted;
the memristor array is correspondingly connected with the processor, the pulse generator and the switch array, is used for receiving the binary check matrix written by the processor, and outputs a target sequence under the action of the accessed direct-current pulse signal and the logic level signal;
when the processing algorithm is a coding algorithm, the target sequence is a coding sequence corresponding to the binary data sequence; when the processing algorithm is a decoding algorithm, the target sequence is an original code sequence corresponding to the binary data sequence decoding.
2. The memristor-based binary domain matrix operation circuit of claim 1, wherein, when the memristor-based binary domain matrix operation circuit is used to perform an encoding algorithm of the binary data sequence,
the pulse generator is used for generating a pulse sequence x according to the original code sequenceTThe numerical value of the middle element generates a logic level signal, when the element 0 outputs a low level, and when the element 1 outputs a high level;
the memristor array is used for receiving a check matrix A written by the processor, wherein element 0 is written into a high-resistance state, and element 1 is written into a low-resistance state; conducting switchThe positive pole of the corresponding memristor is connected with the logic level signal, the negative pole of the corresponding memristor is connected with the direct current pulse signal, so as to output the target sequence, and the target sequence is the binary data sequence xTOf (a) a coding sequence AxT。
3. The memristor-based binary domain matrix operation circuit of claim 1, wherein, when the memristor-based binary domain matrix operation circuit is used to perform a decoding algorithm of the binary data sequence,
the memristor array is used for storing an augmentation matrix composed of a check matrix A and a coding sequence y, and after the logic level signal is accessed to the word line of each memristor in the memristor array, the exclusive OR operation between the rows of the memristor array is executed so as to output the target sequence xTThe target sequence decodes the corresponding original code sequence x for the coding sequence yTWherein x isTIs a non-homogeneous equation AxTThe solution of y.
4. The memristor-based binary domain matrix arithmetic circuit of claim 1, wherein the processor is further to,
when the element in the binary check matrix and the element in the binary data sequence carry out multiplication operation, setting the switch control signal as a conducting signal;
and when the elements in the binary check matrix and the elements in the binary data sequence are subjected to addition operation, setting the switch control signals corresponding to the two superposed elements as conducting signals.
5. The memristor-based binary domain matrix arithmetic circuit of claim 1, wherein the switch array comprises:
the row switch array comprises a plurality of row switches, and the row switches are respectively connected with word lines of all memristors in the memristor array one by one;
the column switch array comprises a plurality of column switches, and the column switches are respectively connected with bit lines of all memristors in the memristor array one by one;
when a row switch and a column switch which are correspondingly connected with any memristor in the memristor array are both in a conducting state, any memristor in the memristor array receives the direct current pulse signal.
6. The memristor-based binary domain matrix arithmetic circuit of any one of claims 1-5, wherein the memristor array has a structure of a crossbar structure, a transistor-memristor cascade structure, a single transistor-multiple memristor cascade structure, or a three-dimensional stacked structure, wherein the memristors are binary devices.
7. The memristor-based binary domain matrix operation circuit according to any one of claims 1 to 5, wherein the memristors in the memristor array are resistive random access memories, phase change memories, self-selection transfer torque-magnetic random access memories, NOR Flash devices or NAND Flash devices.
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