TWI771014B - Memory circuit and operating method thereof - Google Patents

Abstract

A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements. A method of operating memory circuit is also disclosed herein.

Description

Memory circuit and method of operation

The present disclosure relates to a memory circuit and a method of operation thereof.

Memory arrays are commonly used to store and access data for various types of operations, such as logical or mathematical operations. To perform these operations, data bits are moved between the memory array and the circuits used to perform the operations. In some cases, the operation includes multiple layers of operations, and the results of the first operation are used as input data in the second operation.

The present disclosure includes a memory circuit. The memory circuit includes a plurality of input data elements for receiving a plurality of input data elements (each input data element of the input data elements includes a number of bits equal to N) and outputting the first of the H bits of each input data element of the input data elements. A selection circuit for a selected set of k bits, a row of memory cells (each memory cell of a row of memory cells includes a first storage cell for storing a first weight data element and a first weight data element for and the first kth bit in the selected set of kth bits to generate the first multiplier of the first product data element) and used to multiply based on the first Each of the product data elements produces an adder tree that sums the data elements.

The present disclosure includes a method of operating a memory circuit. The method includes receiving, at the row of memory cells, a set of the kth bit of the H number of bits of each input data element in the input data element; The kth bit of the input data element is multiplied by the first weight data element stored in the memory unit, thereby generating a corresponding first product data element; using an adder tree to generate a calculation based on each of the first product data elements; and data elements.

The present disclosure includes a memory circuit. The memory circuit includes a selection circuit for sequentially outputting a selected set of the kth bit to each memory in the plurality of memory cell rows for a plurality of input data elements each including H bits Corresponding memory cells in a row of memory cells; a plurality of adder trees, each adder tree in the adder tree coupled to a corresponding row of memory cells in the row of memory cells; a plurality of accumulators, each of the accumulators in the accumulators The adder is coupled to a corresponding adder tree of the adder tree. Each memory cell of each memory cell row includes a multiplier for generating product data based on the corresponding kth bit in the selected set of the kth bit and the weight data element stored in the memory cell element; each adder tree in the adder tree is used for each sequential output set of the kth bit to generate a summation data element based on each of the product data elements corresponding to the row of memory cells; each of the accumulators in the accumulator Accumulators are used to generate partial sums based on summing data elements generated by corresponding adder trees in the adder tree.

100A: Memory circuit

100B: Memory circuit

110: Selection circuit

120A: Memory Array

120B: Memory array

122: Adder tree

130: I/O circuit

140: accumulator

150: Control circuit

152: Processor

154: Computer-readable storage media

200: Selection circuit

200R: Data register

300A: memory unit

300B: Memory unit

400: Adder tree

500: accumulator

900: Method

910: Operation

920:Operation

930: Operation

940: Operation

950:Operation

1000: Method

1010: Operation

1020: Operations

1030: Operation

1040: Operation

1050: Operation

1060:Operation

1070:Operation

Aspects of the present disclosure will emerge from the following details when read in conjunction with the accompanying drawings. A detailed description is best understood. It should be noted that in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1A and 1B are diagrams of memory circuits according to some embodiments.

FIG. 2 is a diagram of a selection circuit according to some embodiments.

3A and 3B are diagrams of memory cells according to some embodiments.

Figure 4 is a diagram of an adder tree according to some embodiments.

Figure 5 is a diagram of an accumulator according to some embodiments.

FIG. 6 is a diagram of a portion of a memory array in accordance with some embodiments.

7A and 7B are diagrams of portions of memory circuits according to some embodiments.

FIG. 8 is a graph of memory circuit operating voltages in accordance with some embodiments.

9 is a flowchart of a method of operating a memory circuit in accordance with some embodiments.

10 is a flowchart of a method of operating a memory circuit in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, configurations, or the like are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. Consider other components, values, operations, materials, configurations, or the like. For example, in the following description the formation of a first feature over or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include additional Embodiments in which the outer feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference to digits and/or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and/or configurations discussed.

Furthermore, to facilitate the description used to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures, spatially relative terms such as "in. "below", "below", "below", "above", "above", and the like. Spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly accordingly.

In various embodiments, the memory array of the memory circuit includes both memory storage units and mathematical operation units, and is thereby used to perform in-memory operations to generate partial sums based on input data elements and stored weight data elements. Such memory circuits are capable of generating partial sums using a smaller area and lower power bits than methods in which the memory array does not include elements to perform in-memory operations. In various applications, such as convolutional neural network (CNN) applications, memory circuitry enables an array of stored weight data elements to be efficiently applied to the product of one or more sets of input data elements Accumulation (multiply and accumulate; MAC) operation.

FIGS. 1A and 1B are memory circuits according to some embodiments. Figures for each of roads 100A and 100B. Each of the memory circuits 100A and 100B includes a selection circuit 110 coupled to the input data bus IDB and the corresponding memory array 120A or 120B, an input/output (I/O) coupled to the corresponding memory array 120A or 120B O) circuit 130 and M number of accumulators 140, and control circuit 150 coupled via control signal bus CTRLB to selection circuit 110, corresponding memory array 120A or 120B, I/O circuit 130, and each Accumulator 140 .

Each of the memory arrays 120A and 120B includes M rows C1 through CM corresponding to the M accumulators 140 . Memory array 120A includes N number of memory cell BCX columns, each memory cell BCX column includes a single input terminal (not labeled) and a single output terminal (not labeled), each input terminal thus corresponding to N of memory array 120A. one of the data columns. Memory array 120B includes N/2 columns of memory cells BX2, each column BX2 of memory cells includes two input terminals (not labeled) and a single output terminal (not labeled), each input terminal thus corresponds to memory array 120B One of the N data columns of . As described below, each of the memory circuits 100A and 100B is thus configured to receive a plurality of N input data elements A1 through AN on the input data bus IDB, each input data element A1 through AN including a number of bits equal to H.

Table 1 depicts the data structure of input data elements A1 through AN, each of the N input data elements A1 through AN including H data bits.

As described below, memory circuits 100A and 100B are configured to allow, in operation, each row C1 to CM of each memory array 120A and 120B to simultaneously receive the same numbered bits of each input data element A1 to AN from select circuit 110 (th k bits), that is, a set of bits A1k to ANk. Each row performs a mathematical operation based on the received set of bits A1k to ANk and the weight data elements stored in the corresponding memory cell BCX or BX2, thereby generating an M number of summation data elements SD1 to SDM corresponding to rows C1 to CM .

Counter k loops between each of the H bits, eg, from 1 to H, such that selection circuit 110 outputs the set of bits A1k to ANk in a sequentially selected fashion, with each row for each value pair of counter k The selected set of bits A1k through ANk repeats the mathematical operation, thereby producing a sequence of H summed data elements SD1 through SDM. The accumulator 140 is used to generate the corresponding partial sums PS1 to PSM based on the sequence of summed data elements SD1 to SDM, and output the partial sums PS1 to PSM on the corresponding output ports O1 to OM.

In the embodiment depicted in FIG. 1A, memory array 120A includes memory cells BCX for each receiving in a sequentially selected set of the kth bit of input data elements A1 through AN , and in the embodiment depicted in FIG. 1B, memory array 120B includes memory cells BX2 for Each receives two bits of adjacent data elements in the sequentially selected set of the kth bit of input data elements A1 through AN. Each memory circuit 100A and 100B is thereby used to be able to perform some or all of a method (eg, one or both of methods 900 or 1000 discussed below with respect to FIGS. 9 and 10) by which the method is performed In-memory operations.

In various embodiments, the memory circuit 100A or 100B is included in a neural-like network, such as a CNN, sensors (eg, magnetic, imaging, vibration, or gyroscopic sensors), radio-frequency (RF) devices , or other integrated circuit (integrated circuit; IC) devices.

Each of the memory circuits 100A and 100B is simplified for illustrative purposes. In various embodiments, one or both of the memory circuits 100A or 100B include various elements other than those depicted in Figures 1A and 1B, or are otherwise arranged to perform the operations described below.

Two or more circuit elements are considered coupled based on one or more direct signal connections and/or one or more indirect signal connections, including one or more between the two or more circuit elements Logic devices such as inverters or logic gates. In some embodiments, signal communication between two or more coupled circuit elements can be modified, eg, inverted or conditional, by one or more logic devices.

The selection circuit 110 is an electronic circuit including one or more data registers (not shown in FIGS. 1A and 1B ) coupled to the input data bus IDB, and coupled to the one or more data registers (not shown in FIGS. 1A and 1B ) A plurality of data registers and one or more multiplexers or similar circuits for the control signal bus CTRLB (not shown in Figures 1A and 1B).

A data register, also referred to as a buffer in some embodiments, is an electronic circuit used to temporarily store some or all of one or more data elements, such as H of each input data element A1 to AN bits. In various embodiments, the data register includes a single set of terminals for inputting and outputting data bits, or separate sets of terminals for inputting and outputting data bits.

A multiplexer is an electronic circuit that includes a first set of terminals for receiving a plurality of signals (eg, H bits of one of input data elements A1 through AN), for receiving one or more one or more switching devices (eg, transistors) for a control signal (eg, control signal CTRL), and at least one terminal for outputting selected ones of the received signals in response to the one or more control signals one.

The selection circuit 110 is thus used to store the H bits of each data element A1 to AN received on the input data bus, and in response to one or more control signals CTRL received on the control signal bus CTRLB, to select The set of k-th bits A1k to ANk of is output to the corresponding one of the memory arrays 120A or 120B. For each input data element A1 to AN, the correspondingly selected k-th bit A1k to ANk is the same k-th bit of a total of H bits. In some embodiments, selection circuit 110 includes selection circuit 200 discussed below with respect to FIG. 2 .

In some embodiments, the selection circuit 110 is configured to receive an N number (ranging from 4 to 512) of input data elements A1 to AN. In some embodiments, the selection circuit 110 is configured to receive an N number (ranging from 32 to 128) of input data elements A1 to AN.

In some embodiments, the selection circuit 110 is configured to receive H number (ranging from 1 to 16) bits of each input data element A1 to AN. In some embodiments, the selection circuit 110 is configured to receive H number (ranging from 4 to 8) bits of each input data element A1 to AN.

In various embodiments, one or more control signals CTRL are used to cause the selection circuit 110 to operate from the least significant bit (LSB) to the most significant bit (MSB) or from the MSB to The LSB sequentially outputs the set of k-th bits A1k to ANk. In various embodiments, one or more control signals CTRL are used to cause the selection circuit 110 to sequentially output all or a subset of the H number of bit sets. In some embodiments, each of the input data elements A1 to AN includes a number of bits less than H, and the one or more control signals CTRL are used to cause the selection circuit 110 to sequentially output the received number of bits of a set of bits. All or a subset.

In various embodiments, one or more control signals CTRL are used to cause selection circuit 110 to output all or a subset of the corresponding selected set of kth bits A1k through ANk for each value of counter k. In some embodiments, the plurality of input data elements includes a number of data elements less than N, and one or more control signals CTRL are used to cause the selection circuit 110 to output the received data element number of data for each value of the counter k All or a subset of the corresponding set of k-th bits A1k to ANk of the element.

Each memory array 120A and 120B is an electronic circuit that includes M rows C1-CM, each row C1-CM including an adder tree 122 discussed below, and a corresponding adder tree coupled to the adder tree 122 Memory cell BCX or BX2. The memory cells BCX or BX2 of each row C1 to CM are further coupled to the selection circuit 110 and are thereby used so that in operation, each row C1 to CM simultaneously receives the kth bit A1k to CM from the selection circuit 110 based on the output of the counter k. The selected set of ANk.

Because each memory cell BCX is used to receive bits of a single data element A1 to AN, the memory array 120A includes a total of N memory cell BCX rows R1 to RN, such that each row R1 to RN corresponds to a row of the memory array 120A. data column. Since each memory cell BX2 is used to receive the bits of two data cells A1 to AN, the memory array 120B includes a total of L memory cells BX2 rows R1 to RL, the number L being equal to N/2, such that each row R1 to RL Corresponding to the two data columns of the memory array 120B. In the embodiment depicted in Figures 1A and 1B, each instance of memory cell BCX or BX2 includes a position indicator, such as 21, corresponding to the row and column in which a given instance is located.

In some embodiments, the memory array 120A or 120B includes an M number (ranging from 2 to 512) of rows C1 to CM. In some embodiments, the memory array 120A or 120B includes an M number (ranging from 16 to 128) of rows C1 to CM.

In the embodiment depicted in Figures 1A and 1B, each memory array 120A and 120B includes a single array layer of columns R1-RN or columns R1-RL and rows C1-CM. In some embodiments, one or both of the memory arrays 120A or 120B include one or more array layers (not shown) in addition to the single layer depicted in Figures 1A and 1B, thereby including Include columns and rows other than those of a single layer.

The memory cell BCX includes storage elements coupled to a multiplier (not shown in Figures 1A and 1B). A storage element is an electrical, electromechanical, electromagnetic, or other device used to store one or more bits of data expressed by logical states. In some embodiments, the logic state corresponds to the voltage level of the charge stored in some or all of the storage element. In some embodiments, the logical state corresponds to some or all of the physical properties of the storage element, such as resistance or magnetic orientation.

In some embodiments, the storage element includes one or more static random-access memory (SRAM) cells. In various embodiments, an SRAM cell, eg, five-transistor (5T), six-transistor (6T), eight-transistor (8T), or nine-transistor (nine) -transistor; 9T) SRAM cell comprising a number of transistors ranging from two to twelve. In some embodiments, the SRAM cells comprise multi-rail SRAM cells. In some embodiments, the SRAM cell includes a length that is at least twice the width.

In some embodiments, the storage element includes one or more dynamic random-access memory (DRAM) cells, resistive random-access memory (RRAM) cells, Access memory (magnetoresistive random-access memory; MRAM) unit, ferroelectric random-access memory (ferroelectric random-access memory; FeRAM) cell, inverse or flash cell, inverse and flash cell, conductive-bridging random-access memory (CBRAM) cell, data register, non-volatile memory; NVM) cells, 3D NVM cells, or other memory cell types capable of storing bit data.

In some embodiments, the storage element is used to store a number of data bits ranging from 1 to 16. In some embodiments, the storage element is used to store a number of data bits ranging from 4 to 8.

The storage element includes one or more I/O connections (not shown) through which logic states are programmed in write operations and accessed in read operations, such as multiply operations.

A multiplier is an electronic circuit that includes one or more logic gates based on a received data bit (eg, a selected one of the kth bit A1k to ANk ) and the received data element ( For example, a multi-bit weight data element stored in a storage element performs a mathematical operation (eg, multiplication), thereby producing a product data element equal to the product of the input data element and the input data element. In some embodiments, a multiplier is used to generate a product data element comprising a number of bits equal to the number of bits of the received data element. In various embodiments, the multiplier includes one or more AND gates or inverse-OR gates or other circuits suitable for performing some or all of the multiplication operations.

By including a storage element coupled to the multiplier and used to store the weight data element, and coupled to the selection circuit 110 and used to receive the multiplication of a bit in the selected set of kth bits A1k-ANk , each memory cell BCX is used for processing based on the kth bit A1k to ANk A bit in the selected set and the weight data element corresponding to the location of a given memory cell BCX within memory array 120A generate product data elements P11 through PMN. In some embodiments, memory cell BCX includes memory cell 300A discussed below with respect to FIG. 3A.

The memory cell BX2 includes a first storage element coupled to the first multiplier, a second storage element coupled to the second multiplier, and an adder coupled to the first and second multipliers (FIG. 1A and FIG. Not shown in Figure 1B). A first storage element and multiplier are used to generate a first product data element, as discussed above with respect to memory cell BCX; and a second storage element and multiplier are used to generate a second product data element, as discussed above with respect to memory cell BCX .

An adder is an electronic circuit that includes one or more logic gates for receiving first and second data elements (eg, first and second product data generated by first and second multipliers) element) performs a mathematical operation, such as addition, thereby producing a sum data element equal to the sum of the received first and second data elements. In some embodiments, the adder is used to generate a sum data element comprising a number of bits that is one greater than the number of bits of each of the received first and second data elements. In various embodiments, the adder includes one or more of a full adder gate, a half adder gate, a ripple-carry adder circuit, a carry-save adder -save adder circuits, carry-select adder circuits, carry-look-ahead adder circuits, or other circuits suitable for performing some or all of the addition operations.

by including a first multiplier to generate a first product data element based on a first bit element of the selected set of kth bits A1k-ANk and the first stored weight data element for generating the first product data element based on the kth bit The second bit of the selected set of bits A1k through ANk produces a second multiplier of the second product data element, and an adder coupled to each of the first multiplier and the second multiplier, each Memory cell BX2 is used to base the first and second bits in the selected set of kth bits A1k through ANk and the first and second bits corresponding to the location of a given memory cell BX2 within memory array 120B. The second weight data element is generated and data elements S11 to SML are generated. In some embodiments, memory cell BX2 includes memory cell 300B discussed below with respect to Figure 3B.

The adder tree 122 is an electronic circuit comprising a plurality of adder layers (not shown in FIGS. 1A and 1B ), the first of which is used to receive a plurality of data elements, such as product data elements P11 to PMN or sum data elements S11 to SML, and the last layer includes a single adder for generating a data element based on the received plurality of data elements, eg summing data elements SD1 to SDM. In some embodiments, each of the one or more consecutive layers between the first layer and the last layer is used to receive a first number of sum data elements generated by the previous layer, and is generated based on the first number of sum data elements A second number of sum data elements, the second number being half of the first number. Here, the total number of layers includes the first and last layers and each successive layer (if any). In some embodiments, adder tree 122 includes adder tree 400 discussed below with respect to FIG. 4 .

The adder tree 122 is thus used to receive a plurality of data elements, The complex number equals two to the power of a number equal to the total number of layers, and the number of data elements is thus a binary exponent of the total number of layers. In the embodiment depicted in FIG. 1A, memory array 120A includes instances of adder tree 122 that includes a total level number of levels such that the total level power of two equals N product data elements, eg P11 to P1N. In the embodiment depicted in FIG. 1B, memory array 120B includes instances of adder tree 122 that includes a total of levels such that the total level of two powers equals L sum data elements, eg, S11 to S1L.

In some embodiments, the adder tree 122 includes a total number of levels ranging from 2 to 9. In some embodiments, the adder tree 122 includes a total number of levels ranging from 4 to 7 levels.

In some embodiments, each adder in each level of the adder tree 122 is used to generate a corresponding sum data element comprising a more A number of bits greater than the number of bits in the data element in the data element).

In some embodiments depicted in FIG. 1A, the adder tree 122 includes a first level for receiving product data elements P11 through PMN, the product data elements including equal to the amount stored in each memory cell BCX a first number of bits of the number of bits of weight data elements, and a last layer for generating summed data elements SD1 to SDM, the summed data elements including a second number of bits, the second The number is equal to the first number plus a value equal to the total number of levels in the adder tree 122 .

In some embodiments depicted in Figure 1B, the adder tree 122 includes a first level for receiving and data elements S11 through SML, The sum data elements include a first number of bits greater by 1 than the number of bits of the weight data elements stored in each memory unit BX2, and a last layer for generating the sum data elements SD1 to SDM , the summation data elements include a second number of bits equal to the first number plus a value equal to the total number of levels in the adder tree 122 .

The I/O circuit 130 is coupled to the control signal bus CTRLB and to the memory array via one or more word lines, one or more bit lines, and/or one or more data lines (not shown) An electronic circuit to which one or more I/Os of each storage element of each memory cell BCX of 120A or each memory cell BX2 of memory array 120B are connected. The I/O circuit 130 is thus configured to program each memory cell BCX or BX2 to one or more logic states during a write operation in response to one or more control signals CTRL received from the control signal bus CTRLB, And make one or more logic states stored in each memory cell BCX or BX2 accessible in a read operation.

Accumulator 140 is an electronic circuit coupled to the control signal bus CTRLB, and includes one or more adders, one or more data registers, and one or more shifters ( 1A and 1B not shown). One or more adders are coupled to the adder tree 122 and are thereby used to receive one of the summed data elements SD1 to SDM, each of which corresponds to the self-select circuit 110 based on the counter k One of the H summed data elements SD1 to SDM sequences of the sequentially selected set of kth bits A1k to ANk of the output.

The one or more adders are further for receiving from the one or more shifts The shifted data elements output by the processor are generated, and an internal sum data element is generated based on one of the shifted data elements and the summed data elements SD1 to SDM. One or more data registers for receiving internal sum data elements from one or more adders, storing internal sum data elements, and outputting the stored internal sum data elements to one or more shifters and to output ports The corresponding one of O1 to OM. One or more shifters for receiving stored internal data elements output from one or more data registers and generating shifts by shifting the stored internal data elements by one bit in the MSB direction or the LSB direction data element.

The accumulator 140 is thus used to perform an accumulation operation in response to one or more control signals CTRL received on the control signal bus CTRLB such that the stored internal summed data elements follow the sequence of the summed data elements SD1 to SDM. Each one is received and increased. One or more control signals CTRL are based on and/or include counter k information, and are thereby used to coordinate the accumulation operation with the sequential selection of the kth set of bits A1k to ANk such that the stored internal data elements are shifted bits and added to the selected summed data elements SD1 through SDM, synchronizing to the sequentially generated timing and MSB/LSB direction of the kth set of bits.

In operation, the corresponding H instances of summing data elements SD1 to SDM are stored in a The internal data elements in the data registers or registers are output on corresponding output ports O1 to OM as parts and a corresponding one of PS1 to PSM.

The control circuit 150 is an electronic circuit for generating the control signal CTRL and on the control signal bus CTRLB by the electronic circuit The output control signal CTRL controls the operation of the memory circuit 100A or 100B. In operation, the control signal CTRL is received from the control signal bus CTRLB by the selection circuit 110, the memory array 120A or 120B, the I/O circuit 130, and the accumulator 140 in accordance with the embodiments discussed above and below. In some embodiments, the control circuit 150 is used to generate a control signal CTRL that includes and/or is based on one or more timing signals.

In various embodiments, the control circuit 150 includes a hardware processor 152 and a non-transitory computer-readable storage medium 154 . The computer-readable storage medium 154, among other things, encodes (ie stores) computer code (ie, a set of executable instructions). Execution of instructions by hardware processor 152 represents (at least in part) a memory circuit operating tool implementing, for example, method 900 discussed below with respect to FIG. 9 and/or method 1000 discussed below with respect to FIG. 10 part or all of (hereinafter, the process and/or method).

In various embodiments, the processor 152 is electrically coupled to the computer-readable storage medium 154 via an I/O interface and to a network via a bus (details not shown). The network interface is connected to a network (not shown) so that the processor 152 and the computer-readable storage medium 154 can be connected to external components via the network. Processor 152 is used to execute computer code encoded in computer readable storage medium 154 so that control circuit 150 and memory circuit 100A or 100B may be used to perform some or all of the processes and/or methods. In one or more embodiments, the processor 152 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit integrated circuit; ASIC) and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium 154 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, the computer-readable storage medium 154 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, RAM, SRAM, DRAM, read-only memory (ROM), hard disk, and/or or disc. In one or more embodiments using optical disks, the computer-readable storage medium 154 includes compact disk-read only memory (CD-ROM), compact disk-read/write (CD) -R/W) and/or digital video disc (DVD).

In one or more embodiments, the computer-readable storage medium 154 stores computer program code for causing the control circuit 150 to generate control signals so as to be usable for performing some or all of the processes and/or methods. In one or more embodiments, computer-readable storage medium 154 also stores information that facilitates performing some or all of the processes and/or methods.

With the configuration discussed above, each memory circuit 100A and 100B can in operation receive input data elements A1 through AN on the input data bus IDB, select the kth bit A1k through ANk in sequence using selection circuit 110 , receiving a sequence of selected sets of bits A1k through ANk at each row C1 through CM of memory cell BCX or BX2, and performing a series of mathematics for synchronization using memory cell BCX or BX2 and the corresponding adder tree 122 operation, thereby outputting the partial sum PS1 to PSM on the output ports O1 to OM. by including the memory array 120A or 120B, each of the memory circuits 100A or 100B is configured to perform in-memory operations to generate at least one partial sum PS1 to PSM based on the input data elements A1 to AN and the stored weight data elements. Such memory circuits are capable of generating partial sums using a smaller area and lower power bits than methods in which the memory array does not include elements to perform in-memory operations.

FIG. 2 is a diagram of a selection circuit according to some embodiments. Selection circuit 200, also referred to as multiplexing circuit 200 in some embodiments, may be used as selection circuit 110 discussed above with respect to Figures 1A and 1B. The selection circuit 200 includes a data register 200R coupled to the input data bus IDB, and a plurality of N multiplexers M1 to MN coupled to the data register 200R and the control signal bus CTRLB.

The data register 200R includes a first set (not shown) of terminals coupled to the input data bus IDB and is thereby used to receive H bits of bit data including each of the input data elements A1 through AN, and Temporary storage of bit data. In various embodiments, the data register 200R is used to receive bit data in parallel or in series in operation. The data register 200R includes a second set (not shown) of terminals coupled to the multiplexers M1 through MN and thereby used to output each H bits of each input data element A1 through AN in operation (in the first 2 are depicted as A11 to A1H, A21 to A2H, ..., AN1 to ANH) to multiplexers M1 to MN.

The multiplexers M1-MN correspond to the input data elements A1-AN, such that each multiplexer M1-MN includes a set (not labeled) of terminals to receive the H bits of the corresponding data elements A1-AN. Each multiplexer M1 to MN includes corresponding output terminals M10-MNO, and is thereby used in operation to output corresponding data elements A1 to MNO on corresponding output terminals M10-MNO in response to one or more control signals CTRL received from control signal bus CTRLB. The selected set of kth bits Alk to ANk of AN. The multiplexers M1-MN and one or more control signals CTRL are used to simultaneously output the same k-th bit of each data element A1-AN in operation, thereby generating the k-th bit based on the counter k discussed above The set of elements A1k to ANk.

Selection circuit 200 is thus used to be able to perform the operations discussed above with respect to selection circuit 110 and Figures 1A and 1B. By including the selection circuit 200 as the selection circuit 110, each of the memory circuits 100A and 100B can achieve the above-mentioned benefits.

Figures 3A and 3B are diagrams of each of memory cells 300A and 300B, according to some embodiments. Memory cell 300A, also referred to as bit cell 300A in some embodiments, may be used as one or more instances of memory cell BCX discussed above with respect to FIG. 1A, and memory cell 300B, in some embodiments Also referred to as bit cell 300B in , may be used as one or more instances of memory cell BX2 discussed above with respect to FIG. 1B.

Each of the memory cells 300A and 300B are simplified for illustrative purposes. In various embodiments, one or both of the memory cells 300A or 300B include various elements in addition to those depicted in Figures 3A and 3B, or are otherwise arranged to perform the operations discussed below. In various embodiments, memory cell 300A or 300B includes multiplexing to one or more word lines, one or more bit lines, and/or one or more data lines (not shown) Several electrical connections, and thus to I/O circuit 130 discussed above with respect to Figures 1A and 1B, through which the weight data elements WTmn and WTm(n+1) discussed below are stored and/or or accessed.

Each memory unit 300A and 300B includes a storage unit SU1 coupled to a multiplier MUL1. Memory cell 300B also includes storage unit SU2 coupled to multiplier MUL2, and adder ADD coupled to each of multipliers MUL1 and MUL2.

The storage unit SU1 is used for storing the weight data element WTmn, and the storage unit SU2 is used for storing the weight data element WTm(n+1). In some embodiments, indicator m corresponds to one of the M number of rows C1-CM, and indicator n corresponds to one of the N number of data columns of memory array 120A or 120B.

In various embodiments, the storage units SU1 and SU2 are used to store respective weight data elements WTmn or WTm(n+1), the weight data elements including a single bit or multiple bits. In some embodiments, one or both of the storage units SU1 or SU2 are used to store the corresponding weight data element WTmn or WTm(n+1) comprising a number of bits ranging from 1 to 16. In some embodiments, one or both of the storage units SU1 or SU2 are used to store the corresponding weight data element WTmn or WTm(n+1) comprising a number of bits ranging from 4 to 8. In some embodiments, one or both of the storage units SU1 or SU2 are used to store the corresponding weight data element WTmn or WTm(n+1) comprising a programmable number of bits.

Each of the multipliers MUL1 and MUL2 is used to perform a multiplication operation including a given multiplier MUL1 or MUL2 coupled to The number of bits corresponding to the number of bits of the storage unit SU1 or SU2 is equal. The multiplier MUL1 is used to receive the weight data element WTmn and a first of the k-th bits A1k to ANk denoted Ank in Figures 3A and 3B from the storage unit SU1, and output the product as product data Yuan Pmn.

In some embodiments, such as those in which memory cell 300A is used as memory cell BCX, product data element Pmn based on indicators m and n corresponds to product data element P11 discussed above with respect to FIG. 1A to one of the Pmns. Memory cell 300A is thus used to be able to perform the operations discussed above with respect to memory cell BCX and Figure 1A.

The multiplier MUL2 is used to receive the weight data element WTm(n+1) and the second one of the kth bits A1k to ANk denoted as A(n+1)k in FIG. 3B from the storage unit SU2 , and output the product as the product data element Pm(n+1).

The adder ADD is used to receive each product data element Pmn and Pm(n+1) having a bit number corresponding to the multiplier MUL1 or MUL2, perform an addition operation, and output the sum as having a ratio of each product data element Pmn And the number of bits of Pm(n+1) is greater than the sum data element Sm1 of the number of bits. In some embodiments, indicator 1 corresponds to one of the L number of memory cells BX2 columns of memory array 120B.

In some embodiments, such as those in which memory cell 300B is used as memory cell BX2, the sum data element Sm1 based on indicators m and 1 corresponds to the sum data element discussed above with respect to FIG. 1B One of S11 to Sm1. Memory cell 300B is thus used to be able to perform the operations discussed above with respect to memory cell BX2 and Figure IB.

By including memory cell 300A as one or more instances of memory cell BCX or including memory cell 300B as one or more instances of memory cell BX2, the corresponding memory circuit 100A or 100B can realize the above-described benefits.

Figure 4 is a diagram of an adder tree 400 in accordance with some embodiments. Adder tree 400 may be used as adder tree 122 discussed above with respect to Figures 1A and 1B. The adder tree 400 includes u number of adder layers ADD1 to ADDu.

The first adder layer includes adders ADD1 to receive U(=2 ^u ) number and data elements SUM11 to SUM1U, the first layer thus includes U/2 number of adders ADD1 . In some embodiments, such as those in which adder tree 400 is used as adder tree 122 in rows C1 to CM of memory array 120A, and data elements SUM11 to SUM1U correspond to the Corresponding to a plurality of product data elements output by a row, eg, product data elements P11 through P1N output by row C1 discussed above with respect to FIG. 1A . In some embodiments, such as those in which adder tree 400 is used as adder tree 122 in rows C1 through CM of memory array 120B, and data elements SUM11 through SUM1U correspond to the The plurality of sum data elements output by the corresponding line, eg, the sum data elements S11 through S1L output by line C1 discussed above with respect to FIG. 1B.

Each adder ADD1 is used to pair and receive the corresponding pair of data elements An addition operation is performed (eg, with SUM11 and SUM12 of data elements SUM11 to SUM1U), and the sum is output as a corresponding one of sum data elements SUM21 to SUM2(U/2). The adder ADD1 is used to receive the sum data elements SUM11 to SUM1U, and the sum data elements SUM11 to SUM1U include the first number of bits, eg, the number of bits of the product data elements P11 to PMN discussed above with respect to FIG. 1A bits or the number of bits of sum data elements S11 through SML discussed above with respect to Figure 1B, and the output includes sum data element SUM21 of a second number of bits that is one greater than the first number of bits to SUM2(U/2).

The second adder layer includes U/4 number of adders ADD2. Each adder ADD2 is used to perform an addition operation on the corresponding received pair of the sum data elements (such as SUM21 and SUM22 in the sum data elements SUM21 to SUM2 (U/2)), and output the sum as the sum data elements SUM31 to SUM3 (U /4) in the corresponding one. The adder ADD2 is used for receiving the sum data elements SUM21 to SUM2(U/2) including the second number of bits, and outputting the sum including the third number of bits which is one greater than the second number of bits Data elements SUM31 to SUM3 (U/4).

The final adder layer includes a single adder ADDu to perform an addition operation on a pair of sum data elements SUMu1 and SUMu2 received from the adder of the previous layer, and output the sum as a sum data element SDm. The adder ADDu is used to receive the sum data elements SUMu1 and SUMu2 including the fourth number of bits, and the output includes a fifth bit greater than the fourth number of bits and equal to the first number of bits plus the number u The summation data element SDm of the number of bits. In some embodiments, for example, In those embodiments in which adder tree 400 is used as adder tree 122, summing data element SDm corresponds to one of summing data elements SD1-SDm discussed above with respect to Figures 1A and 1B.

In various embodiments, adder tree 400 includes one or more additional adder layers between the second and last layers depicted in FIG. 4, each additional layer being The configurations of the layers and the last layer are configured so that in the operation, the sum data elements SDm are generated based on the received sum data elements SUM11 to SUM1U. In some embodiments, the adder tree 400 does not include the second adder layer ADD2, and thus includes a total of u=2 layers, such that in operation a sum is generated based on a total of U=4 sum data elements SUM11 to SUM1U Data element SDm.

In some embodiments, the adder tree 400 thus includes a total number of levels ranging from 2 to 9. In some embodiments, the adder tree 400 thus includes a total number of levels ranging from 4 to 7 levels.

Adder tree 400 is thus used to enable the operations discussed above with respect to adder tree 122 and Figures 1A and 1B. By including the adder tree 400 as the adder tree 122, each of the memory circuits 100A and 100B can realize the above-described benefits.

Figure 5 is a diagram of an accumulator 500 in accordance with some embodiments. Accumulator 500, also referred to as partial sum circuit 500 in some embodiments, may be used as accumulator 140 discussed above with respect to Figures 1A and 1B. Accumulator 500 includes an adder ADDA coupled to each of data register R1 and shifter SH1 . The shifter SH1 is also coupled to the data register R1, so that the adder ADDA, the data register R1 and the shifter SH1 are thus in Collective coupling in feedback configuration.

The adder ADDA is used to receive, in operation, the summation data element SDm discussed above with respect to FIG. 4 . In some embodiments, such as those in which accumulator 500 is used as accumulator 140, summation data element SDm corresponds to summation data elements SD1 through SDM discussed above with respect to Figures 1A and 1B one of the.

The adder ADDA is further configured to receive the shifted data element SDE output from the shifter SH1 in operation, and to generate an internal sum data element IDE based on the shifted data element SDE and the summed data element SDm. The data register R1 is used to receive the internal and data element IDE from the adder ADDA, store the internal and data element IDE, and output the stored internal and data element IDE to the shifter SH1 and the output port Om. The shifter SH1 is used to receive the stored internal data element IDE output from the data register R1, and generate the shifted data element SDE by shifting the stored internal data element IDE by one bit in the MSB direction or the LSB direction .

The accumulator 500 is thus configured to perform accumulation operations in response to one or more control signals CTRL received on the control signal bus CTRLB (not shown in Figure 5) such that the stored internal and data elements IDE follow the received data. Each of the sequence of sum data elements SDm is incremented. Thus, an accumulation operation is performed on the multiple instances of the summation data element SDm so that the internal data element IDE stored in the data register R1 outputs on the output port Om as the partial sum of the instances of the summation data element SDm PSm.

In some embodiments, such as those in which accumulator 500 is used as accumulator 140, the partial sum of the output on output port Om PSm corresponds to the portion of the output on corresponding output ports O1-Om discussed above with respect to Figures 1A and 1B and one of PS1-PSM.

Accumulator 500 is thus used to be able to perform the operations discussed above with respect to accumulator 140 and Figures 1A and 1B. By including the accumulator 500 as the accumulator 140, each of the memory circuits 100A and 100B can realize the above-mentioned benefits.

FIG. 6 is a diagram of a portion of a memory array 120A or 120B (120A/120B) in accordance with some embodiments. Figure 6 includes multiple instances of memory cells BCX or BX2 (BCX/BX2) and instances of adder tree 122, each of which is discussed above with respect to Figures 1A and 1B. In the embodiment depicted in FIG. 6, the memory array 120A/120B also includes a multiplexer MA coupled between the memory cells BCX/BX2 and the adder tree 122. Figure 6 is simplified for illustrative purposes.

The multiplexer is used to selectively couple one or more of the memory cells BCX/BX2 to the adder tree 122 such that in operation, data elements output from the memory cells BCX/BX2 (eg, above with respect to Product data elements P11 through PMN or sum data elements S11 through SML, discussed in Figures 1A and 1B, are responsive to one or more control signals CTRL (not shown in Figure 6) received on control signal bus CTRLB ) is selectively propagated to the adder tree 122. In various embodiments, memory cells BCX/BX2 are included in the same row of C1-CM or in separate rows of C1-CM, whereby adder tree 122 is shared between the two rows of C1-CM .

With the configuration discussed above, memory circuit 100A or 100B A memory array 120A/120B is included that includes at least one adder tree 122 shared among a plurality of memory cells BCX/BX2. In this embodiment, the memory circuit 100A or 100B is thus able to use a smaller area to generate sections compared to approaches in which the memory array does not include at least one adder tree shared among multiple memory cells and.

7A and 7B are diagrams of portions of memory circuits 100A or 100B (100A/100B), according to some embodiments. Each of FIGS. 7A and 7B depicts a non-limiting example in which two or more parts and PS1-PSM are combined, and the example is simplified for illustrative purposes.

In the embodiment depicted in Figure 7A, memory circuits 100A/100B include two instances of corresponding memory arrays 120A/120B and accumulators 140, each of which is discussed above with respect to Figures 1A and 1B . In the embodiment depicted in FIG. 7A, output port O2 of the first instance of accumulator 140 is coupled to the second instance of accumulator 140 such that in operation, the partial sum PS2 is received by the second instance of accumulator 140 and Included in the output on output port O1 and in PS1. In some embodiments, two instances of accumulator 140 are used to selectively output partial sums PS1 and PS2 without including partial sum PS2 in partial sum PS1 in an operation, eg, in response to a signal on control signal bus CTRLB One or more control signals CTRL (not shown in FIGS. 7A and 7B ) are received.

In the embodiment depicted in FIG. 7B, memory circuits 100A/100B include each of rows C1-C4 (including corresponding instances of accumulators 140) used to receive inputs in operations Input data elements A1 through AN and output counterparts and PS1 through PS4 on the input data bus IDB, as discussed above with respect to Figures 1A and 1B. In the embodiment depicted in FIG. 7B, the memory circuit 100A/100B also includes an adder ADDSUM for receiving the partial sums PS1 to PS4 in operation and generating a combined partial sum based on the partial sums PS1 to PS4 OSUM. In some embodiments, memory circuit 100A/100B is used to selectively output partial sum PS1 to PS4 without outputting partial sum OSUM in an operation, eg, in response to one or more received on control signal bus CTRLB control signal CTRL.

In each of the non-limiting examples depicted in Figures 7A and 7B, in operation, the partial sum PS1 or OSUM output from memory circuit 100A/100B is based on each input data element A1 through AN and row C1 through AN. A memory cell BCX/BX2 combination in two or more of the CMs. The partial sum PS1 or OSUM is thus generated based on the bits of the combination of weight data elements stored in memory cells BCX/BX2, such that the partial sum PS1 to PSM is based on the input data elements A1 to AN and the cells in rows C1 to CM. The resolution or precision of the partial and PS1 or OSUM is improved compared to the combined embodiments.

In some embodiments, memory cells BCX/BX2 include weight data elements that include a total of four bits, such that in operation, in the embodiment depicted in Figure 7A, the partial sum PS1 is based on the total Eight bits of weight data element output, and in the embodiment depicted in Figure 7B, the partial sum OSUM is based on a total of sixteen bits of weight data element output.

The embodiments depicted in Figures 7A and 7B are non-limiting examples provided for illustrative purposes. In various embodiments, memory circuits 100A/100B are otherwise configured to generate one or more partial sums based on combined stored weight data elements, as compared to embodiments where partial sums are not based on combined weight data elements Improved resolution.

FIG. 8 is a diagram of the operating voltage VDD of a memory circuit according to some embodiments. In the embodiment depicted in FIG. 8, the operating voltage VDD is the supply voltage of the power domain in which the memory circuit 100A or 100B operates, as discussed above with respect to FIGS. 1A and 1B. The working voltage VDD includes three power supply voltage levels of 0V, VDD1 and VDD2. Among the three voltage voltage levels, the power supply voltage level VDD1 is greater than the power supply voltage level VDD2. The voltage levels and timing relationships, such as relative durations and/or intensities and sequences depicted in Figure 8, are non-limiting examples provided for illustrative purposes.

A power supply voltage level of 0V indicates a power-down mode in which no memory circuit operations are performed. In some embodiments, memory array 120A or 120B includes storage cells SU1 and SU2 (if present), which include non-volatile memory cells such that weight data elements WTmn and/or WTm(n+1) One or more durations with a voltage level of 0V at the operating voltage VDD are retained.

The supply voltage level VDD1 represents the I/O mode during which one or more weight elements WTmn and/or WTm(n+1) are stored in memory cells BCX and/or in one or more write operations BX2, and/or accessed in one or more read operations.

The power supply voltage bit VDD2 indicates the operation mode, during this mode During this time, operations of one or more in-memory operations are performed, as discussed above with respect to FIGS. 1A and 1B and/or as discussed below with respect to methods 900 and 1000 .

In the embodiment depicted in Figure 8, by performing in-memory operations at a supply voltage level less than the supply voltage level of VDD1, VDD2, the memory is performed in an operation mode with the same voltage level as the I/O mode. Compared with the in vivo computing method, the power consumption is reduced.

FIG. 9 is a flowchart of a method 900 of operating a memory circuit in accordance with some embodiments. The method 900 may be used with a memory circuit, such as the memory circuit 100A or 100B discussed above with respect to Figures 1A and 1B.

The sequence of operations of method 900 depicted in FIG. 9 is for illustration only; the operations of method 900 can be performed concurrently or in a different sequence than depicted in FIG. 9 . In some embodiments, operations other than those depicted in FIG. 9 are performed before, between, during, and/or after the operations depicted in FIG. 9 . In some embodiments, the operating method of method 900 is a subset of the method of operating an IC (eg, a sensor, RF device, processor, logic or signal processing circuit, or the like). In various embodiments, one or more operations of method 900 are subsets of method 1000 discussed below with respect to FIG. 10 .

Method 900 is a non-limiting example of a partial sum calculation, where an instance PSm of the partial sums PS1-PSM is calculated for the corresponding m-th one of rows C1-CM, as discussed above with respect to FIGS. 1A-5 . In the embodiment depicted in Figure 9, the counter k loops between each of the H number of bits of each of the input data elements A1 to AN. At each value of counter k, corresponding to the instance of summed data elements SD1 through SDM, summed data element _Pk is computed as the sum of the N number of products corresponding to the kth bit and weight data element Wmn. The partial sum PSm is generated from the accumulated data elements _Pk , as described below.

At operation 910, the counter k is initialized to zero. In some embodiments, initializing the counter k includes using the control circuit 150 discussed above with respect to FIGS. 1A-5 .

In some embodiments, initializing the counter k to zero includes setting the contents of one or more data registers to zero. In some embodiments, initializing counter k to zero includes setting the internal data element IDE of data register R1 to zero, as discussed above with respect to accumulator 500 and FIG. 5 .

At operation 920, the counter k is incremented by one, and a summation data element Pk is generated based on the value of the counter _k . Generating summed data elements _Pk includes summing product data elements corresponding to each of the N data columns in memory array 120A or 120B over a range defined from n=1 to N. Each nth product data element is multiplied by the kth bit Ank of the input data element An corresponding to the counters n and k by the corresponding weight data element Wmn or Wm(n+1). The resulting product data elements are summed over the range of n=1 to N, thereby producing summed data elements _Pk corresponding to instances of summed data elements SD1 to SDM.

In some embodiments, generating the summation data element _Pk includes using the adder tree 122 corresponding to the mth one of rows C1 to CM over the range of n=1 to n=N to output by memory cell BCX The product data elements Pmn of are summed as discussed above with respect to memory circuit 100A and Figures 1A-5. In some embodiments, generating summation data element _Pk includes generating summation data elements Sm1-SmL over a range of 1=1 to 1=L using memory cell BX2, and using memory cell BX2 corresponding to the first in rows C1-CM M's adder tree 122 sums the sum-product data elements Sm1-SmL output by memory cell BX2, as discussed above with respect to memory circuit 100B and FIG. 1 .

At operation 930, the partial sum data element _Ok is generated based on the value of the counter k. Generating the partial sum data element _Ok includes initializing the partial sum data element _Ok to the first value of the sum data element P _k when the counter k has a value of 1, and when the counter k has a value other than 1, shifting the data element The previous value of O _k (O _k-1 ) is added to the current value of the summing data element P _k .

Shifting the part and the previous value of the data element _Ok corresponds to increasing or decreasing the previous value by one significant bit. In some embodiments, incrementing counter k from 1 to H corresponds to incrementing the valid bits of input data elements A1 through AN, and shifting the portion and the previous value of data element _Ok corresponds to incrementing the previous value by a valid bit bits, that is, multiply the previous value by 2. In some embodiments, incrementing counter k from 1 to H corresponds to decrementing the valid bits of input data elements A1 through AN, and shifting the portion and the previous value of data element _Ok corresponds to decrementing the previous value by a valid bit bits, that is, divide the previous value by 2.

In some embodiments, generating the partial sum data elements _Ok includes setting the partial sum data elements PS1 to PSM as the first instance of the corresponding summed data elements SD1 to SDM by: storing the corresponding summed data elements SD1 to SDM The first instance of is the internal data element IDE in data register R1, shifter SH1 is used to shift the internal data element IDE, and subsequent instances of summed data elements SD1 to SDM are added with the shifter data element SDE , as discussed above with respect to Figures 1A-5.

At operation 940, the counter k is compared to the number H. If counter k is less than number H, method 900 returns to operation 920; and if counter k is equal to number H, method 900 continues with operation 950.

給出，其中計數器k=1對應於一LSB及係數2⁰，及計數器k=4對應於一MSB及係數2³。 At operation 950, part sum data element PSm is set to the final value of part sum data element Ok corresponding to counter _k =H. In some embodiments, number H=4, incrementing counter k corresponds to incrementing the valid bits of input data elements A1 to AN, and setting part sum data element PSm to the final value of part sum data element _Ok , given by PSm=

is given where counter k=1 corresponds to one LSB and coefficient 2 ⁰ , and counter k=4 corresponds to one MSB and coefficient 2 ³ .

In some embodiments, setting part and data element PSm to the final value of part and data element _Ok includes outputting the mth part and data element PS1 to PSM on the corresponding mth output port O1 to OM, as described above with respect to the th 1A to 5 discussed.

The benefits discussed above with respect to memory circuits 100A and 100B are achieved by using memory circuit 100A or 100B to perform some or all of the operations of method 900, in part and based on in-memory operations.

FIG. 10 is a method of operating a memory circuit according to some embodiments. Flowchart of Law 1000. The method 1000 may be used with a memory circuit, such as the memory circuit 100A or 100B discussed above with respect to Figures 1A and 1B.

The sequence of operations of method 1000 depicted in FIG. 10 is for illustration only; the operations of method 1000 can be performed in a different sequence than that depicted in FIG. 10 . In some embodiments, operations other than those depicted in FIG. 10 are performed before, between, during, and/or after the operations depicted in FIG. 10 . In some embodiments, the operating method of method 1000 is a subset of the method of operating an IC (eg, a sensor, RF device, processor, logic or signal processing circuit, or the like). In some embodiments, the operations of method 1000 operate on a subset of CNN or other neural network-like methods.

At operation 1010, in some embodiments, the first weight data element is stored in each memory cell of a row of memory cells. In some embodiments, storing the first weight data element in each memory cell of the row of memory cells includes storing the weight data in the plurality of rows of memory cells. In various embodiments, storing the first weight data element in each memory cell of each memory cell row includes using the I/O circuit 130 to store the weight data element WTmn and/or WTm(n+1) in rows C1 to In the memory cell BCX or BX2 of the CM, as discussed above with respect to Figures 1A-5.

In some embodiments, storing the first weighted data element in each memory cell of the row of memory cells includes at a first power supply voltage level that is greater than a second power supply voltage level at which some or all of operations 1020-1070 are performed Operates memory circuits. In some embodiments, operating the memory circuit at the first supply voltage level includes operating at the supply voltage level VDD1 Making the memory circuit, and operating the memory circuit at the second supply voltage level includes operating the memory circuit at the supply voltage level VDD2, as discussed above with respect to FIG. 8 .

At operation 1020, in some embodiments, a set of kth bits of the H bits of each input data element of the plurality of input data elements is output simultaneously from the selection circuit. In some embodiments, simultaneously outputting the set of the kth bit of the H bits of each of the input data elements includes outputting the kth bit of the input data elements A1 to AN from the selection circuit 110 The set of elements A1k through ANk, as discussed above with respect to Figures 1A-5.

In various embodiments, simultaneously outputting the kth bit set of the H bits of each of the input data elements is performed by sequentially outputting the kth bit from LSB to MSB or from MSB to LSB in increasing order. part of a set of k bits.

In some embodiments, simultaneously outputting the kth set of H bits of each of the input data elements includes receiving the input data elements at a selection circuit. In some embodiments, simultaneously outputting the k-th set of the H bits of each of the input data elements includes storing the input data elements in a selection circuit, eg, in a or multiple data registers. In some embodiments, simultaneously outputting the kth set of bits of each of the input data elements includes receiving and storing the input data elements using the selection circuit 110 discussed above with respect to Figures 1A and 1B A1 to AN. In some embodiments, the set of k-th bits of each of the input data elements is output simultaneously The combination includes using the selection circuit 200 discussed above with respect to FIG. 2 .

In some embodiments, simultaneously outputting the kth set of H bits of each of the input data elements includes generating and responding to one or more control signals, eg, by the above One or more control signals CTRL generated by the control circuit 150 discussed herein with respect to FIGS. 1A-5.

In some embodiments, simultaneously outputting the kth set of H bits of each of the input data elements includes performing some or all of the method 900 discussed below with respect to FIG. 9 .

At operation 1030, the kth set of bits is received at a row of memory cells. In various embodiments, receiving the kth set of bits at the row of memory cells includes receiving the kth set of bits Alk through ANk at the row of memory cells BCX or BX2.

In some embodiments, receiving the kth set of bits at the row of memory cells includes receiving the kth set of bits at each of the plurality of rows. In various embodiments, receiving the k-th set of bits at the rows includes receiving the k-th bits A1k-ANk at each of rows C1-CM discussed above with respect to FIGS. 1A-5 collection.

In some embodiments, receiving the kth set of bits at the memory cell row includes performing some or all of the method 900 discussed below with respect to FIG. 9 .

At operation 1040, each memory cell of the memory cell row is used to multiply the kth bit of the corresponding input data element by the first weight data element stored in the memory cell, thereby generating a corresponding first product data element. In various embodiments, multiplying the kth bit corresponding to the input data element by the first weight data element stored in the memory cell using the memory cell includes multiplying the kth bit using the memory cell BCX or BX2 A1k through ANk are multiplied by the first weight data element, as discussed above with respect to FIGS. 1A through 5 .

In some embodiments, the kth bit corresponding to the input data element is multiplied by the first weight data element stored in the memory unit to thereby generate the corresponding first product data element, including multiplying the bit Ank with the weight data The elements WTmn are multiplied thereby resulting in a product data element Pmn, as discussed above with respect to memory cells 300A and 300B and Figures 3A and 3B.

In some embodiments, each memory cell using a row of memory cells multiplies the kth bit of the corresponding input data element among the data elements by the first weight data element, including using each memory cell of the row of memory cells. The memory unit multiplies the k-th bit of another corresponding input data element among the data elements by the second weight data element stored in the memory unit, thereby generating a second product data element, and multiplying the k-th data element A product data element is added with a second product data element to generate a sum data element.

In some embodiments, the k-th bit of another corresponding input data element of the data elements is multiplied by the second weight data element stored in the memory unit, thereby generating a second product data element, and Summing the first product data element and the second product data element to generate the sum data element, including multiplying the bit A(n+1)k by the weight data element WTm(n+1), thereby producing the product data element Pm (n+1), and the product data element Pmn and the product data element Pm(n+1) are added to generate the above for memory cells 300B and 3B Figure discusses and data element Sm1.

In various embodiments, multiplying the kth bit corresponding to the input data element by the first weight data element stored in the memory cell using a memory cell, including using a plurality of memory cell rows (eg, above, Rows C1 through CM) discussed with respect to Figures 1A through 5 multiply the kth bit A1k through ANk of the corresponding input data element by a corresponding first weight data element of the plurality of first weight data elements.

In various embodiments, multiplying the kth bit corresponding to the input data element by the first weighted data element stored in the memory cell using the memory cell row includes generating and responding to one or more control signals, such as , one or more control signals CTRL generated by the control circuit 150 discussed in FIGS. 1A-5 above.

In some embodiments, multiplying the kth bit of the corresponding input data element by the first weight data element stored in the memory cell using the memory cell row includes performing some of the method 900 discussed below with respect to FIG. 9 or all.

At operation 1050, the adder tree is used to generate a summation data element based on each of the first product data elements. In some embodiments, using the adder tree to generate the summation data elements based on each of the first product data elements includes using the adder tree 122 based on the product data elements Pmn and/or the product data elements Pmn discussed above with respect to FIGS. 1A-5. Or Pm(n+1) yields instances of summed data elements SD1 to SDM.

In some embodiments, using the adder tree to generate the summation data element includes using the adder tree 400 discussed above with respect to FIG. 4 .

In some embodiments, generating a summation data element using an adder tree includes generating a plurality of summation data elements using a plurality of adder trees, eg, summation data elements SD1 through as discussed above with respect to FIGS. 1A through 5 SDM.

In some embodiments, generating the summation data element using the adder tree includes receiving the first product data element at the adder tree. In some embodiments, receiving the first product data element at the adder tree includes receiving the product data element P11 through PMN at the adder tree 122, as discussed above with respect to FIGS. 1A-5.

In some embodiments, generating the sum data element using the adder tree includes receiving the sum data element at the adder tree. In some embodiments, receiving the sum data elements at the adder tree includes receiving the sum data elements S11 through SML at the adder tree 122, as discussed above with respect to FIGS. 1A-5.

In some embodiments, using the adder tree to generate the summation data element includes coupling the adder tree to selected memory cells using a multiplexer, eg, using the multiplexer MA discussed above with respect to FIG. 6 .

In some embodiments, generating a summation data element based on each of the first product data elements using the adder tree includes generating and responding to one or more control signals, eg, as described above with respect to FIGS. 1A-5 One or more control signals CTRL are generated by the control circuit 150 discussed in FIG.

In some embodiments, generating a summation data element based on each of the first product data elements using the adder tree includes performing some or all of the method 900 discussed below with respect to FIG. 9 .

At operation 1060, the accumulator is used to generate based on the summed data elements part and. In some embodiments, generating the partial sums based on the summed data elements using the accumulator includes generating the partial sums PS1 through PSM based on the corresponding summed data elements SD1 through SDM using the accumulator 140 , as discussed above with respect to FIGS. 1A through 5 .

In some embodiments, generating the partial sum using the accumulator includes adding a first summed data element to a second summed data element stored in a data register and shifted by a shifter. In some embodiments, adding the first summed data element to the second summed data element is synchronized with the selection circuit to sequentially output the kth bit set. In some embodiments, generating the partial sum using the accumulator includes generating the partial sum PSm using the accumulator 500 , as discussed above with respect to FIG. 5 .

In some embodiments, using an accumulator to generate a partial sum based on summing data elements includes generating a plurality of parts and data elements using a plurality of accumulators, eg, as discussed above with respect to FIGS. 1A-5 , the partial sum data element PS1 to PSM.

In some embodiments, generating the partial sums using the accumulators includes generating the first partial sums based on the second partial sums generated by the second accumulators using a first accumulator, eg, using a first instance of the accumulator 140 based on Partial Sum PS2 produces Partial Sum PS1, as discussed above with respect to Figure 7A.

In some embodiments, generating the partial sums using the accumulators includes generating a partial sum based on the partial sums generated by the accumulators using an adder, eg, generating the partial sums based on the partial sums PS1 to PS4 using the adder ADDSUM section and OSUM, as discussed above with respect to Figure 7B.

In some embodiments, generating a partial sum based on summed data elements using an accumulator includes generating and responding to one or more control signals, eg, generated by the control circuit 150 discussed above with respect to FIGS. 1A-5 . One or more control signals CTRL.

In some embodiments, generating a partial sum based on summing data elements using an accumulator includes performing some or all of the method 900 discussed below with respect to FIG. 9 .

At operation 1070, in some embodiments, some or all of operations 1010-1060 are repeated. In some embodiments, repeating some or all of operations 1010-1060 includes synchronizing the performance of some or all of operations 1010-1060. In some embodiments, repeating some or all of operations 1010-1060 includes incrementing a counter, eg, counter k discussed above with respect to FIGS. 1A-9. In some embodiments, repeating some or all of operations 1010-1060 includes generating one or more control signals, eg, using control circuit 150 to generate one or more of control signals CTRL, as described above with respect to FIGS. 1A-5 discussed in the figure.

In some embodiments, repeating some or all of operations 1010-1060 includes performing some or all of method 900 discussed above with respect to FIG. 9 .

In some embodiments, repeating some or all of operations 1010-1060 includes generating a partial sum based on the H summed data elements using an accumulator, eg, using accumulator 140 based on H instances of the corresponding summed data elements SD1-SDM Partial sums PS1 through PSM are generated as discussed above with respect to Figures 1A through 5 .

In some embodiments, repeating some or all of operations 1010-1060 includes sequentially multiplying the k-th set of bits output by the selection circuit with the corresponding first weight data element, thereby generating a plurality of first product data elements For example, the first product data element Pmn discussed above with respect to Figures 3A and 3B.

In some embodiments, repeating some or all of operations 1010-1060 includes sequentially multiplying the k-th set of bits output by the selection circuit with the corresponding second weight data element, thereby generating a plurality of second product data elements For example, the second product data element Pm(n+1) discussed above with respect to Figure 3B.

In some embodiments, repeating some or all of operations 1010-1060 includes using an adder tree to generate H summation data based on the first product data elements, and in some embodiments further based on the second product data elements Yuan.

In some embodiments, the input data elements are the first plurality of input data elements in the set of the plurality of input data elements, and repeating some or all of operations 1010-1060 includes sequentially receiving the set of the plurality of input data elements each of the plurality of input data elements in , and performing some or all of operations 1010-1060 to generate one or more based on each of the plurality of input data elements in the set of the plurality of input data elements and the single plurality of weight data elements part and.

By performing some or all of the operations of method 1000, a partial sum is generated based on in-memory operations, thereby realizing the benefits discussed above with respect to memory circuits 100A and 100B. based on multiple input data elements In embodiments where each plurality of input data elements and a single plurality of weight data elements in a set generate one or more partial sums, a method for partial sum operations with a single plurality of weight data elements not duplicated in multiple memories In contrast, the power level is further reduced.

In some embodiments, the memory circuit includes a means to receive a plurality of input data elements (each of the input data elements includes a number of bits equal to N) and output each of the input data elements A selection circuit of the selected set of the kth bit of the H bits of the data element, the memory cell row (each memory cell of the memory cell row includes a first storage for storing the first weight data element unit and a first multiplier to generate a first product data element based on the first weight data element and the first kth bit in the selected set of the kth bit) and to generate a first product data element based on the first product data Each of the elements produces an adder tree that sums the data elements. In some embodiments, the first weight data element is a multi-bit data element. In some embodiments, each memory cell of a row of memory cells includes a second storage cell for storing a second weight data element in a selected set based on the second weight data element and the kth bit The second k-th bit of the second multiplier for generating the second product data element, and the adder for generating the sum data element from the first and second product data elements, wherein the adder tree is used based on the sum data element Each of them produces a summation data element. In some embodiments, the summation data element is a summation data element among the H summation data elements, and the selection circuit is configured to sequentially output the kth bit from the first bit to the Hth bit. a set, an adder tree for generating each of the H summed data elements based on the set of sequentially outputting the kth bit, and a memory circuit included for generating based on the H summed data elements Accumulator for partial sums. In some embodiments, the memory circuit includes a control circuit for generating one or more control signals received by the selection circuit and the accumulator, whereby the memory circuit is used for sequentially outputting the kth signal in synchronization with the selection circuit A collection of bits yields a partial sum. In some embodiments, a row of memory cells is one of a plurality of rows of memory cells, each row of memory cells being used to receive a selected kth bit of the H bits of the plurality of bits A set of adder trees; an adder tree is an adder tree among a plurality of adder trees, and the adder tree is coupled to a corresponding row among the rows of memory cells; an accumulator is an accumulator among a plurality of accumulators, accumulating The accumulators are coupled to corresponding ones of the adder trees, and each of the accumulators is used to generate corresponding ones based on the H summation data elements generated by the corresponding ones of the adder trees part and. In some embodiments, at least one of the accumulators is used to generate a corresponding partial sum based on a partial sum generated by another of the accumulators. In some embodiments, each first storage unit includes an SRAM device for storing some or all of the first weight data elements. In some embodiments, the memory circuit includes an I/O circuit for storing each first weight data element in a corresponding first storage unit.

In some embodiments, a method of operating a memory circuit includes receiving, at a row of memory cells, a set of kth bits of the H number of bits for each of the input data elements; using the memory Each memory cell of the cell row multiplies the kth bit of the corresponding input data element among the data elements by the first weight data element stored in the memory cell, thereby generating the corresponding first product data element; and using an adder tree based on the first product The owners of the data elements generate the summed data elements. In some embodiments, using each memory cell of the row of memory cells to multiply the kth bit of the corresponding input data element of the data elements by the first weight data element includes using each memory of the row of memory cells The volume unit multiplies the k-th bit of another of the data elements corresponding to the input data element by the second weight data element stored in the memory unit, thereby generating a second product data element, and multiplying the first product The data elements are added with the second product data elements to generate sum data elements, wherein the use of the adder tree to generate the summed data elements is based on each of the corresponding sum data elements. In some embodiments, the method includes sequentially outputting a set of kth bits of the H bits of each of the input data elements using a selection circuit, and summing the data based on the H data using an accumulator generating a partial sum of elements, wherein each memory cell using a row of memory cells multiplies the kth bit of the input data element among those data elements by the first weight data element including multiplying each kth bit with the first weight data element A weight data element is sequentially multiplied, thereby generating a plurality of first product data elements; and generating a summation data element based on each of the first product data elements using an adder tree includes using an adder tree based on the first products The data element produces H summed data elements. In some embodiments, receiving the kth bit of each of the input data elements includes receiving the kth set of bits at each of the plurality of memory cell rows; using memory Multiplying the kth bit by the first weight data element by each memory cell of the row of memory cells includes storing the kth bit with the memory cell of each row of memory cells in the row of memory cells. Corresponding first weight data elements in the memory cells are multiplied, thereby generating corresponding first product data elements; using the adder tree to generate summation data elements includes using complex numbers based on the first product data elements generating a plurality of summation data elements; and generating a partial sum using the accumulators includes generating a plurality of partial sums based on the corresponding H summation data elements using the plurality of accumulators. In some embodiments, generating the partial sums using the accumulators includes generating the first partial sums using the first accumulator based on the second partial sum generated by the second accumulator. In some embodiments, generating the partial sum using an accumulator includes adding a first summed data element to a second summed data element stored in a data register and shifted by a shifter, and adding the first summed data element The addition of the sum data element to the second summed data element is synchronized with the selection circuit to sequentially output the set of kth bits. In some embodiments, using the selection circuit to sequentially output the set of kth bits of the H bits of each of the input data elements includes outputting the set of kth bits from LSB to MSB . In some embodiments, the method includes storing the first weighted data element in each memory cell of a row of memory cells based on a first supply voltage level, wherein the kth bit cell is stored using each memory cell of the row of memory cells Each of multiplying the first weight data element and generating the summing data element using the adder tree is based on a second supply voltage level that is lower than the first supply voltage level.

In some embodiments, the memory circuit includes a selection circuit for sequentially outputting the selected set of kth bits to the plurality of memories for the plurality of input data elements each comprising H bits Corresponding memory cells of each memory cell row in the memory cell row; a plurality of adder trees, each adder tree in the adder trees is coupled to a corresponding memory cell row in the memory cell rows; and a plurality of accumulators, each of the accumulators is coupled to a corresponding adder tree of the adder trees. Each memory cell of each memory cell row includes a multiplier for Corresponding kth bits in the selected set of kth bits and weight data elements stored in memory cells generate product data elements; each of the adder trees is used for the kth Each sequential output set of bits generates a summation data element based on each of the product data elements corresponding to the row of memory cells; and each of the accumulators is used to generate a summation data element based on each of the accumulators in the adder tree based on the corresponding ones in the adder tree. The summation data elements produced by the adder tree produce partial sums. In some embodiments, each of the adder trees includes a first adder for receiving first and second sum data elements and outputting a result having a first number of bits sum data elements; and second and third adders for outputting first and second sum data elements, first and second sum data elements based on product data elements corresponding to the row of memory cells Each of has a second number of bits that is one less than the first number of bits. In some embodiments, at least one of the adder trees is coupled to a corresponding one of the rows of memory cells via a multiplexer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. It should be appreciated by those skilled in the art that those skilled in the art may readily use the present disclosure as a design or modification for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Advantages of other processes and the basis of structure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes herein without departing from the spirit and scope of the present disclosure , replacement and modification.

1000: Method

1010: Operation

1020: Operations

1030: Operation

1040: Operation

1050: Operation

1060:Operation

1070:Operation

Claims (10)

A memory circuit includes: a selection circuit for receiving a plurality of input data elements, each of the input data elements including a number of bits equal to H, and outputting each of the input data elements a selected set of kth bits of the H bits of the input data element; a row of memory cells, each memory cell of the row of memory cells comprising: a first storage unit for storing a first weight data element; and a first multiplier for generating a corresponding first kth bit based on the first weight data element and the selected set of kth bits first product data elements; and an adder tree for generating a summation data element based on each of the first product data elements. The memory circuit of claim 1, wherein each memory cell of the memory cell row further comprises: a second storage unit for storing a second weight data element; a second multiplier for based on the second weight data element and a plurality of kth A corresponding second kth bit in the selected set of bits generates a second product data element; and an adder for generating from the first product data element and the second product data element A sum data element, wherein the adder tree is used to generate the sum data element based on each of the sum data elements. The memory circuit of claim 1, wherein the summation data element is a summation data element among H summation data elements, and the selection circuit is used to select from a first bit to an Hth bit element sequentially outputs a plurality of sets of k-th bits, the adder tree is used to generate each of the H summation data elements based on the sets of outputs of a plurality of k-th bits in sequence, and the memory The bulk circuit further includes an accumulator for generating a partial sum based on the H summed data elements. A method of operating a memory circuit, comprising: receiving a set of a plurality of kth bits of H number of bits of each input data element in a plurality of input data elements at a memory cell row; using the Each memory cell of a memory cell row associates the The k-th bit of a corresponding input data element is multiplied by a first weight data element stored in the memory unit to generate a corresponding first product data element; and an adder tree is used based on the k-th data elements Each of a product data element yields a summation data element. The method of claim 4, wherein each memory cell using the memory cell row multiplies the kth bit of the corresponding input data element among the data elements by the first weight data element Including using each memory cell of the memory cell row to perform the following operation: associate the kth bit of another corresponding input data element among the data elements with a second weight stored in the memory cell multiplying data elements to generate a second product data element; and adding the first product data element and the second product data element to generate a sum data element, wherein the summation data element is generated using the adder tree is based on each of these correspondences and data elements. The method of claim 4, further comprising: using a selection circuit to sequentially output each input data element in the input data elements a plurality of sets of a plurality of kth bits of the H bits of the element; and generating a partial sum based on the H summed data elements using an accumulator, wherein the use of each memory of the row of memory cells The unit multiplying the k-th bit of the corresponding input data element among the data elements by the first weight data element includes: sequentially multiplying each k-th bit by the first weight data element, to generate a plurality of first product data elements; and the generating the summation data elements based on each of the first product data elements using the adder tree includes: using the adder tree based on the first product data elements The H summation data elements are generated. The method of claim 4, further comprising: storing the first weighted data element in each memory cell of the memory cell row based on a first supply voltage level, wherein the using the memory cell row Each of the memory cells of the multiplication of the k-th bit by the first weight data element and the use of the adder tree to generate the summed data element is based on a voltage below the first supply voltage level a second power supply voltage level. A memory circuit, comprising: a selection circuit for sequentially outputting a plurality of selected sets of a plurality of kth bits to a plurality of memory cells for a plurality of input data elements each including H bits a plurality of corresponding memory cells of each row of memory cells in a row; a plurality of adder trees, each of the adder trees being coupled to a corresponding row of memory cells of the rows of memory cells and a plurality of accumulators, each of the accumulators is coupled to a corresponding one of the adder trees, wherein each memory cell of each row of memory cells includes a multiplier that multiplies A device for generating a product data element based on the corresponding k-th bit in the selected set of k-th bits and a weight data element stored in the memory cell, in the adder tree Each adder tree of is used to generate a summation data element based on each of the product data elements of the corresponding row of memory cells for each set of sequential outputs of a plurality of kth bits, and the Each of the accumulators is used to generate a partial sum based on the summation data elements generated by the corresponding one of the adder trees. The memory circuit of claim 8, wherein each of the adder trees comprises: a first adder for receiving a first sum data element and a second sum data elements, and output the summed data elements having a first number of bits; and a second adder and a third adder for use based on the corresponding The product data elements of the row of memory cells output the first sum data element and the second sum data element, each of the first sum data element and the second sum data element having a number greater than the first sum data element A second bit number less than one bit. The memory circuit of claim 8, wherein at least one of the adder trees is coupled to the corresponding one of the rows of memory cells via a multiplexer.

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