CN112071347B

CN112071347B - Operation method of resistive random access memory, control method of memory device and memory device

Info

Publication number: CN112071347B
Application number: CN202010933272.2A
Authority: CN
Inventors: 高滨; 席悦; 陈俊任; 吴华强; 唐建石; 钱鹤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2020-09-08
Filing date: 2020-09-08
Publication date: 2024-01-16
Anticipated expiration: 2040-09-08
Also published as: CN112071347A

Abstract

A method for operating a resistive random access memory, a method for controlling a memory device, and a memory device are provided. The operation method of the resistive random access memory comprises the following steps: performing a write operation on the resistive random access memory; performing a delay operation after the write operation, wherein the delay operation is continued for a predetermined time to delay; and performing delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of obtaining the current stored value of the resistance random access memory and judging whether the difference between the current stored value and the target value of the resistance random access memory is within a preset error range. The method for operating the resistive random access memory can improve the reliability of the storage value stored by the resistive random access memory and improve the accuracy of the calculation result of the resistive random access memory in the calculation application.

Description

Operation method of resistive random access memory, control method of memory device and memory device

Technical Field

Embodiments of the present disclosure relate to a method of operating a resistive random access memory, a method of controlling a memory device, and a memory device.

Background

The resistive random access memory (Resistive Random Access Memory, RRAM) has the advantages of non-volatility, low power consumption, high calculation speed, good micro characteristic and the like, so that the resistive random access memory has good application prospect in the fields of artificial intelligence, neural networks, memories and the like.

However, due to the relaxation phenomenon of the resistive random access memory itself, the resistive random access memory may be unstable, thereby changing the stored memory value and affecting the accuracy of the calculation result of the resistive random access memory in the computing application.

Disclosure of Invention

At least one embodiment of the present disclosure provides a method of operating a resistive random access memory, including: performing a write operation on the resistive random access memory; performing a delay operation after the write operation, wherein the delay operation is continued for a predetermined time to delay; and executing delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of obtaining the current stored value of the resistance random access memory and judging whether the difference between the current stored value and the target value of the resistance random access memory is within a preset error range.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: if the judgment result of the delay verification operation is negative, continuing to execute the write operation, the delay operation and the delay verification operation; or if the judgment result of the delay verification operation is yes, ending the operation method.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: performing a pre-verify operation on the resistive random access memory after the write operation and before the delay operation, wherein the pre-verify operation comprises: acquiring a current storage value of the resistance random access memory; and judging whether the difference between the current stored value of the resistance change memory and the target value is within the preset error range.

For example, in the operation method provided in an embodiment of the present disclosure, performing a delay operation after the write operation includes: if the judgment result of the pre-verification operation is negative, the write operation and the pre-verification operation are sequentially executed on the resistive random access memory after the pre-verification operation until the judgment result of the pre-verification operation is positive; and if the judgment result of the pre-checking operation is yes, executing the time delay operation on the resistance random access memory.

For example, in the operation method provided in an embodiment of the present disclosure, the operation method further includes ending the operation method if the determination result of the pre-verification operation is yes and the determination result of the delay verification operation is yes.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes performing a pre-read operation on the resistive random access memory before the write operation; wherein the pre-read operation includes: reading the current storage value of the resistance random access memory; and determining a write pulse adopted by the write operation according to the current stored value of the resistance change memory.

For example, in the operation method provided in an embodiment of the present disclosure, obtaining the current stored value of the resistive random access memory includes: applying a read voltage to the resistive random access memory; acquiring a current value output by the resistance random access memory under the action of the reading voltage; and determining a current storage value of the resistive random access memory according to the current value and the read voltage.

For example, in the operation method provided in an embodiment of the present disclosure, the value range of the predetermined time is 1ms to 10s.

At least one embodiment of the present disclosure provides a control method of a memory device, wherein the memory device includes a plurality of resistive random access memories, the control method including: performing an operation method on at least part of the plurality of resistive random access memories, respectively, the operation method comprising: performing a write operation on the resistive random access memory; performing a delay operation after the write operation, wherein the delay operation is continued for a predetermined time to delay; and executing delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of obtaining the current stored value of the resistance random access memory and judging whether the difference between the current stored value and the target value of the resistance random access memory is within a preset error range.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: performing a read-ahead operation on the resistive random access memory prior to the write operation; the pre-reading operation comprises the step of reading the current stored value of the resistance change memory; and determining a write pulse adopted by the write operation according to the current stored value of the resistance change memory.

For example, in an operation method provided in an embodiment of the present disclosure, the performing the operation method on at least some of the plurality of resistive random access memories includes: determining a first sequence of operations on the at least partial resistive switching memory; sequentially performing the write operations to the at least partial resistive random access memories according to the first operation sequence, wherein after the write operation performed to a first resistive random access memory in the at least partial resistive random access memories is finished, performing the delay operation to the first resistive random access memory, performing the write operation to a second resistive random access memory in the at least partial resistive random access memory, and the like, completing the write operation to the at least partial resistive random access memory; during a write operation performed on a last one of the at least partial resistive random access memories, performing the delay verification operation on a first one of the at least partial resistive random access memories; and after the delay verification operation of the first resistance random access memory is finished, executing the delay verification operation on the second resistance random access memory, and the delay verification operation on the at least part of resistance random access memories is finished by the same method.

For example, in an operation method provided in an embodiment of the present disclosure, the performing the operation method on at least some of the plurality of resistive random access memories includes: dividing the plurality of resistive random access memories into N memory blocks, each of the N memory blocks including at least one resistive random access memory; selecting N memory blocks from the N memory blocks, and determining a second order of operation of the N memory blocks; and sequentially executing the operation method on the N memory blocks according to the second operation sequence, wherein the operation method is executed by the at least one resistive random access memory in each memory block in parallel, N is an integer greater than or equal to 2, and N is an integer less than or equal to 2 and less than or equal to N.

For example, in an operation method provided in an embodiment of the present disclosure, the determining the n memory blocks according to the second operation order as a first-level memory block, a second-level memory block, …, and an nth-level memory block, respectively, and sequentially performing the operation method on the n memory blocks according to the second operation order includes: performing the write operation to a resistive random access memory in the first level memory block; after the writing operation of the resistive random access memory in the first-stage memory block is finished, executing the delay operation on the first-stage memory block, executing the writing operation on the resistive random access memory in the second-stage memory block, and completing the writing operation of the n memory blocks by analogy; in the process of executing the writing operation on the n memory blocks, executing the delay verification operation on all the resistance random access memories in the first-stage memory block; and after the delay verification operation of the resistive random access memory in the first-stage memory block is finished, executing the delay verification operation on the resistive random access memory in the second-stage memory block, and the delay verification operation of the n memory blocks is finished in a similar way.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: performing a read-ahead operation on the resistive random access memory prior to the write operation; the pre-reading operation comprises the step of reading the current stored value of the resistance change memory; determining a write pulse adopted by the write operation according to the current stored value of the resistance random access memory; the method for sequentially executing the operation method on the n memory blocks according to the second operation sequence comprises the following steps: performing the pre-read operation on the resistive random access memory in the first level memory block; after the pre-reading operation of the resistive random access memory of the first-stage memory block is finished, executing the pre-reading operation on the resistive random access memory of the second-stage memory block, and finishing the pre-reading operation of the n memory blocks by analogy; performing the write operation on a (k+1) -th-level memory block during the pre-read operation on the (k+1) -th-level memory block, and performing a delay operation on the (k) -th-level memory after the write operation on the (k+1) -th-level memory block is completed; after the pre-read operation of an nth stage memory block of the n memory blocks is completed, performing the delay verification operation on a resistive random access memory in the first stage memory block, and performing the write operation on the nth stage memory block; and after the delay verification operation of the first-stage memory block is finished, executing the delay verification operation on the resistance random access memory in the second-stage memory block, and the delay verification operation of the n memory blocks is finished by the same, wherein k is more than or equal to 1 and less than or equal to n-1.

For example, in the operation method provided in an embodiment of the present disclosure, sequentially executing the operation method on the n memory blocks according to the second operation order further includes: if the judgment result of the delay verification operation of at least one resistive random access memory in the kth stage memory block is no, continuously executing the write operation on the resistive random access memory with the judgment result of the delay verification operation in the kth stage memory block being no in the process of performing the delay verification operation on the (k+1) th stage memory block, wherein k is more than or equal to 1 and less than or equal to n-1.

For example, in an operation method provided in an embodiment of the present disclosure, the sequentially executing the operation method on the n memory blocks according to the second operation order further includes: and if the judgment result of the delay verification operation of all the resistance change memories in the k-stage memory block is yes, stopping the operation of the k-stage memory block, and determining one from the memory blocks to be processed to replace the k-stage memory block, wherein the memory blocks to be processed are other memory blocks except the N memory blocks.

For example, in an operation method provided in an embodiment of the present disclosure, the sequentially executing the operation method on the n memory blocks according to the second operation order further includes: and when the operation on the k-th stage memory block is stopped and no new memory block to be processed can be replaced, performing an idle operation on the k-th stage memory block, so that the time for sequentially performing the operation method on the n memory blocks according to the second operation sequence is kept unchanged.

For example, in the operating method provided in an embodiment of the present disclosure, each memory block includes the same number of resistive random access memories.

At least one embodiment of the present disclosure provides a storage device including: at least one resistive random access memory; a write circuit for performing a write operation on the resistance change memory; a delay circuit for performing a delay operation after the write operation, wherein the delay operation is continued for a predetermined time to delay; and the verification circuit is used for executing delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of obtaining the current storage value of the resistance random access memory and judging whether the difference between the current storage value and the target value of the resistance random access memory is within a preset error range.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A is a schematic diagram of a resistive random access memory circuit;

fig. 1B shows a structural view of a resistance change element R1;

FIG. 1C shows a schematic diagram of a process for programming a resistive random access memory;

FIG. 1D is a schematic diagram showing random drift phenomenon after a conductance value is successfully programmed;

FIG. 2A illustrates a flow chart of a method of operating a resistive random access memory provided in at least one embodiment of the present disclosure;

FIG. 2B is a schematic diagram illustrating a method of operating a resistive random access memory according to at least one embodiment of the present disclosure;

FIG. 2C illustrates a schematic diagram of another method of operating a resistive random access memory provided in accordance with at least one embodiment of the present disclosure;

FIG. 3 shows a flow chart of performing a delay operation after a write operation;

FIG. 4 illustrates a flow chart of another method of operation of a resistive random access memory provided in at least one embodiment of the present disclosure;

FIGS. 5A and 5B illustrate two schematic diagrams of a read-ahead operation performed on a resistive random access memory prior to a write operation;

FIG. 6 illustrates a resistive memory array;

FIG. 7 shows a flow chart of a method of performing an operation on at least a portion of a plurality of resistive random access memories, respectively;

FIG. 8A shows a schematic diagram of a method of performing an operation on 4 of a plurality of resistive random access memories, respectively;

FIG. 8B is a schematic diagram showing another method of performing an operation on each of 4 of the plurality of resistive random access memories;

FIG. 9 shows a schematic diagram of a plurality of resistive random access memories divided into N memory blocks; and

FIG. 10 illustrates a flowchart of a method of sequentially performing operations on n memory blocks in a second order of operation;

FIG. 11A illustrates a schematic diagram of a method of sequentially performing operations on a plurality of memory blocks;

FIG. 11B illustrates another schematic diagram of a method of sequentially performing operations on a plurality of memory blocks;

FIG. 12 shows a schematic diagram of a method of sequentially performing operations on n memory blocks in a second order of operation;

FIG. 13 shows a schematic diagram of a memory device; and

fig. 14 shows a schematic diagram of another memory device.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

A resistive random access memory is a nonvolatile type device whose conductance state can be adjusted by applying external stimulus, and it can be used as a memory cell or a calculation cell. For example, when a resistive memory is used as a memory cell, different conductance states (or resistance states, which are reciprocal relationships between resistance and conductance) of the resistive memory can be used to store different data information. When the resistive random access memory is used as the calculation unit, for example, an input voltage may be applied to the resistive random access memory, and the multiplication and accumulation calculation may be performed in parallel by an array of the resistive random access memory, for example, the conductance value of the resistive random access memory may be used as a multiplier in the multiplication calculation of two numbers.

The resistive random access memory often needs to be programmed in order to achieve stable and reliable information storage and to obtain accurate calculation results. The resistance change memory may be programmed, for example, by applying pulses of a certain amplitude and pulse width to the resistance change memory to adjust the conductance value (or resistance value) of the resistance change memory to a target value. However, due to the influence of the working mechanism of the resistive random access memory, after the resistive random access memory is successfully programmed, the resistive random access memory is likely to have a strong random conductivity value drift (also called relaxation phenomenon) due to the factors of unstable conductive filaments, spontaneous migration of oxygen vacancies, trapping and releasing of charges by defects and the like in the resistive random access memory. This phenomenon causes the conductance value of the resistive random access memory to deviate from the written conductance value rapidly in a short time scale (< 1 s), thereby failing to store the target value stably and reliably or affecting the accuracy of the calculation result.

FIG. 1A is a schematic diagram of a resistive random access memory circuit. As shown in fig. 1A, the resistive memory circuit adopts a 1T1R structure, that is, the resistive memory circuit includes a transistor M1 and a resistive element R1.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that the source and drain may be indistinguishable in structure. In embodiments of the present disclosure, in order to distinguish between two poles of a transistor other than a gate, one of the poles is directly described as a first pole, and the other pole as a second pole.

The embodiments of the present disclosure do not limit the type of transistor employed, for example, when the transistor M1 employs an N-type transistor, the gate thereof is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL inputs a high level; the first pole of the transistor M1 may be a source and configured to be connected to the source terminal SL, e.g., the transistor M1 may receive a reset voltage through the source terminal SL; the second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a lower electrode) of the resistive element R1, the first pole (e.g., an upper electrode) of the resistive element R1 being connected to the bit line terminal BL, e.g., the resistive element R1 may receive a Set (Set) voltage through the bit line terminal BL. For example, when the transistor M1 adopts a P-type transistor, the gate thereof is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL inputs a low level; the first pole of the transistor M1 may be a drain and configured to be connected to the source terminal SL, e.g., the transistor M1 may receive a Reset (Reset) voltage through the source terminal SL; the second pole of the transistor M1 may be a source and configured to be connected to the second pole (e.g., a lower electrode) of the resistive element R1, the first pole (e.g., an upper electrode) of the resistive element R1 being connected to the bit line terminal BL, e.g., the resistive element R1 may receive the set voltage through the bit line terminal BL. It should be noted that the resistive random access memory circuit structure may be implemented as other structures, for example, a structure in which the second pole of the resistive random access element R1 is connected to the source terminal SL, or the resistive random access memory may be a circuit structure including only the resistive random access element R1, which is not limited in the embodiments of the present disclosure. The following embodiments will be described by taking an N-type transistor as an example.

The word line terminal WL functions to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. In the operation of the resistive element R1, for example, the set operation or the reset operation, the transistor M1 needs to be turned on first, that is, an on voltage needs to be applied to the gate of the transistor M1 through the word line terminal WL. After the transistor M1 is turned on, for example, the resistance state of the resistance variable element R1 can be changed by applying a voltage to the resistance variable element R1 at the source terminal SL and the bit terminal BL. For example, a set voltage may be applied through the bit line terminal BL so that the resistive element R1 is in a low resistance state; for another example, a reset voltage may be applied through the source terminal SL so that the resistive element R1 is in a high resistance state.

The resistive element R1 is a critical component in a resistive memory array. Fig. 1B shows a structural diagram of a resistive element R1.

As shown in fig. 1B, the resistive element R1 may include a resistive layer 111, a functional layer 112, and upper and lower electrodes 113 and 114 at both sides. The functional layer 112 is an optional layer, and can be added or not according to the optimization direction of the performance of the resistive random access memory device, and the functional layer is designed accordingly. The resistive layer 111 may be, for example, a single layer of a single type binary metal oxide (for example, niO, alOx, etc.), a graphene oxide, or a multi-perovskite oxide (for example, STO, SZO, PCMO, etc.), or may be a stack of a plurality of layers of the above materials, for example, a stack of TixN and AlOx.

For example, when a transistor is used as a switching element of a resistive memory, the lower electrode 114 and the upper electrode 113 of the resistive element R1 may be connected to the drain of the transistor and the bit line BL, respectively. The source of the transistor is connected to a source line SL and the gate is connected to a word line WL. In this way, when voltages are applied to the bit line BL and the word line WL at the same time, for example, a Set (Set) operation can be performed. When voltages are simultaneously applied to the source line SL and the word line WL, for example, a Reset (Reset) operation may be performed. The gate of the transistor functions to turn on the transistor by receiving an on voltage from the word line WL, so that a voltage can be applied to the resistive switching layer 111 through the electrodes on both sides of the resistive switching element R1. Therefore, in the structure using a transistor as a switching element, the transistor needs to be turned on first when a voltage is applied to the resistive layer 111, that is, an on voltage needs to be applied to the gate of the transistor via the word line WL.

In the embodiment of the present disclosure, for example, the resistance variable element R1 has a threshold voltage, and the resistance value (or the conductance value) of the resistance variable element R1 is not changed when the input voltage amplitude is smaller than the threshold voltage of the resistance variable element R1. In this case, calculation can be performed by inputting a voltage smaller than the threshold voltage, using the resistance value (or the conductance value) of the resistance variable element R1; and the resistance value (or the conductance value) of the resistive element R1 may be changed by inputting a voltage larger than the threshold voltage.

FIG. 1C shows a schematic diagram of a process for programming a resistive random access memory. In fig. 1C, the ordinate indicates the magnitude of the voltage applied across the resistive random access memory, and the abscissa indicates the time. The minimum pulse voltage Va applied is a read voltage, and the current stored value of the resistive random access memory is read by applying the read voltage to the resistive random access memory. The current stored value of the resistive random access memory may be, for example, the conductance value of the resistive random access memory. The read voltage is, for example, smaller than the threshold voltage of the resistive random access memory, so that the current conductance value of the resistive random access memory is read without changing the resistance value of the resistive random access element R1.

In fig. 1C, other voltages than the read voltage applied to the resistance change memory are a Set voltage (Set voltage) or a Reset voltage (Reset voltage). For example, the Set voltage is a positive voltage pulse, while the Reset voltage is a negative voltage pulse, and the pulse voltage amplitude is the voltage difference between the BL and SL terminals in FIG. 1A. Applying a Set voltage to the resistive switching memory can adjust the conductance value up and applying a Reset voltage to the resistive switching memory can adjust the conductance value down. In the embodiments of the present disclosure, applying a Set voltage to a resistive random access memory is referred to as a Set operation, and applying a Reset voltage to a resistive random access memory is referred to as a Reset operation, and one Set operation or Reset operation may be referred to as one write operation.

In embodiments of the present disclosure, the resistive random access memory may be programmed using an incremental step programming pulse (Incremental Step Program Pulse, ISPP) strategy, i.e., the pulse amplitude employed in a Set operation or Reset operation may be incrementally increased. The method comprises the following steps: the process of applying a read voltage to read the current conductance of the resistive random access memory and comparing the conductance with a target value is called a verify (verify) operation. If the current conductivity value of the resistive random access memory is smaller than the target value, performing Set operation, and performing verification operation again after the Set operation, and if the current conductivity value is still smaller than the target value, applying a Set voltage pulse with the same pulse width and larger amplitude than the previous Set voltage pulse, and performing enhanced Set operation; if the conductance value is larger than the target value, a Reset operation is required, and the Reset operation is similar to the Set operation. After each verification of the conductance value of the resistive random access memory, a Set operation or a Reset operation is performed to correct the conductance value until the conductance value of the resistive random access memory reaches a target value (or a target range).

The programming method of writing-checking can realize writing of target electric conduction value, but the resistance change memory which successfully completes writing of electric conduction value is likely to have electric conduction value drift with strong randomness due to factors such as unstable conductive filaments, spontaneous migration of oxygen vacancies, capturing and releasing of electric charges by defects and the like in the device after operation due to the influence of the working mechanism of the resistance change memory. This phenomenon causes the conductance value of the resistive random access memory to deviate from the written conductance value rapidly in a short time scale (< 1 s), thereby failing to store the target value stably and reliably or affecting the accuracy of the calculation result.

FIG. 1D is a schematic diagram showing random drift after the conductance values are programmed successfully. The different curves in fig. 1D represent the variation of the conductance values of several different resistive random access memories over time after successful programming, respectively. As shown in fig. 1D, the conductance value at time 0 is a programmed value (i.e., a desired target value), and the conductance values of these resistive random access memories drift in a time scale of 1 second, and the random drift phenomenon has short time duration, large drift degree and strong randomness.

In order to reduce or eliminate the effect of relaxation phenomena of a resistive random access memory on a stored value, so as to improve stability and reliability of the stored value stored by the resistive random access memory, and to improve accuracy of a calculation result of the resistive random access memory in a computing application, at least one embodiment of the present disclosure provides a method of operating the resistive random access memory.

Fig. 2A is a flow chart illustrating a method of operating a resistive random access memory according to at least one embodiment of the present disclosure. As shown in fig. 2A, the operation method includes operation S10-operation S30.

In operation S10, a write operation is performed on the resistive random access memory.

In one embodiment of the present disclosure, the write operation may be, for example, a Set operation or a Reset operation.

In another embodiment of the present disclosure, the write operation may include, for example, a plurality of Set operations or a plurality of Reset operations, or the write operation may also include at least one Set operation and at least one Reset operation.

In operation S20, a delay operation is performed after the write operation, and the delay operation is continued for a predetermined time to perform delay.

In one embodiment of the present disclosure, the delay operation is a delay performed for a predetermined time after the write operation, i.e., an operation after the write operation is performed on the resistive random access memory and after the delay for a predetermined time has elapsed, such as a delay verification operation hereinafter.

For example, the delay operation may be performed by a delay circuit that performs a delay operation according to a set predetermined time, and does not perform other operations on the resistive random access memory for the duration of the delay operation.

For example, if the verify operation is required to be performed on the resistive random access memory after the write operation is performed on the resistive random access memory, and the predetermined time is 10s, the verify operation may be performed on the resistive random access memory after the write operation is performed on the resistive random access memory for another 10 s.

In embodiments of the present disclosure, the predetermined delay time may be set according to a suppression requirement for the relaxation phenomenon and a programmed speed requirement. For example, if the demand for suppression of the relaxation phenomenon is high and high-speed programming is not required, a long predetermined time may be set, and the predetermined time may be set to 10s, 5s, 2s, 1s, or the like. If the suppression requirement for relaxation phenomenon is low and high-speed programming is required, a short predetermined time may be set, for example, 1ms, 2ms, 5ms, 10ms, or the like may be set. One skilled in the art can select an appropriate length of time as the predetermined time based on the suppression requirement for the relaxation phenomenon and the programmed speed requirement.

In operation S30, a delay verification operation is performed after the delay operation, the delay verification operation including obtaining a current stored value of the resistive random access memory and determining whether a difference between the current stored value and a target value of the resistive random access memory is within a preset error range.

In an embodiment of the present disclosure, obtaining a current stored value of a resistive random access memory includes: applying a reading voltage to the resistive random access memory, obtaining a current value output by the resistive random access memory under the action of the reading voltage, and determining the current storage value of the resistive random access memory according to the current value and the reading voltage.

For example, the current stored value of the resistive random access memory may be the current conductance value of the resistive random access memory, or may be the current resistance value of the resistive random access memory, which is not limited by the embodiments of the present disclosure, and the embodiments of the present disclosure are described taking the stored value as the conductance value as an example. For example, a read voltage may be applied to the source line of the resistive random access memory, which may employ the read voltage Va of fig. 1C above, so that the conductance value of the resistive random access memory may be determined using ohm's law according to the current value output by the bit line.

It should be understood that those skilled in the art may also use other technical means to obtain the current stored value of the resistive random access memory, for example, a multimeter may be used to obtain the current conductance value or resistance value of the resistive random access memory, which is not limited in the embodiments of the present disclosure.

In the embodiments of the present disclosure, the target value may be preset. The target value may be, for example, a resistance value. The target value may be, for example, 500 Ω, 10mΩ, and so on. The preset error range may be preset according to the requirement of calculation accuracy. The preset error range with respect to the target value may be, for example, -5k omega, 5k omega.

In at least one embodiment of the present disclosure, the method of operating a resistive random access memory ensures the accuracy of the verification result by adding a delay operation between the write operation and the delay verification operation. Since the probability of reoccurrence in the subsequent time is low if the resistive random access memory does not have a relaxation phenomenon after the lapse of the predetermined time; from another point of view, it is understood that by means of a delay verification operation, a resistive random access memory which has a relaxation phenomenon occurring during the duration of the delay operation can be verified, so that it can be programmed to reach the target value in a subsequent write operation.

The operation method of the resistive random access memory reduces the influence of relaxation phenomenon of the resistive random access memory on the storage value, so that the stability and reliability of the storage value stored by the resistive random access memory can be improved, and the accuracy of a calculation result of the resistive random access memory in calculation application is improved.

Fig. 2B is a schematic diagram illustrating an operation method of a resistive random access memory according to at least one embodiment of the present disclosure. Hereinafter, the operation method shown in fig. 2B is collectively referred to as a delay-check scheme.

As shown in fig. 2B, in the delay-check scheme, after the end of the write operation to the resistive random access memory, a delay operation is performed, which lasts for a predetermined time to delay. After the delay lasting for a preset time, a delay check operation is performed on the resistance random access memory, so that whether the difference between the current stored value and the target value of the resistance random access memory is within a preset error range or not is judged through the delay check operation.

Fig. 2C is a schematic diagram illustrating another method of operating a resistive random access memory according to at least one embodiment of the present disclosure. Hereinafter, the operation method shown in fig. 2C is collectively referred to as a check-delay-check scheme.

In this check-delay-check scheme, as shown in fig. 2C, a pre-check operation is performed on the resistive random access memory after a write operation is performed on the resistive random access memory. After the pre-verification operation is finished, the delay operation is executed again, and after the delay operation, the delay verification operation is executed again. The pre-verification operation is similar to the time delay verification operation, namely the pre-verification operation comprises the steps of obtaining the current stored value of the resistance random access memory and judging whether the difference between the current stored value and the target value of the resistance random access memory is within the preset error range.

It should be noted that, in the embodiment of the present disclosure, the content of execution of the pre-checking operation is identical to the content of execution of the delay checking operation, that is, the current stored value of the resistive random access memory is obtained, and then it is determined whether the difference between the current stored value and the target value of the resistive random access memory is within the preset error range, where only the time that the pre-checking operation and the delay checking operation occur is different.

It should be understood that, all the technical schemes of firstly delaying and then checking the resistive random access memory after the writing operation are within the scope of the disclosure, that is, all other technical schemes of combining the delay and the checking for multiple times are also within the scope of the disclosure, for example, a delay-checking scheme is followed by a series of checking operations, or a checking-delay-checking is followed by a series of checking operations.

For example, in one embodiment, performing a latency operation after a write operation includes: and after each writing operation, a pre-verification operation, a delay operation and a delay verification operation are sequentially executed.

In one embodiment shown in FIG. 2C, performing a delay operation after a write operation includes: if the judgment result of the pre-checking operation is no, the writing operation and the pre-checking operation are sequentially executed on the resistance random access memory after the pre-checking operation until the judgment result of the pre-checking operation is yes, and if the judgment result of the pre-checking operation is yes, the delay operation is executed on the resistance random access memory.

In the embodiment of the disclosure, when the judgment result of the pre-verification operation is yes, the delay operation is executed on the resistive random access memory, so that the times of executing the delay operation and the delay verification operation can be reduced, and the operation efficiency can be improved under the condition of ensuring that the resistive random access memory has a stable storage value.

The method of performing a delay operation after a write operation described above is described below in connection with the flowchart shown in fig. 3. Fig. 3 shows a flow chart of performing a delay operation after a write operation. As shown in fig. 3, after the operation S10 performs a write operation on the resistive random access memory, operations S40 and S201 to S202 may be performed. For example, a method of performing a delay operation after a write operation may include operations S201-S202.

In operation S40, a pre-verification operation is performed on the resistive random access memory.

In operation S201, a determination result of the pre-verification operation is determined.

If the result of the pre-verification operation is no, that is, the difference between the current stored value and the target value of the resistive random access memory is not within the preset error range, operations S10 and S40 are performed in a returning manner until the result of the pre-verification operation is yes.

If the pre-verification operation has a yes judgment, that is, the difference between the current stored value and the target value of the resistive random access memory is within the preset error range, operation S202 is performed.

In operation S202, a delay operation is performed. Note that this operation S202 is similar to the operation S30 described above.

Fig. 4 is a flow chart illustrating another method of operating a resistive random access memory provided in accordance with at least one embodiment of the present disclosure. As shown in fig. 4, the operation method may further include operation S50 on the basis of the operation method described above with reference to fig. 2A.

In operation S50, a determination result of the delay verification operation is determined. If the judgment result of the delay verification operation is no, that is, the difference between the current stored value and the target value of the resistive random access memory is not within the preset error range, the operations S10 writing operation, S20 delay operation and S30 delay verification operation are continuously executed. If the judgment result of the delay verification operation is yes, that is, the difference between the current stored value and the target value of the resistance change memory is within the preset error range, the success of writing the target value is indicated, and the operation method can be ended.

In one embodiment of the present disclosure, the operation method includes a pre-verification operation, that is, after the write operation and before the delay operation, the pre-verification operation is performed on the resistive random access memory, and if the determination result of the pre-verification operation is yes and the determination result of the delay verification operation is yes, it indicates that the write target value is successful, and the operation method may be ended.

For example, in the operation method described above with reference to fig. 3, if operation S201 determines that the determination result of the pre-verification operation is yes, operation S202, i.e., a delay operation, is performed. Next, a delay verification operation may be performed after the delay operation. If the judgment result of the delay verification operation is yes, the writing target value is successful, and if the judgment result of the delay verification operation is no, the operation S10 writing operation, the operation S20 delay operation and the operation S30 delay verification operation are continuously executed.

In one embodiment of the present disclosure, the method of operation may further include: before the write operation, a read-ahead operation is performed on the resistive random access memory. The pre-read operation includes: and determining a write pulse adopted by the write operation according to the current stored value of the resistive random access memory. In embodiments of the present disclosure, performing a pre-read operation prior to a write operation may determine a subsequent specific programming operation (e.g., including a set operation and a reset operation) based on a current stored value (e.g., a conductance value) of the resistive random access memory, thereby improving programming efficiency.

Fig. 5A and 5B show two schematic diagrams of performing a read-ahead operation on a resistive random access memory prior to a write operation.

As shown in fig. 5A and 5B, a pre-read operation may be performed on the resistive random access memory prior to the write operation, a current stored value of the resistive random access memory is acquired through the pre-read operation, and a write pulse employed for the write operation is determined according to the current stored value of the resistive random access memory.

For example, if the current memory of the resistive random access memory obtained by the pre-read operation is larger than the target value, it may be determined that the write pulse used for the subsequent write operation is a Reset voltage pulse. If the current memory of the resistive random access memory obtained through the pre-reading operation is smaller than the target value, the write pulse adopted by the subsequent write operation can be determined to be a Set voltage pulse.

In an embodiment of the present disclosure, the pre-read operation may be an operation performed when programming the resistive random access memory is started. The write pulse employed for the first write operation may be determined from the pre-read operation, and the subsequent write operation may determine the write pulse from the result of the delay verification operation.

At least one embodiment of the present disclosure also provides a control method of a memory device, which may include a plurality of resistive random access memories. The control method includes performing an operation method, which may be the method described above with reference to fig. 2A, on at least a part of the plurality of resistive random access memories, respectively. That is, the operating method may include: s10, executing write operation on the resistive random access memory; s20, executing a delay operation after the write operation, wherein the delay operation lasts for a preset time to delay; and S30, performing delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of obtaining the current stored value of the resistance random access memory and judging whether the difference between the current stored value and the target value of the resistance random access memory is within a preset error range.

The control method respectively executes the operation method on at least part of the resistive random access memory in the storage device, for example, the operation method is respectively executed on a part or all of the resistive random access memory in the storage device, so that the stability and the reliability of the storage value of the at least part of the resistive random access memory are ensured, and the accuracy of the calculation result of the at least part of the resistive random access memory in the calculation application is improved.

Since operations S10 to S30 have been described above, operations S10 to S30 will not be described again here.

In one embodiment of the present disclosure, a plurality of resistive random access memories in one memory device may be arranged in an array, for example, to form one or more resistive random access memory arrays.

Fig. 6 shows a resistive memory array composed of a plurality of resistive memory circuits as shown in fig. 1A, for example, a plurality of resistive memory circuits compose an array of m rows and n columns, m being an integer greater than 1, n being an integer greater than or equal to 1. BL <1>, BL <2> … … BL < m > in FIG. 6 represent bit lines of the m-th row of the first row and the second row … …, respectively, and the resistive element in the resistive random access memory circuit of each row is connected to the bit line corresponding to the row; in fig. 6, WL <1>, WL <2> … … WL < n > represent the word lines of the n-th column of the first and second columns … …, respectively, and the gates of the transistors in the resistive random access memory circuit of each column are connected to the corresponding word line of that column; in fig. 6, SL <1>, SL <2> … … SL < n > represent source lines of the first column and the second column … …, respectively, and the source of a transistor in each column of the resistive random access memory circuit is connected to the source line corresponding to the column.

It should be noted that the resistive memory array shown in fig. 6 is only an example, and embodiments of the present disclosure include, but are not limited to, for example, word Lines (WL) may be made parallel to Bit Lines (BL).

In one embodiment of the present disclosure, the above method of operation may be performed separately for at least a portion of the resistive random access memory in the resistive random access memory array.

For example, the above-described operation method may be performed for all the resistive random access memories in the resistive random access memory array, or may be performed for a plurality of resistive random access memories located in some rows and some columns in the resistive random access memory array, respectively. As shown in fig. 6, the above-described operation methods may be performed for the resistive random access memories 610 to 640, respectively, for example. The above-described operation method may also be performed on several non-adjacent resistive random access memories, respectively, and the positions of the plurality of resistive random access memories to be performed are not limited in the embodiments of the present disclosure.

In one embodiment of the present disclosure, the memory device may also include a plurality of resistive random access memory arrays, the above-described operation method may be performed on a plurality of resistive random access memories in only one resistive random access memory array, the above-described operation method may be performed on a plurality of resistive random access memories in a portion of the plurality of resistive random access memory arrays, and the above-described operation method may be performed on a plurality of resistive random access memories in all of the plurality of resistive random access memory arrays.

In one embodiment of the present disclosure, the operating method performed on each resistive random access memory further includes: before the write operation, a read-ahead operation is performed on the resistive random access memory. The pre-read operation includes reading a current stored value of the resistive random access memory and determining a write pulse to be used for a write operation based on the current stored value of the resistive random access memory. This method of operation is described above with reference to fig. 5A and 5B and will not be described in detail herein.

Fig. 7 shows a flow chart of a method of performing an operation on at least a portion of a plurality of resistive random access memories, respectively. As shown in fig. 7, the method may include operations S710-S740.

In operation S710, a first order of operation for operating at least a portion of the resistive random access memory is determined.

In operation S720, the write operations are sequentially performed on at least a portion of the resistive random access memories according to the first operation order, wherein after the write operation performed on a first one of the at least a portion of the resistive random access memories is completed, a delay operation is performed on the first resistive random access memory, and a write operation is performed on a second one of the at least a portion of the resistive random access memories, and so on.

In operation S730, in performing a write operation on a last one of at least partial resistive random access memories, a delay verification operation is performed on a first one of the at least partial resistive random access memories.

In operation S740, after the delay verification operation of the first resistive random access memory is finished, the delay verification operation is performed on the second resistive random access memory, and so on to complete the delay verification operation on the at least part of the resistive random access memories.

In the embodiment of the disclosure, the method realizes the pipeline operation of a plurality of resistive random access memories, namely, when one resistive random access memory is subjected to delay operation, the other resistive random access memory can be subjected to write operation, so that the time expenditure caused by delay operation and write operation is reduced, and the programming efficiency is improved.

In order to facilitate understanding of the embodiments of the present disclosure, the embodiment described in fig. 7 above will be described with reference to fig. 8A by taking, as an example, at least a portion of the resistive random access memories having a number of 4. However, this does not mean that the number of at least part of the resistive random access memories is limited to 4, and in the present disclosure, the number of at least part of the resistive random access memories may be any number less than or equal to the total number of resistive random access memories in the memory device.

Fig. 8A shows a schematic diagram of a method of performing an operation on 4 resistive random access memories among a plurality of resistive random access memories, respectively.

For example, a first operation order in which the plurality of resistive random access memories are operated may be determined according to a preset order rule. For example, in the resistive random access memory array shown in fig. 6, the order rule may be that the resistive random access memories in the same row are sequentially executed in the order from top to bottom.

For example, at least a portion of the resistive random access memory may include resistive random access memories 610-640, and the first order of operation of the resistive random access memories 610-640 may be resistive random access memory 610, resistive random access memory 620, resistive random access memory 630, resistive random access memory 640.

As shown in fig. 8A, according to the first operation sequence of the resistive random access memories 610 to 640, a write operation may be performed on the resistive random access memory 610 first, and after the write operation is performed on the resistive random access memory 610 is completed, a delay operation is performed on the resistive random access memory 610. The delay operation may mean, for example, not performing any operation on the resistive random access memory 610.

As shown in fig. 8A, after the end of the write operation to the resistive random access memory 610, the write operation to the resistive random access memory 620 is also performed during the delay operation to the resistive random access memory 610, and similarly to the resistive random access memory 610, after the end of the write operation to the resistive random access memory 620, the delay operation to the resistive random access memory 620 is performed.

As shown in fig. 8A, after the end of the write operation to the resistive random access memory 620, the write operation to the resistive random access memory 630 is performed, and similarly to the resistive random access memory 610 and the resistive random access memory 620, after the end of the write operation to the resistive random access memory 630, the delay operation is performed to the resistive random access memory 630.

As shown in fig. 8A, after the end of the write operation to the resistive random access memory 630, the write operation to the resistive random access memory 640 is performed, and similarly to the resistive random access memories 610 to 630, after the end of the write operation to the resistive random access memory 640, the delay operation to the resistive random access memory 640 is performed.

As shown in fig. 8A, in performing a write operation to the last resistive random access memory (i.e., resistive random access memory 640), a delay verification operation is performed to the first resistive random access memory (i.e., resistive random access memory 610).

For example, when a write operation to the resistive random access memory 640 is started, a delay verification operation is performed to the resistive random access memory 610. If the delay verification operation performed on the resistive random access memory 610 determines that the difference between the current stored value and the target value of the resistive random access memory 610 is not within the preset error range, the write operation may be performed again on the resistive random access memory 610. And, after the delay verification operation performed on the resistive random access memory 610 is finished, the delay verification operation is performed on the resistive random access memory 620. Similar to the resistive random access memory 610, if the delay verification operation performed on the resistive random access memory 620 determines that the difference between the current stored value and the target value of the resistive random access memory 620 is not within the preset error range, the write operation may be performed again on the resistive random access memory 620. And so on to complete the delay verification operations for the resistive random access memory 630 and the resistive random access memory 640.

Fig. 8B shows another schematic diagram of an operation method performed on 4 resistive random access memories among a plurality of resistive random access memories, respectively.

As shown in fig. 8B, before the write operation is sequentially performed on the resistive random access memory 610, the resistive random access memory 620, the resistive random access memory 630, and the resistive random access memory 640, the read operation may be sequentially performed on the resistive random access memory 610, the resistive random access memory 620, the resistive random access memory 630, and the resistive random access memory 640. The pre-read operation includes reading a current stored value of the resistive random access memory and determining a write pulse to be used for a write operation based on the current stored value of the resistive random access memory. Reference may be made to the corresponding description in the above embodiments for the pre-read operation, and no further description is given here.

It should be noted that, after the write operation and before the delay operation, a pre-verification operation may also be performed on the resistive random access memory. The method of performing the pre-verification operation on the resistive random access memory is described above with reference to fig. 2C and 3, and will not be described again.

As described above with reference to fig. 8A and 8B, since a plurality of resistive random access memories form a pipeline operation, the duration of the delay operation of each resistive random access memory in the pipeline is the same, i.e., the delay operation lasts for the same predetermined time.

In one embodiment of the present disclosure, the number of resistive random access memories (i.e., the number of at least a portion of resistive random access memories) included in the pipeline operation may be determined, for example, based on a predetermined time of the delay operation, a time of the pre-read operation, and a time-duration relationship between the pre-verify/delay verify. The predetermined time of the delay operation may be adjusted according to the number of different pipeline operations.

In one embodiment of the present disclosure, a method of performing an operation on at least a portion of a plurality of resistive random access memories, respectively, includes: dividing the plurality of resistive random access memories into N memory blocks, each memory block of the N memory blocks comprising at least one resistive random access memory; selecting N memory blocks from the N memory blocks, and determining a second order of operation of the N memory blocks; and sequentially performing the operation method on the n memory blocks according to the second operation order. The parallel execution operation method of at least one resistive random access memory in each memory block is characterized in that N is an integer greater than or equal to 2, and N is an integer greater than or equal to 2 and less than or equal to N. In the embodiment of the disclosure, the method can enable a plurality of resistance change memory blocks in one memory block to execute the operation method in parallel, thereby further improving the programming efficiency.

In one embodiment of the present disclosure, each of the N memory blocks may include the same number of resistive random access memories. The inclusion of the same number of resistive random access memories per memory block may reduce the complexity of the programming operation and simplify the system design. In another embodiment of the present disclosure, the N memory blocks may include a different number of resistive random access memories. For example, one memory block may include 1 resistance change memory, and another memory block may include a plurality of resistance change memories. In the case where a plurality of resistance change memories are included in the memory block, the plurality of resistance change memories execute the above-described operation methods in parallel, that is, write operation, delay verification operation, and the like are executed in parallel.

In one embodiment of the present disclosure, N memory blocks may be distributed over different resistive memory arrays, respectively, and multiple memory blocks distributed over different resistive memory arrays may be programmed cooperatively. Of course, the N memory blocks may also be distributed over the same resistive memory array. The locations of the plurality of memory blocks on the same resistive memory array may or may not be adjacent, as embodiments of the present disclosure are not limited in this regard.

In one embodiment of the present disclosure, the second order of operation of the n memory blocks may be pre-set or may be determined according to a pre-set order rule.

Fig. 9 shows a schematic diagram of dividing a plurality of resistive random access memories into N memory blocks. It should be understood that fig. 9 is only a schematic diagram of a resistive memory array, and does not represent a specific circuit structure or resistive memory structure.

In the example of fig. 9, the plurality of resistance change memories is divided into 4 memory blocks, each including 4 resistance change memories therein. The 4 memory blocks are memory blocks 910-940, respectively.

For example, 4 memory blocks 910-940 may be selected from the N memory blocks and a second order of operation of the memory blocks 910-940 is determined. For example, the second operation order may be determined as memory block 910, memory block 920, memory block 930, memory block 940 according to a predetermined order rule. So that the above-described operation methods may be sequentially performed in the order of the memory block 910, the memory block 920, the memory block 930, and the memory block 940. For example, at least one resistive random access memory in each memory block performs the method of operation in parallel.

In one embodiment of the present disclosure, the n memory blocks are determined as a first level memory block, a second level memory block, …, an nth level memory block, respectively, in a second order of operation. For example, the memory block 910, the memory block 920, the memory block 930, and the memory block 940 may be determined as a first level memory block, a second level memory block, a third level memory block, and a fourth level memory block, respectively.

Fig. 10 shows a flow chart of a method of sequentially performing operations on n memory blocks in a second order of operation.

As shown in FIG. 10, the method may include operations S1010-S1040.

In operation S1010, a write operation is performed on the resistive random access memory in the first-level memory block.

In operation S1020, after the write operation of the resistive random access memory in the first-level memory block is finished, a delay operation is performed on the first-level memory block, and a write operation is performed on the resistive random access memory in the second-level memory block, and so on to complete the write operations of the n memory blocks.

In operation S1030, a delay verification operation is performed on all the resistive random access memories in the first-stage memory block in the course of performing a write operation on the nth-stage memory block.

In operation S1040, after the delay verification operation of the resistive random access memory in the first-stage memory block is finished, the delay verification operation is performed on the resistive random access memory in the second-stage memory block, and so on to complete the delay verification operation of the n memory blocks.

In embodiments of the present disclosure, the n memory blocks implement pipelining, e.g., write operations may be performed to one level of memory blocks while another level of memory blocks is performing a delay operation, which may reduce the time cost of accumulated delay operations from memory block-by-memory block serial programming.

To facilitate an understanding of embodiments of the present disclosure, the method illustrated in fig. 10 is described below with reference to fig. 11A by taking the selection of 4 memory blocks from N memory blocks as an example.

FIG. 11A shows a schematic diagram of a method of sequentially performing operations on a plurality of memory blocks.

As shown in fig. 11A, according to the second operation sequence of the memory blocks 910 to 940, a write operation may be performed on the resistive random access memory in the memory block 910 first, and after the write operation is performed on the resistive random access memory in the memory block 910 is completed, a delay operation is performed on the memory block 910. The delay operation does not perform any operation on the resistive random access memory in the memory block 910, for example.

As shown in fig. 11A, after the end of the write operation to the resistive random access memory in the memory block 910, the write operation to the resistive random access memory in the memory block 920 is performed in the process of performing the delay operation to the memory block 910, and similarly to the memory block 910, the delay operation to the memory block 920 is performed after the end of the write operation to the memory block 920.

As shown in fig. 11A, after the end of the write operation to the resistive random access memory in the memory block 920, the write operation to the resistive random access memory in the memory block 930 is performed, and similarly to the memory block 910 and the memory block 920, after the end of the write operation to the memory block 930, the delay operation is performed to the memory block 930.

As shown in FIG. 11A, after the write operation to memory block 930 is completed, the write operation to memory block 940 is performed, and similar to memory blocks 910-930, after the write operation to memory block 940 is completed, a delay operation is performed to memory block 940.

As shown in fig. 11A, in performing a write operation to a memory block of the last stage (i.e., memory block 940), a latency check operation is performed to a memory block of the first stage.

For example, at the beginning of a write operation to memory block 940, a latency check operation is performed on memory block 910. If the delay verification operation performed on the memory block 910 determines that the difference between the current stored value and the target value of the memory block 910 is not within the preset error range, the write operation may be performed again on the memory block 910. And, after the delay check operation performed on the memory block 910 is finished, the delay check operation is performed on the memory block 920. Similar to memory block 910, if the latency check operation performed on memory block 920 determines that the difference between the current stored value and the target value of memory block 920 is not within the preset error range, a write operation may be performed again on memory block 920. And so on to complete the latency check operations for memory block 930 and memory block 940.

In one embodiment of the present disclosure, the operating method performed on each resistive random access memory further includes: performing a read-ahead operation on the resistive random access memory prior to the write operation; the pre-reading operation comprises the steps of reading the current stored value of the resistance random access memory; and determining a write pulse used for writing according to the current stored value of the resistive random access memory.

In this embodiment, sequentially performing the operation method on the n memory blocks in the second operation order includes: performing a pre-read operation on the resistive random access memory in the first level memory block; after the pre-reading operation of the resistive random access memory of the first-stage memory block is finished, the pre-reading operation is carried out on the resistive random access memory in the second-stage memory block, and the pre-reading operation of n memory blocks is finished by analogy; performing a write operation on the (k+1) -th-level memory block during the pre-read operation on the (k+1) -th-level memory block, and performing a delay operation on the (k) -th-level memory after the write operation of the (k) -th-level memory block is completed; after the pre-read operation of the nth stage memory block of the n memory blocks is completed, performing a delay verification operation on the resistive random access memory in the first stage memory block, and performing a write operation on the nth stage memory block; and after the verification operation of the first-stage memory block is finished, performing delay verification operation on the resistive random access memory in the second-stage memory block, and the like to finish the delay verification operation of n memory blocks, wherein k is more than or equal to 1 and less than or equal to n-1.

FIG. 11B illustrates a schematic diagram of a method of sequentially performing operations on a plurality of memory blocks. A control method of sequentially executing the operation method on n memory blocks will be described with reference to fig. 9 and 11B. As shown in fig. 9, the plurality of resistance change memories is divided into 4 memory blocks, and each memory block includes 4 resistance change memories therein. The 4 memory blocks are memory blocks 910-940, respectively. Memory block 910, memory block 920, memory block 930, and memory block 940 may be determined as, for example, a first level memory block, a second level memory block, a third level memory block, and a fourth level memory block, respectively.

As shown in fig. 11B, a read-ahead operation is performed on the resistive random access memory in the memory block 910; after the read-ahead operation of the resistive random access memory of the memory block 910 is completed, the read-ahead operation is performed on the resistive random access memory in the memory block 920; after the read-ahead operation of the resistive random access memory in the memory block 920 is completed, the read-ahead operation is performed on the resistive random access memory in the memory block 930; after the read-ahead operation of the resistive random access memory of the memory block 930 is completed, the read-ahead operation is performed on the resistive random access memory in the memory block 940.

In the course of performing the pre-read operation on the resistive random access memory in the memory block 920, a write operation is performed on the resistive random access memory in the memory block 910, and after the write operation of the memory block 910 is completed, a delay operation is performed on the memory block 910; after the read-ahead operation of the last level of memory block (i.e., memory block 940) is completed, a delay verification operation is performed on the resistive random access memory in memory block 910, and a write operation is performed on the resistive random access memory in memory block 940; and performing a delay verification operation on the resistive random access memory in the memory block 920 after the verification operation of the memory block 910 is finished, and thus completing the delay verification operation of the 4 memory blocks.

In one embodiment of the present disclosure, a pre-verification operation may be included after the write operation and before the delay operation. If the judgment result of the pre-verification operation is that the difference between the current stored value and the target value of the resistance random access memory is not in the preset error range, the writing operation and the pre-verification operation are executed again until the judgment result of the pre-verification operation is yes. And if the judgment result of the pre-verification operation is that the difference between the current storage value and the target value of the resistance random access memory is within the preset error range, sequentially executing the delay operation and the delay verification operation.

In one embodiment of the present disclosure, if a pre-verify operation is included after a write operation and before a delay operation, in a case where a result of a determination that a memory block of a subsequent stage reaches the pre-verify operation earlier than a memory block of a previous stage is yes, the memory block of the subsequent stage may perform a null operation to wait for the result of the determination of the pre-verify operation of the memory block of the previous stage to be yes. After the previous stage memory block completes the delay verification operation, the next stage memory block executes the delay verification operation. For example, the idle operation may be not performed any operation, or may be an idle running preset program.

In one embodiment of the present disclosure, the sequentially performing the operation method on the n memory blocks in the second operation order further includes: if the judgment result of the delay verification operation of at least one resistance random access memory in the k-th stage memory block is no, in the process of carrying out the delay verification operation on the (k+1) -th stage memory block, continuously executing the write operation on the resistance random access memory of which the judgment result of the delay verification operation in the k-th stage memory block is no, wherein k is more than or equal to 1 and less than or equal to n-1.

For example, the second-stage memory block includes 4 resistive random access memories, and if the determination result of the delay verification operation of 1 resistive random access memory is no, then in the process of performing the delay verification operation on the third-stage memory block, the writing operation is continuously performed on the 1 resistive random access memory in the second-stage memory block.

In one embodiment of the present disclosure, the sequentially performing the operation method on the n memory blocks in the second operation order further includes: and if the judgment result of the delay verification operation of all the resistance random access memories in the k-stage memory block is yes, stopping the operation of the k-stage memory block, and determining one to replace the k-stage memory block from the memory blocks to be processed. The memory block to be processed is the other memory blocks except for the N memory blocks in the N memory blocks.

In the embodiment of the disclosure, after one memory block is successfully programmed, another new memory block is added into the pipeline operation, so that the number of stages in the pipeline operation is unchanged, and the time of delay operation performed on the resistive random access memory in each memory block is unchanged.

For example, a plurality of resistance change memories in one memory device are divided into 10 memory blocks, and 4 memory blocks are selected from the 10 memory blocks to sequentially perform the above-described pipelining. If the judgment result of the delay verification operation of all the resistive random access memories in the first-stage memory block is yes, stopping the operation of the first-stage memory block, and selecting one from the rest 6 memory blocks to replace the first-stage memory block.

Fig. 12 shows a schematic diagram of a method of sequentially performing operations on n memory blocks in a second order of operation.

As shown in fig. 12, first, the pre-read operation may be sequentially performed on n memory blocks in the second operation order. After the pre-reading operation of the resistive random access memory of the first-stage memory block is finished, the pre-reading operation is carried out on the resistive random access memory of the second-stage memory block, and the pre-reading operation of n memory blocks is finished by analogy. In the process of performing the pre-read operation on the (k+1) -th stage memory block, a write operation is performed on the k-th stage memory block, and after the write operation of the k-th stage memory block is ended, a delay operation is performed on the k-th stage memory. After the pre-read operation of the nth stage memory block of the n memory blocks is completed, performing a delay verification operation on the resistive random access memory in the first stage memory block, and performing a write operation on the nth stage memory block; and after the verification operation of the first-stage memory block is finished, performing delay verification operation on the resistive random access memory in the second-stage memory block, and the like to finish the delay verification operation of n memory blocks, wherein k is more than or equal to 1 and less than or equal to n-1.

With continued reference to fig. 12, for example, if the delay verification of the resistive random access memory in the first-stage memory block passes, that is, if the result of the determination of the delay verification operation is yes, the operation on the first-stage memory block is stopped, and a memory block to be processed is selected to replace the first-stage memory block, so as to continue the pipeline operation. As shown in fig. 12, if the delay verification of the kth level (e.g., third level) memory block passes, the kth level memory block may be aligned and delayed to ensure that the timing of the plurality of memory blocks is performed normally, i.e., to ensure that the delay operation lasts for a preset time. For example, the delay verification of the first level memory block passes, then a read-ahead operation may be performed on the new block added after the delay verification operation is performed on the nth level memory block.

As shown in fig. 12, if the result of the delay verification operation of at least one resistive random access memory in the kth stage memory block is no, in the process of performing the delay verification operation on the (k+1) th stage memory block, the writing operation is continuously performed on the resistive random access memory in which the result of the delay verification operation in the kth stage memory block is no, where k is greater than or equal to 1 and less than or equal to n-1. For example, if the second-stage memory block has no delay verification operation of 1 resistive random access memory, then the writing operation is continuously performed on the 1 resistive random access memory in the second-stage memory block during the delay verification operation of the third-stage memory block.

In one embodiment of the present disclosure, if the number of delay verification operations for a certain resistive random access memory reaches a preset upper limit, the write operation, the delay operation, and the delay verification operation may not be continued for the resistive random access memory. For example, the resistive random access memory can be omitted, when the other resistive random access memories except the resistive random access memory in the memory block where the resistive random access memory is located pass the time delay verification, the operation on the memory block is stopped, and the memory block is replaced by a new block. For example, the preset upper limit may be set according to actual conditions, and may be 50 times, 100 times, or the like, for example.

In one embodiment of the present disclosure, when the operation on the kth level memory block is stopped and no new pending memory block is available for replacement, then a null operation is performed on the kth level memory block such that the time elapsed for sequentially performing the operation method on the n memory blocks in the second operation order remains unchanged. The method further ensures that the time of the delay operation performed on the resistive random access memory in each memory block is unchanged.

In the embodiments of the present disclosure, the delay verification operation or the pre-verification operation described above may be performed one or more times, for example, the determination result of 5 delay verification operations determines the determination result of the final delay verification operation.

It should be understood that, although the time lengths of the write operation and the delay verification operation shown in fig. 8A, 8B, 11A, and 11B of the present disclosure are equal, this is merely illustrative, and does not mean that the time of the write operation and the time of the delay verification operation must be equal in actual operation, which may be greater than, equal to, or less than the time of the delay verification operation, which is not limited in the embodiments of the present disclosure.

In one embodiment of the present disclosure, as shown in fig. 11A, 11B, and 12, the number of stages of the pipeline operation, i.e., the number n of memory blocks, may be determined, for example, according to a predetermined time of the delay operation, the pre-read time, and a time-duration relationship between pre-verification/delay verification. The predetermined time of the delay operation may be adjusted according to the number of stages of different pipeline operations.

At least one embodiment of the present disclosure also provides a memory device, for example, fig. 13 shows a schematic diagram of a memory device 1300.

As shown in fig. 13, the memory device 1300 includes at least one resistive memory 1310, a write circuit 1320, a delay circuit 1330, and a verification circuit 1340.

Write circuit 1320 is configured to perform a write operation to at least one resistive random access memory 1310.

And a delay circuit 1330 for performing a delay operation after the write operation, the delay operation lasting for a predetermined time to delay.

The checking circuit 1340 is configured to perform a delay checking operation on the resistive random access memory 1310 after the delay operation, where the delay checking operation includes obtaining a current stored value of the resistive random access memory, and determining whether a difference between the current stored value and a target value of the resistive random access memory is within a preset error range.

In one embodiment of the present disclosure, write circuit 1320 may include, for example, a pulse generator that generates a write pulse that is used to perform a write operation to a resistive random access memory. The verification circuit 1340 may be a current test module for detecting a current value output from the resistive random access memory, so that a stored value may be calculated according to the current value, and then the stored value may be compared with a target value. It should be noted that, in the embodiment of the present disclosure, the verification circuit may perform not only the delay verification operation on the resistive random access memory, but also the pre-verification operation described above on the resistive random access memory.

For example, the delay circuit may be implemented as a dedicated circuit or as comprising a processor and a memory. For example, the memory may be pre-stored with a predetermined time required to perform the delay operation, and when the delay operation needs to be performed, the processor may call the predetermined time from the memory to complete the delay operation.

For example, the processor may be a Central Processing Unit (CPU) or a Field Programmable Gate Array (FPGA) or a single chip Microcomputer (MCU) or a Digital Signal Processor (DSP) or an Application Specific Integrated Circuit (ASIC) or the like having a logic operation device with data processing capability and/or program execution capability. The memory may be variously implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

Fig. 14 shows a schematic diagram of another memory device 1400. As shown in fig. 14, the memory device 1400 includes at least one resistance change memory 1410, a write circuit 1420, a delay circuit 1430, a verify circuit 1440, and a controller 1450.

The write circuit 1420 may receive a write signal from the controller 1450 and write the at least one resistive random access memory 1410 according to the write signal. Write circuit 1420 may also feed back a write operation completed signal to controller 1450.

The delay circuit 1430 is configured to receive the delay signal from the controller 1450, delay the delay signal according to the delay signal, and feed back the delayed signal to the controller 1450.

The check circuit 1440 is configured to receive a control signal from the controller 1450 and perform any one of a read-ahead, a check-ahead, or a delay check operation on the at least one resistive random access memory 1410 according to the control signal.

The controller 1450 is configured to send a write signal to the write circuit 1420, to provide a control signal to the check circuit 1440, and to send a delay signal to the delay circuit 1430 such that the delay circuit 1430 delays according to the delay signal. The controller 1450 may execute the determination logic described above, such as determining whether the difference between the stored value and the target value is within a preset error range.

The stored value (which may be, for example, a conductance value) of the resistive switching memory 1410 may be read by the check circuit 1440 and sent to the controller 1450 so that the controller 1450 determines whether the difference between the stored value and the target value is within a preset error range.

The following points need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A control method of a memory device, wherein the memory device includes a plurality of resistance change memories, the control method comprising:

performing an operation method on at least part of the plurality of resistive random access memories, respectively, the operation method comprising:

performing a write operation on the at least part of the resistive random access memory;

performing a delay operation after the write operation, wherein the delay operation is continued for a predetermined time to delay; and

performing delay verification operation after the delay operation, wherein the delay verification operation comprises obtaining the current stored value of the resistive random access memory, judging whether the difference between the current stored value and the target value of the resistive random access memory is within a preset error range,

wherein a write operation is performed on the at least part of the resistive random access memory; performing a delay operation after the write operation, wherein the delay operation is continued for a predetermined time to delay; and performing a delay verification operation after the delay operation, wherein the delay verification operation includes obtaining a current stored value of the resistive random access memory, and determining whether a difference between the current stored value of the resistive random access memory and a target value is within a preset error range, and includes:

Determining a first sequence of operations on the at least partial resistive switching memory;

sequentially performing the write operations to the at least partial resistive random access memories according to the first operation sequence, wherein after the write operation performed to a first resistive random access memory in the at least partial resistive random access memories is finished, performing the delay operation to the first resistive random access memory, performing the write operation to a second resistive random access memory in the at least partial resistive random access memory, and the like, completing the write operation to the at least partial resistive random access memory;

during the process of executing the writing operation to the last resistive random access memory in the at least partial resistive random access memory, executing the time delay checking operation to the first resistive random access memory in the at least partial resistive random access memory; and

after the delay verification operation of the first resistance random access memory is finished, the delay verification operation is executed on the second resistance random access memory, and the delay verification operation on at least part of the resistance random access memories is finished by the same way,

dividing the plurality of resistive random access memories into N memory blocks, each of the N memory blocks including at least one resistive random access memory;

Selecting N memory blocks from the N memory blocks, and determining a second order of operation of the N memory blocks; and

sequentially performing the operation method for the n memory blocks in the second operation order,

wherein the at least one resistive random access memory in each memory block performs the operation method in parallel, N is an integer greater than or equal to 2, N satisfies an integer greater than or equal to 2 and less than or equal to N,

the n memory blocks are respectively determined as a first-level memory block, a second-level memory block, …, an nth-level memory block according to the second operation order,

if the judgment result of the delay verification operation of all the resistance random access memories in the k-stage memory block is yes, stopping the operation of the k-stage memory block, determining one from the memory blocks to be processed to replace the k-stage memory block,

the memory blocks to be processed are other memory blocks except the N memory blocks in the N memory blocks.

2. The control method according to claim 1, further comprising:

if the judgment result of the delay verification operation is negative, continuing to execute the write operation, the delay operation and the delay verification operation; or alternatively

And if the judgment result of the delay verification operation is yes, ending the operation method.

3. The control method according to claim 1, further comprising:

after the write operation and before the delay operation, a pre-verify operation is performed on the resistive random access memory,

wherein the pre-verification operation comprises:

acquiring a current storage value of the resistance random access memory; and

and judging whether the difference between the current stored value of the resistance random access memory and the target value is within the preset error range.

4. The control method of claim 3, wherein the performing a delay operation after the write operation comprises:

if the judgment result of the pre-verification operation is negative, the write operation and the pre-verification operation are sequentially executed on the resistive random access memory after the pre-verification operation until the judgment result of the pre-verification operation is positive; and

and if the judgment result of the pre-checking operation is yes, executing the delay operation on the resistance random access memory.

5. The control method according to claim 3, further comprising:

and if the judgment result of the pre-verification operation is yes, and the judgment result of the delay verification operation is yes, ending the operation method.

6. The control method according to any one of claims 1 to 5, further comprising:

performing a read-ahead operation on the resistive random access memory prior to the write operation; wherein,

the pre-read operation includes:

reading the current storage value of the resistance random access memory; and

and determining a write pulse adopted by the write operation according to the current stored value of the resistance random access memory.

7. The control method according to any one of claims 1 to 5, wherein the obtaining the current stored value of the resistive random access memory includes:

applying a read voltage to the resistive random access memory;

acquiring a current value output by the resistance random access memory under the action of the reading voltage; and

and determining the current storage value of the resistance change memory according to the current value and the reading voltage.

8. The control method according to any one of claims 1 to 5, wherein the predetermined time has a value in a range of 1ms to 10s.

9. The control method of claim 1, wherein the sequentially performing the operation method on the n memory blocks in the second operation order comprises:

performing the write operation to a resistive random access memory in the first level memory block;

After the writing operation of the resistive random access memory in the first-stage memory block is finished, executing the delay operation on the first-stage memory block, executing the writing operation on the resistive random access memory in the second-stage memory block, and completing the writing operation of the n memory blocks by analogy;

in the process of executing the writing operation on the nth stage memory block, executing the delay verification operation on all the resistance random access memories in the first stage memory block; and

and after the delay verification operation of the resistance random access memory in the first-stage memory block is finished, executing the delay verification operation on the resistance random access memory in the second-stage memory block, and the delay verification operation of the n memory blocks is finished by the same.

10. The control method according to claim 1, wherein the operation method further includes:

performing a read-ahead operation on the resistive random access memory prior to the write operation; the pre-reading operation comprises the step of reading the current stored value of the resistance change memory; determining a write pulse adopted by the write operation according to the current stored value of the resistance random access memory;

the method for sequentially executing the operation method on the n memory blocks according to the second operation sequence comprises the following steps:

Performing the pre-read operation on the resistive random access memory in the first level memory block;

after the pre-reading operation of the resistive random access memory of the first-stage memory block is finished, executing the pre-reading operation on the resistive random access memory of the second-stage memory block, and finishing the pre-reading operation of the n memory blocks by analogy;

performing the write operation on a (k+1) -th-level memory block during the pre-read operation on the (k+1) -th-level memory block, and performing a delay operation on the (k) -th-level memory after the write operation on the (k+1) -th-level memory block is completed;

after the pre-read operation of an nth stage memory block of the n memory blocks is completed, performing the delay verification operation on a resistive random access memory in the first stage memory block, and performing the write operation on the nth stage memory block; and

after the delay verification operation of the first-stage memory block is finished, the delay verification operation is executed on the resistance random access memory in the second-stage memory block, and the delay verification operation of the n memory blocks is finished in the similar way,

wherein k is more than or equal to 1 and less than or equal to n-1.

11. The control method according to claim 9 or 10, wherein the sequentially performing the operation method on the n memory blocks in the second operation order further includes:

If the judgment result of the delay verification operation of at least one resistive random access memory in the kth stage memory block is no, continuing to execute the write operation on the resistive random access memory in the kth stage memory block, which is no in the judgment result of the delay verification operation, in the process of performing the delay verification operation on the (k+1) th stage memory block,

wherein k is more than or equal to 1 and less than or equal to n-1.

12. The control method of claim 11, wherein the sequentially performing the operation method on the n memory blocks in the second operation order further comprises:

and when the operation on the k-th stage memory block is stopped and no new memory block to be processed can be replaced, performing an idle operation on the k-th stage memory block, so that the time for sequentially performing the operation method on the n memory blocks according to the second operation sequence is kept unchanged.

13. The control method of claim 1, wherein each memory block comprises the same number of resistive random access memories.

14. A storage device, comprising:

a plurality of resistive random access memories;

a write circuit for performing a write operation on at least a portion of the plurality of resistive random access memories;

A delay circuit for performing a delay operation after the write operation, wherein the delay operation is continued for a predetermined time to delay; and

a checking circuit for performing a delay checking operation after the delay operation, wherein the delay checking operation includes obtaining a current stored value of the resistive random access memory, and judging whether a difference between the current stored value and a target value of the resistive random access memory is within a preset error range,

wherein the storage device is configured to perform the following operations:

wherein the plurality of resistive random access memories is divided into N memory blocks, each memory block of the N memory blocks comprising at least one resistive random access memory,

the storage device is further configured to:

the operations are sequentially performed on N memory blocks selected from the N memory blocks in a second order of operation,