CN112071347A

CN112071347A - Operation method of resistive random access memory, control method of memory device, and memory device

Info

Publication number: CN112071347A
Application number: CN202010933272.2A
Authority: CN
Inventors: 高滨; 席悦; 陈俊任; 吴华强; 唐建石; 钱鹤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2020-09-08
Filing date: 2020-09-08
Publication date: 2020-12-11
Anticipated expiration: 2040-09-08
Also published as: CN112071347B

Abstract

An operation method of a resistive random access memory, a control method of a memory device, and a memory device. The operation method of the resistive random access memory comprises the following steps: performing a write operation on the resistive random access memory; performing a delay operation after the write operation, wherein the delay operation lasts for a predetermined time to perform a delay; and executing a delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of acquiring a current stored value of the resistive random access memory and judging whether the difference between the current stored value of the resistive random access memory and the target value is within a preset error range. The operation method of the resistive random access memory can improve the reliability of the stored value stored in the resistive random access memory and improve the accuracy of the calculation result of the resistive random access memory in calculation application.

Description

Operation method of resistive random access memory, control method of memory device, and memory device

Technical Field

Embodiments of the present disclosure relate to an operation method of a resistance change memory, a control method of a memory apparatus, and a memory apparatus.

Background

Resistive Random Access Memory (RRAM) has many advantages such as non-volatility, low power consumption, fast calculation speed, good micro-shrinkage characteristics, and the like, so the RRAM has a good application prospect in the fields of artificial intelligence, neural networks, memories, and the like.

However, the resistive random access memory may be unstable due to a relaxation phenomenon of the resistive random access memory itself, so that a stored storage value is changed, and accuracy of a calculation result of the resistive random access memory in a calculation application is affected.

Disclosure of Invention

At least one embodiment of the present disclosure provides an operation method of a resistance change memory, including: performing a write operation on the resistive random access memory; performing a delay operation after the write operation, wherein the delay operation lasts for a predetermined time to perform a delay; and executing a delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of acquiring a current storage value of the resistive random access memory and judging whether the difference between the current storage value of the resistive random access memory and a target value is within a preset error range.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: if the judgment result of the time delay check operation is negative, continuing to execute the writing operation, the time delay operation and the time delay check operation; or if the judgment result of the time delay check operation is yes, ending the operation method.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: after the write operation and before the delay operation, performing a pre-verify operation on the resistive random access memory, wherein the pre-verify operation includes: acquiring a current storage value of the resistive random access memory; and judging whether the difference between the current stored value of the resistive random access memory and the target value is within the preset error range.

For example, in an operation method provided in an embodiment of the present disclosure, performing a delay operation after the write operation includes: if the judgment result of the pre-verification operation is negative, sequentially executing the writing operation and the pre-verification operation on the resistive random access memory after the pre-verification operation until the judgment result of the pre-verification operation is positive; and if the judgment result of the pre-verification operation is yes, executing the delay operation on the resistive random access memory.

For example, in the operation method provided in an embodiment of the present disclosure, the operation method further includes ending the operation method if the result of the pre-verification operation is yes and the result of the delayed verification operation is yes.

For example, in an operation method provided by an embodiment of the present disclosure, the operation method further includes performing a pre-read operation on the resistive random access memory before the write operation; wherein the pre-read operation comprises: reading a current stored value of the resistive random access memory; and determining a write pulse adopted by the write operation according to the current stored value of the resistive random access memory.

For example, in an operation method provided in an embodiment of the present disclosure, acquiring a current storage value of the resistive random access memory includes: applying a read voltage to the resistive random access memory; acquiring a current value output by the resistive random access memory under the action of the reading voltage; and determining the current storage value of the resistive random access memory according to the current value and the reading voltage.

For example, in the operation method provided in an embodiment of the present disclosure, the predetermined time has a value ranging from 1ms to 10 s.

At least one embodiment of the present disclosure provides a control method of a memory apparatus, wherein the memory apparatus includes a plurality of resistance change memories, the control method including: respectively executing an operation method on at least part of the resistive random access memories, wherein the operation method comprises the following steps: performing a write operation on the resistive random access memory; performing a delay operation after the write operation, wherein the delay operation lasts for a predetermined time to perform a delay; and executing a delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of acquiring a current storage value of the resistive random access memory and judging whether the difference between the current storage value of the resistive random access memory and a target value is within a preset error range.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: performing a pre-read operation on the resistive random access memory before the write operation; the pre-reading operation comprises reading a current storage value of the resistive random access memory; and determining a write pulse adopted by the write operation according to the current stored value of the resistive random access memory.

For example, in an operation method provided by an embodiment of the present disclosure, the performing the operation method on at least some of the resistive random access memories includes: determining a first operation sequence for operating the at least part of the resistive random access memory; sequentially executing the writing operation on the at least partial resistive random access memories according to the first operation sequence, wherein after the writing operation executed on a first resistive random access memory in the at least partial resistive random access memories is finished, the delay operation is executed on the first resistive random access memory, the writing operation is executed on a second resistive random access memory in the at least partial resistive random access memories, and the like, the writing operation on the at least partial resistive random access memories is finished; performing the delay check operation on a first resistive random access memory in the at least part of resistive random access memories in the process of performing the write operation on a last resistive random access memory in the at least part of resistive random access memories; and after the time delay verification operation of the first resistive random access memory is finished, executing the time delay verification operation on the second resistive random access memory, and completing the time delay verification operation on at least part of the resistive random access memories in the same way.

For example, in an operation method provided by an embodiment of the present disclosure, the performing the operation method on at least some of the resistive random access memories includes: dividing the plurality of resistive random access memories into N memory blocks, wherein each of the N memory blocks comprises at least one resistive random access memory; selecting N memory blocks from the N memory blocks and determining a second order of operation for the N memory blocks; and sequentially executing the operation method on the N memory blocks according to the second operation sequence, wherein the at least one resistive random access memory in each memory block executes the operation method in parallel, N is an integer greater than or equal to 2, and N satisfies an integer not less than 2 and not greater than N.

For example, in an operation method provided in an embodiment of the present disclosure, the determining the n memory blocks as a first-level memory block, a second-level memory block, …, and an nth-level memory block according to the second operation order respectively includes: performing the write operation on the resistive random access memory in the first-level memory block; after the writing operation of the resistive random access memory in the first-level memory block is finished, the delay operation is executed on the first-level memory block, the writing operation is executed on the resistive random access memory in the second-level memory block, and the writing operation of the n memory blocks is finished by analogy in sequence; in the process of performing writing operation on the n memory blocks, performing the delay verification operation on all the resistive random access memories in the first-level memory block; and after the time delay verification operation of the resistive random access memory in the first-level memory block is finished, executing the time delay verification operation on the resistive random access memory in the second-level memory block, and completing the time delay verification operation of the n memory blocks in the same way.

For example, in an operation method provided in an embodiment of the present disclosure, the operation method further includes: performing a pre-read operation on the resistive random access memory before the write operation; the pre-reading operation comprises reading a current storage value of the resistive random access memory; determining a write pulse adopted by the write operation according to the current stored value of the resistive random access memory; the method for sequentially executing the operations on the n memory blocks according to the second operation sequence comprises the following steps: performing the pre-read operation on the resistive random access memory in the first-level memory block; after the pre-reading operation of the resistive random access memory of the first-level memory block is finished, the pre-reading operation is executed on the resistive random access memory in the second-level memory block, and the pre-reading operation of the n memory blocks is finished by analogy in sequence; in the process of executing the pre-reading operation on the (k +1) th-level memory block, executing the writing operation on the kth-level memory block, and after the writing operation of the kth-level memory block is finished, executing a delay operation on the kth-level memory; after the pre-read operation of the nth-level memory block of the n memory blocks is completed, performing the delay check operation on the resistive random access memory in the first-level memory block, and performing the write operation on the nth-level memory block; and after the time delay verification operation of the first-level memory block is finished, executing the time delay verification operation on the resistive random access memory in the second-level memory block, and completing the time delay verification operation of the n memory blocks in the same way, wherein k is more than or equal to 1 and less than or equal to n-1.

For example, in an operation method provided in an embodiment of the present disclosure, sequentially executing the operation method on the n memory blocks according to the second operation order further includes: if the judgment result of the delay check operation of at least one resistive random access memory in the kth-level memory block is negative, in the process of performing the delay check operation on the (k +1) th-level memory block, continuously executing the write operation on the resistive random access memory in the kth-level memory block, wherein the judgment result of the delay check operation is negative, and k is more than or equal to 1 and less than or equal to n-1.

For example, in an operation method provided in an embodiment of the present disclosure, the sequentially executing the operation method on the n memory blocks according to the second operation order further includes: if the judgment result of the delay check operation of all the resistive random access memories in the kth-level memory block is yes, stopping the operation on the kth-level memory block, and determining one memory block to be processed to replace the kth-level memory block, wherein the memory block to be processed is other memory blocks except the N memory blocks in the N memory blocks.

For example, in an operation method provided in an embodiment of the present disclosure, the sequentially executing the operation method on the n memory blocks according to the second operation order further includes: and when the operation on the k-th-level memory block is stopped and no new memory block to be processed can be replaced, performing a null operation on the k-th-level memory block, so that the time for sequentially performing the operation method on the n memory blocks according to the second operation sequence is kept unchanged.

For example, in an operation method provided by an embodiment of the present disclosure, each of the memory blocks includes the same number of resistive random access memories.

At least one embodiment of the present disclosure provides a storage apparatus including: at least one resistive random access memory; a write circuit for performing a write operation on the resistance change memory; a delay circuit for performing a delay operation after the write operation, wherein the delay operation lasts for a predetermined time to perform a delay; and the checking circuit is used for executing the delay checking operation after the delay operation, wherein the delay checking operation comprises the steps of acquiring the current stored value of the resistive random access memory and judging whether the difference between the current stored value of the resistive random access memory and the target value is within a preset error range.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic diagram of a resistive random access memory circuit;

fig. 1B shows a structural diagram of a resistance change element R1;

FIG. 1C illustrates a schematic diagram of a process for programming a resistive random access memory;

FIG. 1D is a graph illustrating a random drift phenomenon after a successful programming of a conductance value;

fig. 2A illustrates a flow chart of an operation method of a resistive random access memory provided by at least one embodiment of the present disclosure;

fig. 2B illustrates a schematic diagram of an operation method of a resistive random access memory according to at least one embodiment of the present disclosure;

fig. 2C illustrates a schematic diagram of another operation method of a resistive random access memory provided by at least one embodiment of the present disclosure;

FIG. 3 illustrates a flow chart for performing a delay operation after a write operation;

fig. 4 illustrates a flow chart of an operation method of another resistive random access memory provided by at least one embodiment of the present disclosure;

fig. 5A and 5B show two schematic diagrams of performing a pre-read operation on a resistance change memory before a write operation;

fig. 6 shows a resistance change memory array;

fig. 7 shows a flowchart of a method of operating at least some of the plurality of resistive random access memories, respectively;

fig. 8A illustrates a schematic diagram of an operation method performed on 4 resistive random access memories of a plurality of resistive random access memories, respectively;

fig. 8B is a schematic diagram illustrating another method of operating 4 resistive random access memories of a plurality of resistive random access memories, respectively;

fig. 9 shows a schematic diagram of a division of a plurality of resistive random access memories into N memory blocks; and

FIG. 10 is a flow chart illustrating a method of sequentially performing operations on n memory blocks in a second operational order;

FIG. 11A illustrates a schematic diagram of a method of sequentially performing operations on a plurality of memory blocks;

FIG. 11B is a schematic diagram illustrating another method of sequentially performing operations on a plurality of memory blocks;

FIG. 12 is a schematic diagram showing a method of sequentially performing operations on n memory blocks in a second order of operation;

FIG. 13 shows a schematic diagram of a memory device; and

FIG. 14 shows a schematic diagram of another memory device.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The resistive random access memory is a nonvolatile device which can adjust its conductance state by applying an external stimulus, and can be used as a memory cell or a calculation cell. For example, when the resistive random access memory is used as a memory cell, different electrical conduction states (or resistance states, where resistance and electrical conduction are in reciprocal relation) of the resistive random access memory can be used for storing different data information. When the resistive random access memory is used as a calculation unit, for example, an input voltage may be applied to the resistive random access memory, and an array formed by the resistive random access memory may perform multiply-accumulate calculations in parallel, for example, a conductance value of the resistive random access memory may be used as one multiplier in the multiply calculation of two numbers.

Whether to realize stable and reliable information storage or obtain accurate calculation results, the resistive random access memory is often required to be programmed. The programming of the resistive random access memory may be, for example, adjusting a conductance value (or a resistance value) of the resistive random access memory to a target value by applying a pulse having a certain amplitude and a certain pulse width to the resistive random access memory. However, due to the influence of the working mechanism of the resistive random access memory, after the resistive random access memory is successfully programmed, the resistive random access memory is likely to cause strong random conductance value drift (also called relaxation phenomenon) due to factors such as instability of conductive filaments inside the resistive random access memory, spontaneous migration of oxygen vacancies, capture and release of charges by defects, and the like. This phenomenon causes the conductance value of the resistance change memory to rapidly deviate from the written conductance value in a short time scale (<1s), so that the target value cannot be stably and reliably stored, or the accuracy of the calculation result is affected.

Fig. 1A is a schematic diagram of a resistance change memory circuit. As shown in fig. 1A, the resistive random access memory circuit adopts a 1T1R structure, that is, the resistive random access memory circuit includes a transistor M1 and a resistive element R1.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is a second pole.

The embodiment of the present disclosure does not limit the type of the transistor used, for example, when the transistor M1 is an N-type transistor, its gate is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL inputs a high level; the first pole of the transistor M1 may be a source and configured to be connected to a source line terminal SL, e.g., the transistor M1 may receive a reset voltage through the source line terminal SL; the second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a lower electrode) of the resistive switching element R1, and a first pole (e.g., an upper electrode) of the resistive switching element R1 is connected to the bit line terminal BL, e.g., the resistive switching element R1 may receive a Set (Set) voltage through the bit line terminal BL. For example, when the transistor M1 is a P-type transistor, its gate is connected to the word line terminal WL, for example, the transistor M1 is turned on when the word line terminal WL is low; the first pole of the transistor M1 may be a drain and configured to be connected to a source line terminal SL, e.g., the transistor M1 may receive a Reset (Reset) voltage through the source line terminal SL; the second pole of the transistor M1 may be a source and configured to be connected to the second pole (e.g., the lower electrode) of the resistive switching element R1, and the first pole (e.g., the upper electrode) of the resistive switching element R1 is connected to the bit line terminal BL, e.g., the resistive switching element R1 may receive the set voltage through the bit line terminal BL. It should be noted that the resistive random access memory circuit structure may also be implemented as another structure, for example, a structure in which the second pole of the resistive random access element R1 is connected to the source line terminal SL, or the resistive random access memory may also be a circuit structure including only the resistive random access element R1, which is not limited in this respect. In the following embodiments, the transistors are described as N-type transistors.

The word line terminal WL is used to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. When the resistance change element R1 is operated, for example, a set operation or a reset operation, the transistor M1 needs to be turned on first, that is, a gate of the transistor M1 needs to be applied with an on voltage through the word line terminal WL. After the transistor M1 is turned on, for example, the resistance state of the resistive element R1 can be changed by applying a voltage to the resistive element R1 at the source line terminal SL and the bit line terminal BL. For example, a set voltage may be applied through the bit line terminal BL to cause the resistive switching element R1 to be in a low resistance state; for another example, a reset voltage may be applied through the source terminal SL so that the resistive element R1 is in a high resistance state.

The resistive switching element R1 is a key component in a resistive switching memory array. Fig. 1B shows a structural diagram of a resistance change element R1.

As shown in fig. 1B, the resistance change element R1 may include a resistance change layer 111, a functional layer 112, and an upper electrode 113 and a lower electrode 114 on both sides. The functional layer 112 is an optional layer, and whether the functional layer is added or not can be determined according to the optimization direction of the performance of the resistive random access memory device, and the functional layer is designed correspondingly. The resistance change layer 111 may be a single layer of a single-type binary metal oxide (e.g., NiO, AlOx, etc.), a graphene oxide, or a multi-perovskite oxide (e.g., STO, SZO, PCMO, etc.), or may be a stack of a plurality of layers thereof, for example, a stack of TixN and AlOx.

For example, when a transistor is used as a switching element of the resistance change memory, the lower electrode 114 and the upper electrode 113 of the resistance change element R1 may be connected to, for example, a drain of the transistor and a bit line BL, respectively. The source of the transistor is connected to a source line SL, and the gate is connected to a word line WL. In this way, when a voltage is applied to the bit line BL and the word line WL at the same time, for example, a Set operation can be performed. When voltages are simultaneously applied to the source line SL and the word line WL, for example, a Reset (Reset) operation may be performed. The gate of the transistor functions to turn on the transistor by receiving an on voltage from the word line WL, so that a voltage can be applied to the resistive layer 111 through electrodes on both sides of the resistive element R1. Therefore, in the structure using a transistor as a switching element, it is necessary to turn on the transistor first when applying a voltage to the resistance change layer 111, that is, to apply an on-voltage to the gate of the transistor through the word line WL.

In the embodiments of the present disclosure, for example, the resistive switching element R1 has a threshold voltage, and when the input voltage magnitude is smaller than the threshold voltage of the resistive switching element R1, the resistance value (or conductance value) of the resistive switching element R1 is not changed. In this case, calculation can be performed using the resistance value (or the conductance value) of the resistance change element R1 by inputting a voltage smaller than the threshold voltage; and the resistance value (or the conductance value) of the resistive switching element R1 can be changed by inputting a voltage larger than the threshold voltage.

Fig. 1C shows a schematic diagram of a process for programming a resistive random access memory. In fig. 1C, the ordinate indicates the magnitude of a voltage applied across the resistance change memory, and the abscissa indicates time. Here, Va, which is the minimum pulse voltage applied, is a read voltage, and the currently stored value of the resistance change memory is read by applying the read voltage to the resistance change memory. The currently stored value of the resistive random access memory may be, for example, a conductance value of the resistive random access memory. The read voltage is, for example, smaller than the threshold voltage of the resistance change memory, so that the current conductance value of the resistance change memory is read without changing the resistance value of the resistance change element R1.

In fig. 1C, the other voltages than the read voltage applied to the resistance change memory are a Set voltage (Set voltage) or a Reset voltage (Reset voltage). For example, the Set voltage is a positive voltage pulse, and the Reset voltage is a negative voltage pulse, and the pulse voltage amplitude is the voltage difference between the BL and SL terminals in fig. 1A. The conductance value can be adjusted to be large by applying Set voltage to the resistive random access memory, and the conductance value can be adjusted to be small by applying Reset voltage to the resistive random access memory. In the embodiments of the present disclosure, applying a Set voltage to the resistance change memory is referred to as a Set operation, applying a Reset voltage to the resistance change memory is referred to as a Reset operation, and one Set operation or Reset operation may be a write operation.

In an embodiment of the present disclosure, the resistive random access memory may be programmed using an Incremental Step Program Pulse (ISPP) strategy, that is, the Pulse amplitude used in the Set operation or the Reset operation may be increased in steps. The method comprises the following steps: a process of applying a read voltage to read a current conductance value of the resistance change memory and comparing the conductance value with a target value is called a verify (verify) operation. If the current conductance value of the resistive random access memory is smaller than the target value, performing Set operation, performing verification operation again after the Set operation, and if the current conductance value of the resistive random access memory is still smaller than the target value, applying a Set voltage pulse with the same pulse width and larger amplitude than the current pulse width to perform enhanced Set operation; if the read conductance value is larger than the target value, a Reset operation is required, which is similar to the Set operation. After the conductance value of the resistive random access memory is verified each time, Set operation or Reset operation is carried out to correct the conductance value until the conductance value of the resistive random access memory reaches a target value (or a target range).

The programming method of writing-verifying can realize the writing of the target conductance value, but because of the influence of the working mechanism of the resistive random access memory, the resistive random access memory which successfully completes the writing of the conductance value is likely to generate the conductance value drift (also called relaxation phenomenon) with strong randomness due to factors such as unstable conductive filaments, spontaneous migration of oxygen vacancies, trapping and releasing of charges by defects and the like in the device after operation. This phenomenon causes the conductance value of the resistance change memory to rapidly deviate from the written conductance value in a short time scale (<1s), so that the target value cannot be stably and reliably stored, or the accuracy of the calculation result is affected.

FIG. 1D is a graph illustrating a random drift phenomenon after a successful programming of a conductance value. The different curves in fig. 1D respectively represent the change of the conductance values of several different resistive random access memories randomly selected with time after being successfully programmed. As shown in fig. 1D, the conductance value at time 0 is a value that is successfully programmed (i.e., a required target value), the conductance values of the resistive random access memories all drift within a time scale of 1 second, and the random drift phenomenon has a short time, a large drift degree, and strong randomness.

In order to reduce or eliminate an influence of a relaxation phenomenon of the resistive random access memory on the stored values, so as to improve stability and reliability of the stored values stored by the resistive random access memory, and improve accuracy of calculation results of the resistive random access memory in a calculation application, at least one embodiment of the present disclosure provides an operation method of the resistive random access memory.

Fig. 2A illustrates a flowchart of an operation method of a resistive random access memory according to at least one embodiment of the present disclosure. As shown in FIG. 2A, the method of operation includes operations S10-S30.

In operation S10, a write operation is performed on the resistance change memory.

In one embodiment of the present disclosure, the write operation may be, for example, a Set operation or a Reset operation.

In another embodiment of the present disclosure, the write operation may include, for example, a plurality of Set operations or a plurality of Reset operations, or the write operation may also include at least one Set operation and at least one Reset operation.

In operation S20, a delay operation is performed after the write operation, the delay operation continuing for a predetermined time to delay.

In one embodiment of the present disclosure, the delay operation is a delay performed for a predetermined time after the write operation, that is, an operation after the write operation is performed on the resistance change memory and is performed after a delay for a predetermined time elapses, for example, a delay verify operation hereinafter.

For example, the delay operation may be performed by a delay circuit that performs a delay operation according to a set predetermined time, and does not perform other operations on the resistance change memory for the duration of the delay operation.

For example, if the verify operation needs to be performed on the resistance change memory after the write operation is performed on the resistance change memory, and the predetermined time is 10s, the verify operation may be performed on the resistance change memory after 10s has elapsed after the write operation is performed on the resistance change memory.

In the embodiment of the present disclosure, the predetermined delay time may be set according to a suppression requirement for the relaxation phenomenon and a speed requirement for programming. For example, if the suppression demand for the relaxation phenomenon is high and high-speed programming is not required, a long predetermined time may be set, and the predetermined time may be set to 10s, 5s, 2s, 1s, or the like. If the suppression demand for the relaxation phenomenon is low and high-speed programming is required, a short predetermined time may be set, for example, the predetermined time may be set to 1ms, 2ms, 5ms, 10ms, or the like. One skilled in the art can select an appropriate length of time as the predetermined time according to the suppression requirement for the relaxation phenomenon and the speed requirement for programming.

In operation S30, a delay verifying operation is performed after the delay operation, the delay verifying operation including obtaining a current stored value of the resistive random access memory and determining whether a difference between the current stored value of the resistive random access memory and a target value is within a preset error range.

In an embodiment of the present disclosure, acquiring a current storage value of the resistive random access memory includes: and applying a reading voltage to the resistive random access memory, acquiring a current value output by the resistive random access memory under the action of the reading voltage, and determining a current storage value of the resistive random access memory according to the current value and the reading voltage.

For example, the current stored value of the resistive random access memory may be the current conductance value of the resistive random access memory, or may also be the current resistance value of the resistive random access memory, which is not limited in this embodiment of the present disclosure, and the embodiment of the present disclosure describes using the stored value as the conductance value as an example. For example, a read voltage may be applied to a source line of the resistive random access memory, and the read voltage may be the read voltage Va in fig. 1C above, so that a conductance value of the resistive random access memory may be determined using ohm's law according to a current value output by the bit line.

It should be understood that other technical means may be adopted by a person skilled in the art to obtain the current stored value of the resistive random access memory, for example, a multimeter may be used to obtain the current conductance value or the current resistance value of the resistive random access memory, which is not limited by the embodiment of the present disclosure.

In the embodiment of the present disclosure, the target value may be set in advance. The target value may be, for example, a resistance value. The target value may be, for example, 500 Ω, 10M Ω, etc. The preset error range may be preset according to the calculation accuracy requirement. For example, the preset error range with respect to the target value may be [ -5k Ω, 5k Ω ].

In at least one embodiment of the present disclosure, the operation method of the resistive random access memory ensures accuracy of a verification result by adding a delay operation between a write operation and a delay verification operation. After the delay operation of the preset time, if the relaxation phenomenon does not occur in the resistive random access memory, the probability of recurrence in the subsequent time is very low; from another perspective, it can be understood that the resistive random access memory in which the relaxation phenomenon occurs within the duration of the delay operation can be verified through the delay verifying operation, so that it can be continuously programmed to reach the target value in the subsequent writing operation.

The operation method of the resistive random access memory reduces the influence of relaxation phenomena of the resistive random access memory on the stored value, so that the stability and the reliability of the stored value of the resistive random access memory can be improved, and the accuracy of the calculation result of the resistive random access memory in calculation application is improved.

Fig. 2B illustrates a schematic diagram of an operation method of a resistive random access memory according to at least one embodiment of the present disclosure. Hereinafter, the operation method shown in fig. 2B is collectively referred to as a delay-check scheme.

As shown in fig. 2B, in the delay-verify scheme, after the write operation performed on the resistance change memory is finished, a delay operation is performed, and the delay operation lasts for a predetermined time to perform a delay. And after the time delay of the preset time is continued, performing time delay verification operation on the resistive random access memory so as to judge whether the difference between the current stored value of the resistive random access memory and the target value is within a preset error range through the time delay verification operation.

Fig. 2C illustrates a schematic diagram of another operation method of a resistive random access memory provided by at least one embodiment of the present disclosure. Hereinafter, the operation method shown in fig. 2C is collectively referred to as a check-delay-check scheme.

As shown in fig. 2C, in the verify-delay-verify scheme, after a write operation is performed on the resistance change memory, a pre-verify operation is performed on the resistance change memory. And after the execution of the pre-verification operation is finished, the time delay operation is executed again, and the time delay verification operation is executed again after the time delay operation. The pre-verification operation is similar to the delay verification operation, that is, the pre-verification operation includes obtaining a current stored value of the resistive random access memory, and determining whether a difference between the current stored value of the resistive random access memory and a target value is within the preset error range.

It should be noted that, in the embodiment of the present disclosure, the content of the pre-verification operation execution and the content of the delay verification execution are all performed in a verification manner, that is, the current stored value of the resistive random access memory is obtained, and then it is determined whether a difference between the current stored value of the resistive random access memory and the target value is within the preset error range, where only the occurrence times of the pre-verification operation and the delay verification operation are different.

It should be understood that all the technical solutions of performing the time delay before verifying the resistance random access memory after the write operation are within the scope of the present disclosure, that is, other technical solutions of performing the time delay and verifying multiple combinations also belong to the scope of the present disclosure, for example, a time delay-verifying solution followed by a series of verifying operations, or a verifying-time delay-verifying solution followed by a series of verifying operations all belong to the scope of the present disclosure.

For example, in one embodiment, performing the delay operation after the write operation includes: after each write operation, the pre-verify operation, the delay operation and the delay verify operation are sequentially executed.

In one embodiment, shown in FIG. 2C, performing the delay operation after the write operation includes: if the judgment result of the pre-check operation is negative, then sequentially performing writing operation and pre-check operation on the resistive random access memory after the pre-check operation until the judgment result of the pre-check operation is positive, and if the judgment result of the pre-check operation is positive, performing delay operation on the resistive random access memory.

In the embodiment of the disclosure, when the judgment result of the pre-verification operation is yes, the delay operation is performed on the resistive random access memory, so that the times of performing the delay operation and the delay verification operation can be reduced, and the operation efficiency can be improved under the condition of ensuring that the resistive random access memory has a stable storage value.

The method for performing the delay operation after the write operation described above is described below with reference to the flowchart shown in fig. 3. Fig. 3 shows a flow chart for performing a delay operation after a write operation. As shown in fig. 3, after the write operation is performed on the resistance change memory in operation S10, operations S40 and operations S201-S202 may be performed. For example, a method of performing a latency operation after a write operation may include operations S201-S202.

In operation S40, a pre-verify operation is performed on the resistance change memory.

In operation S201, a judgment result of the pre-verification operation is determined.

If the pre-verifying operation is judged to be negative, that is, the difference between the current stored value of the resistive random access memory and the target value is not within the preset error range, the operations S10 and S40 are executed in a return mode until the pre-verifying operation is judged to be positive.

If the pre-verifying operation is judged to be yes, that is, the difference between the current stored value of the resistance change memory and the target value is within the preset error range, operation S202 is performed.

In operation S202, a delay operation is performed. Note that this operation S202 is similar to the above-described operation S30.

Fig. 4 shows a flowchart of an operation method of another resistive random access memory provided by at least one embodiment of the present disclosure. As shown in fig. 4, the operation method may further include operation S50 on the basis of the operation method described above with reference to fig. 2A.

In operation S50, a determination result of the delay check operation is determined. If the result of the delay verification operation is negative, that is, the difference between the current stored value of the resistive random access memory and the target value is not within the preset error range, the writing operation of S10, the delay operation of S20, and the delay verification operation of S30 are continuously performed. If the judgment result of the delay verification operation is yes, that is, the difference between the current stored value of the resistive random access memory and the target value is within the preset error range, it is indicated that the target value is successfully written, and the operation method can be ended.

In an embodiment of the disclosure, the operation method includes a pre-verification operation, that is, after the write operation and before the delay operation, the pre-verification operation is performed on the resistive random access memory, and if the determination result of the pre-verification operation is yes and the determination result of the delay verification operation is yes, it is indicated that the target value is successfully written, and the operation method may be ended.

For example, in the operation method described above with reference to fig. 3, if the operation S201 determines that the judgment result of the pre-verification operation is yes, operation S202, i.e., a delay operation is performed. Next, a delay check operation may be performed after the delay operation. If the result of the delay check operation is yes, it indicates that the target value is successfully written, and if the result of the delay check operation is no, the operations S10, S20 and S30 are continuously performed.

In one embodiment of the present disclosure, the operating method may further include: and performing a pre-read operation on the resistive random access memory before the write operation. The pre-read operation comprises: and reading the current storage value of the resistive random access memory, and determining a write pulse adopted by the write operation according to the current storage value of the resistive random access memory. In the embodiment of the disclosure, performing a pre-read operation before a write operation may determine a subsequent specific programming operation (including, for example, a set operation and a reset operation) according to a currently stored value (for example, a conductance value) of the resistive random access memory, so as to improve programming efficiency.

Fig. 5A and 5B show two schematic diagrams of performing a pre-read operation on a resistance change memory before a write operation.

As shown in fig. 5A and 5B, a pre-read operation may be performed on the resistive random access memory before the write operation, a currently stored value of the resistive random access memory is acquired through the pre-read operation, and a write pulse employed for the write operation is determined according to the currently stored value of the resistive random access memory.

For example, if the current memory of the resistive random access memory acquired through the pre-read operation is larger than the target value, it may be determined that the write pulse used in the subsequent write operation is a Reset voltage pulse. If the current memory of the resistive random access memory acquired through the pre-read operation is smaller than the target value, it can be determined that the write pulse adopted by the subsequent write operation is a Set voltage pulse.

In an embodiment of the present disclosure, the pre-read operation may be an operation performed when programming the resistance change memory is started. The write pulse used for the first write operation may be determined based on the pre-read operation, and the write pulse may be determined based on the result of the delayed verify operation for the subsequent write operation.

At least one embodiment of the present disclosure also provides a control method of a memory device, which may include a plurality of resistance change memories. The control method includes performing an operation method, which may be the method described above with reference to fig. 2A, on at least some of the resistive random access memories, respectively. That is, the operation method may include: s10, writing operation is carried out on the resistance random access memory; s20, performing a delay operation after the write operation, the delay operation lasting for a predetermined time to perform a delay; and S30, executing the delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of obtaining the current storage value of the resistive random access memory and judging whether the difference between the current storage value of the resistive random access memory and the target value is within the preset error range.

The control method respectively executes the operation method on at least part of the resistive random access memories in the storage device, for example, the operation method is respectively executed on a part of or all of the resistive random access memories in the storage device, so that the stability and the reliability of the storage values of the at least part of the resistive random access memories are ensured, and the accuracy of the calculation results of the at least part of the resistive random access memories in calculation application is improved.

Since operations S10 through S30 have been described above, operations S10 through S30 will not be described again.

In one embodiment of the present disclosure, a plurality of resistive random access memories in one memory device may be arranged in an array, for example, thereby forming one or more resistive random access memory arrays.

Fig. 6 shows a resistance change memory array composed of a plurality of resistance change memory circuits as shown in fig. 1A, for example, a plurality of resistance change memory circuits constitute an array of m rows and n columns, m is an integer greater than 1, and n is an integer greater than or equal to 1. BL <1> and BL <2> … … BL < m > in fig. 6 denote bit lines of the first row and the second row … … and the mth row, respectively, and the resistance change element in the resistance change memory circuit of each row is connected to the bit line corresponding to the row; WL <1>, WL <2> … … WL < n > in fig. 6 indicate word lines of the first column and the second column … …, respectively, and the gate of the transistor in the resistance change memory circuit of each column is connected to the word line corresponding to the column; in fig. 6, SL <1> and SL <2> … … denote source lines of the first column and the second column … …, respectively, and the source of the transistor in the resistance change memory circuit of each column is connected to the source line corresponding to the column.

It should be noted that the resistive random access memory array shown in fig. 6 is only an example, and the embodiments of the present disclosure include, but are not limited to, for example, the Word Line (WL) may be parallel to the Bit Line (BL).

In one embodiment of the present disclosure, the above operation methods may be respectively performed on at least some of the resistive random access memories in the resistive random access memory array.

For example, the above-described operation method may be performed on all the resistive random access memories in the resistive random access memory array, or may be performed on a plurality of resistive random access memories located in some rows and some columns in the resistive random access memory array. As shown in fig. 6, the operation methods described above may be performed on the resistive random access memories 610 to 640, respectively. The operation method may also be performed on several resistive random access memories that are not adjacent to each other, and the embodiments of the present disclosure do not limit the positions of the plurality of resistive random access memories that are performed.

In an embodiment of the present disclosure, the memory device may include a plurality of resistance change memory arrays, and the operation method may be performed on only a plurality of resistance change memories in one resistance change memory array, on a plurality of resistance change memories in a part of the plurality of resistance change memory arrays, or on a plurality of resistance change memories in all of the plurality of resistance change memory arrays.

In one embodiment of the present disclosure, the operating method performed on each resistance change memory further includes: and performing a pre-read operation on the resistive random access memory before the write operation. The pre-reading operation comprises reading a current storage value of the resistive random access memory and determining a write pulse adopted by the write operation according to the current storage value of the resistive random access memory. The operation method is described above with reference to fig. 5A and 5B, and is not described again here.

Fig. 7 shows a flowchart of a method for operating at least some of the plurality of resistive random access memories respectively. As shown in fig. 7, the method may include operations S710-S740.

In operation S710, a first operation sequence for operating at least a portion of the resistance change memory is determined.

In operation S720, writing operations are sequentially performed on at least some of the resistance change memories according to a first operation sequence, wherein after the writing operation performed on a first one of the at least some of the resistance change memories is finished, a delay operation is performed on the first one of the resistance change memories, a writing operation is performed on a second one of the at least some of the resistance change memories, and so on, the writing operation on the at least some of the resistance change memories is completed.

In operation S730, in the process of performing a write operation on the last resistive random access memory in at least some resistive random access memories, a delay verification operation is performed on the first resistive random access memory in the at least some resistive random access memories.

In operation S740, after the delay verification operation of the first resistive random access memory is completed, the delay verification operation is performed on the second resistive random access memory, and so on, the delay verification operation on at least part of the resistive random access memories is completed.

In the embodiment of the disclosure, the method realizes the pipeline operation of the plurality of resistive random access memories, that is, when one resistive random access memory is subjected to delay operation, writing operation can be performed on the other resistive random access memory, so that the time overhead caused by the delay operation and the writing operation is reduced, and the programming efficiency is improved.

In order to facilitate understanding of the embodiments of the present disclosure, the embodiment described in fig. 7 above is described below with reference to fig. 8A, taking the number of at least some resistive random access memories as an example, being 4. However, this does not mean that the number of at least part of the resistive random access memories is limited to 4, and in the present disclosure, the number of at least part of the resistive random access memories may be any number equal to or less than the total number of the resistive random access memories in the memory device.

Fig. 8A illustrates a schematic diagram of an operation method performed on 4 resistive random access memories of a plurality of resistive random access memories, respectively.

For example, a first operation order in which the plurality of resistance change memories are operated may be determined according to a preset order rule. For example, in the resistive random access memory array shown in fig. 6, the order rule may be sequentially executed from top to bottom in a row, and the plurality of resistive random access memories in the same row are sequentially executed from left to right.

For example, at least a portion of the resistive random access memory may include the resistive

random access memory

610 and 640, and the first operation sequence of the resistive

random access memory

610 and 640 may be the resistive random access memory 610, the resistive random access memory 620, the resistive random access memory 630, and the resistive random access memory 640.

As shown in fig. 8A, according to the first operation sequence of the resistive

random access memory

610 and 640, a write operation may be performed on the resistive random access memory 610 first, and after the write operation is performed on the resistive random access memory 610, a delay operation is performed on the resistive random access memory 610. The delay operation may refer to, for example, not performing any operation on the resistance change memory 610.

As shown in fig. 8A, after the writing operation on the resistance random access memory 610 is finished, the writing operation is also performed on the resistance random access memory 620 in the process of performing the delay operation on the resistance random access memory 610, and similar to the resistance random access memory 610, the delay operation is performed on the resistance random access memory 620 after the writing operation on the resistance random access memory 620 is finished.

As shown in fig. 8A, after the writing operation on the resistance random access memory 620 is finished, the writing operation is performed on the resistance random access memory 630, and similar to the resistance random access memory 610 and the resistance random access memory 620, after the writing operation on the resistance random access memory 630 is finished, the delay operation is performed on the resistance random access memory 630.

As shown in fig. 8A, after the writing operation on the resistance random access memory 630 is finished, the writing operation is performed on the resistance random access memory 640, and similar to the resistance

random access memory

610 and 630, after the writing operation on the resistance random access memory 640 is finished, the delay operation is performed on the resistance random access memory 640.

As shown in fig. 8A, in the process of performing a write operation on the last resistive random access memory (i.e., the resistive random access memory 640), a delay time verification operation is performed on the first resistive random access memory (i.e., the resistive random access memory 610).

For example, when the write operation is started to be performed on the resistance change memory 640, the delay time verification operation is performed on the resistance change memory 610. If the difference between the current stored value of the resistive random access memory 610 and the target value is determined not to be within the preset error range in the delay verification operation performed on the resistive random access memory 610, the write operation may be performed on the resistive random access memory 610 again. And, after the delay verification operation performed on the resistive random access memory 610 is finished, the delay verification operation is performed on the resistive random access memory 620. Similar to the resistance random access memory 610, if the difference between the current stored value of the resistance random access memory 620 and the target value is determined not to be within the preset error range in the delay verification operation performed on the resistance random access memory 620, the writing operation may be performed on the resistance random access memory 620 again. And the time delay verification operation of the resistive random access memory 630 and the resistive random access memory 640 is completed by analogy.

Fig. 8B is a schematic diagram illustrating another method for operating 4 resistive random access memories of a plurality of resistive random access memories, respectively.

As shown in fig. 8B, before the writing operation is sequentially performed on the resistance change memory 610, the resistance change memory 620, the resistance change memory 630, and the resistance change memory 640, a pre-reading operation may be sequentially performed on the resistance change memory 610, the resistance change memory 620, the resistance change memory 630, and the resistance change memory 640. The pre-reading operation comprises reading a current storage value of the resistive random access memory and determining a write pulse adopted by the write operation according to the current storage value of the resistive random access memory. For the pre-reading operation, reference may be made to the corresponding description in the above embodiments, which is not described herein again.

Note that, after the write operation and before the delay operation, a pre-verification operation may be performed on the resistance change memory. The method for performing the pre-verification operation on the resistive random access memory is described above with reference to fig. 2C and fig. 3, and is not described herein again.

As described above with reference to fig. 8A and 8B, since the plurality of resistive random access memories form a pipeline operation, the duration of the delay operation of each resistive random access memory in the pipeline is the same, i.e., the delay operation lasts the same predetermined time.

In one embodiment of the present disclosure, the number of the resistive random access memories (i.e., the number of at least some of the resistive random access memories) included in the pipeline operation may be determined according to, for example, a predetermined time of the delay operation, a time of the pre-read operation, and a time length relationship between the pre-verify/delay verify. The predetermined time of the delay operation can be adjusted according to the number of different pipeline operations.

In one embodiment of the present disclosure, the method of respectively operating at least some of the plurality of resistive random access memories includes: dividing a plurality of resistive random access memories into N memory blocks, wherein each memory block in the N memory blocks comprises at least one resistive random access memory; selecting N memory blocks from the N memory blocks and determining a second order of operation for the N memory blocks; and sequentially executing the operation method on the n memory blocks according to a second operation sequence. At least one resistive random access memory in each memory block executes an operation method in parallel, N is an integer greater than or equal to 2, and N satisfies an integer which is greater than or equal to 2 and less than or equal to N. In the embodiment of the disclosure, the method can enable a plurality of resistive random access memory blocks in one memory block to execute the operation method in parallel, thereby further improving the programming efficiency.

In one embodiment of the present disclosure, each of the N memory blocks may include the same number of resistive random access memories. The same number of resistive random access memories per memory block can reduce the complexity of the programming operation and simplify the system design. In another embodiment of the present disclosure, the N memory blocks may include different numbers of resistive random access memories. For example, one memory block may include 1 resistive random access memory, and another memory block may include a plurality of resistive random access memories. In the case where a plurality of resistance change memories are included in a memory block, the plurality of resistance change memories perform the above-described operation methods in parallel, that is, perform a write operation, a delay check operation, and the like in parallel.

In an embodiment of the disclosure, the N memory blocks may be respectively distributed on different resistive random access memory arrays, and the plurality of memory blocks distributed on different resistive random access memory arrays may be cooperatively programmed. Of course, the N memory blocks may also be distributed on the same resistive random access memory array. The positions of the plurality of memory blocks on the same resistive random access memory array may be adjacent or non-adjacent, which is not limited in this embodiment of the disclosure.

In one embodiment of the present disclosure, the second operation order of the n memory blocks may be set in advance, or may also be determined according to an order rule set in advance.

Fig. 9 shows a schematic diagram of dividing a plurality of resistance change memories into N memory blocks. It should be understood that fig. 9 is a schematic diagram of a resistive random access memory array, and does not represent a specific circuit structure and a resistive random access memory structure.

In the example of fig. 9, the plurality of resistance change memories are divided into 4 memory blocks each including 4 resistance change memories therein. The 4 memory blocks are respectively the

memory block

910 and 940.

For example, 4 memory blocks 910- > 940 may be selected from the N memory blocks and the second order of operation of the memory blocks 910- > 940 is determined. For example, the second operation order may be determined as memory block 910, memory block 920, memory block 930, and memory block 940 according to a preset order rule. So that the above-described operation method can be sequentially performed in the order of the memory block 910, the memory block 920, the memory block 930, and the memory block 940. For example, at least one resistive random access memory in each memory block performs the operation method in parallel.

In one embodiment of the present disclosure, the n memory blocks are determined as a first-level memory block, a second-level memory block, …, an nth-level memory block, respectively, in a second operation order. For example, the memory blocks 910, 920, 930, 940 may be determined as a first-level memory block, a second-level memory block, a third-level memory block, and a fourth-level memory block, respectively.

Fig. 10 shows a flow chart of a method of sequentially performing operations on n memory blocks in a second operational order.

As shown in FIG. 10, the method may include operations S1010-S1040.

In operation S1010, a write operation is performed on the resistance change memory in the first-level memory block.

In operation S1020, after the write operation of the resistance change memory in the first-level memory block is finished, a delay operation is performed on the first-level memory block, and a write operation is performed on the resistance change memory in the second-level memory block, and so on, to complete the write operation of the n memory blocks.

In operation S1030, in the process of performing a write operation on the nth-level memory block, a latency check operation is performed on all the resistive random access memories in the first-level memory block.

In operation S1040, after the delay verification operation of the resistive random access memory in the first-level memory block is completed, the delay verification operation is performed on the resistive random access memory in the second-level memory block, and so on, the delay verification operations of the n memory blocks are completed.

In the embodiment of the disclosure, the n memory blocks realize pipeline operation, for example, when a certain memory block of one level performs a delay operation, a write operation can be performed on a memory block of another level, and the pipeline operation mode can reduce the time cost of accumulated delay operation brought by serial programming of memory blocks one by one.

To facilitate understanding of the embodiment of the present disclosure, the method shown in fig. 10 is described below with reference to fig. 11A by taking an example of selecting 4 memory blocks from N memory blocks.

FIG. 11A illustrates a schematic diagram of a method of sequentially performing operations on a plurality of memory blocks.

As shown in fig. 11A, according to the second operation sequence of the memory blocks 910 and 940, a write operation may be performed on the resistive random access memory in the memory block 910 first, and after the write operation performed on the resistive random access memory in the memory block 910 is finished, a delay operation may be performed on the memory block 910. The delay operation does not perform any operation on the resistance change memory in the memory block 910, for example.

As shown in fig. 11A, after the writing operation on the resistance change memory in the memory block 910 is finished, the writing operation is performed on the resistance change memory in the memory block 920 during the delay operation on the memory block 910, and similar to the memory block 910, the delay operation is performed on the memory block 920 after the writing operation on the memory block 920 is finished.

As shown in fig. 11A, after the writing operation on the resistance change memory in the memory block 920 is finished, the writing operation on the resistance change memory in the memory block 930 is performed, and similarly to the memory block 910 and the memory block 920, after the writing operation on the memory block 930 is finished, the delay operation is performed on the memory block 930.

As shown in fig. 11A, after the write operation on the memory block 930 is finished, the write operation is performed on the memory block 940, and similar to the

memory block

910 and 930, after the write operation on the memory block 940 is finished, the delay operation is performed on the memory block 940.

As shown in fig. 11A, in performing a write operation on a memory block of the last level, i.e., memory block 940, a latency check operation is performed on a memory block of the first level.

For example, at the beginning of a write operation to memory block 940, a latency check operation is performed to memory block 910. If the delay check operation performed on the memory block 910 determines that the difference between the currently stored value of the memory block 910 and the target value is not within the preset error range, the write operation may be performed on the memory block 910 again. And, after the latency check operation performed on the memory block 910 is finished, the latency check operation is performed on the memory block 920. Similar to memory block 910, if the latency checking operation performed on memory block 920 determines that the currently stored value of memory block 920 is not within the predetermined error range from the target value, the write operation may be performed on memory block 920 again. And so on to complete the latency check operations for memory block 930 and memory block 940.

In one embodiment of the present disclosure, the operating method performed on each resistance change memory further includes: performing a pre-read operation on the resistive random access memory before a write operation; the pre-reading operation comprises reading the current storage value of the resistive random access memory; and determining a write pulse adopted by the write operation according to the current stored value of the resistive random access memory.

In this embodiment, sequentially performing the operation method on the n memory blocks in the second operation order includes: performing pre-reading operation on the resistive random access memory in the first-level memory block; after the pre-reading operation of the resistive random access memory of the first-level memory block is finished, performing the pre-reading operation on the resistive random access memory in the second-level memory block, and repeating the steps to finish the pre-reading operation of the n memory blocks; in the process of executing pre-reading operation on the (k +1) th-level memory block, executing writing operation on the k-level memory block, and after the writing operation of the k-level memory block is finished, executing delay operation on the k-level memory; after completing the pre-reading operation of the nth-level memory block in the n memory blocks, performing a delay check operation on the resistive random access memory in the first-level memory block, and performing a write operation on the nth-level memory block; and after the verification operation of the first-level memory block is finished, performing delay verification operation on the resistive random access memory in the second-level memory block, and completing the delay verification operation of n memory blocks in the same way, wherein k is more than or equal to 1 and less than or equal to n-1.

FIG. 11B illustrates a schematic diagram of a method of sequentially performing operations on a plurality of memory blocks. A control method for sequentially executing the operation method on n memory blocks will be described with reference to fig. 9 and 11B. As shown in fig. 9, the plurality of resistance change memories are divided into 4 memory blocks, and each memory block includes 4 resistance change memories therein. The 4 memory blocks are respectively the

memory block

910 and 940. The memory blocks 910, 920, 930, 940 may be determined as, for example, first-level memory blocks, second-level memory blocks, third-level memory blocks, fourth-level memory blocks, respectively.

As shown in fig. 11B, a pre-read operation is performed on the resistance change memory in the memory block 910; after the pre-reading operation of the resistive random access memory of the memory block 910 is finished, performing the pre-reading operation on the resistive random access memory in the memory block 920; after the pre-reading operation of the resistive random access memory of the memory block 920 is finished, the pre-reading operation is performed on the resistive random access memory in the memory block 930; after the pre-read operation of the resistance change memory of the memory block 930 is finished, the pre-read operation is performed on the resistance change memory in the memory block 940.

In the process of performing pre-read operation on the resistive random access memory in the memory block 920, performing write operation on the resistive random access memory in the memory block 910, and after the write operation of the memory block 910 is finished, performing delay operation on the memory block 910; after completing the pre-read operation of the last-stage memory block (i.e., the memory block 940), performing a delay check operation on the resistive random access memory in the memory block 910, and performing a write operation on the resistive random access memory in the memory block 940; and after the verification operation of the memory block 910 is finished, performing a delay verification operation on the resistive random access memory in the memory block 920, and so on to complete the delay verification operation of the 4 memory blocks.

In one embodiment of the present disclosure, a pre-verify operation may be included after a write operation and before a delay operation. And if the judgment result of the pre-verification operation is that the difference between the current stored value of the resistive random access memory and the target value is not within the preset error range, executing the writing operation and the pre-verification operation again until the judgment result of the pre-verification operation is yes. And if the judgment result of the pre-verification operation is that the difference between the current stored value of the resistive random access memory and the target value is within the preset error range, sequentially executing the time delay operation and the time delay verification operation.

In one embodiment of the present disclosure, if a pre-verify operation is included after a write operation and before a delay operation, in a case where a determination result that a memory block of a subsequent stage reaches the pre-verify operation before a memory block of a previous stage is yes, the memory block of the subsequent stage may perform a dummy operation to wait for the determination result of the pre-verify operation of the memory block of the previous stage to be yes. And after the previous-stage memory block finishes the time delay check operation, the next-stage memory block executes the time delay check operation. For example, the idle operation may be no operation, or may be an idle running preset program.

In one embodiment of the present disclosure, the method of sequentially performing operations on the n memory blocks in the second operation order further includes: if the judgment result of the delay check operation of at least one resistive random access memory in the kth-level memory block is negative, in the process of performing the delay check operation on the (k +1) th-level memory block, continuously performing the write operation on the resistive random access memory of which the judgment result of the delay check operation in the kth-level memory block is negative, wherein k is more than or equal to 1 and less than or equal to n-1.

For example, the second-level memory block includes 4 resistive random access memories, and if the result of the determination of the delay verification operation of 1 resistive random access memory is negative, the write operation is continuously performed on the 1 resistive random access memory in the second-level memory block during the delay verification operation of the third-level memory block.

In one embodiment of the present disclosure, the method of sequentially performing operations on the n memory blocks in the second operation order further includes: and if the judgment result of the delay verification operation of all the resistive random access memories in the kth-level memory block is yes, stopping the operation on the kth-level memory block, and determining one memory block to be processed to replace the kth-level memory block. The memory blocks to be processed are other memory blocks except N memory blocks in the N memory blocks.

In the embodiment of the disclosure, after one memory block is successfully programmed, another new memory block is added into the pipeline operation, so that the number of stages in the pipeline operation is ensured to be unchanged, and thus the time of the delay operation performed on the resistive random access memory in each memory block is ensured to be unchanged.

For example, a plurality of resistance change memories in one memory device are divided into 10 memory blocks, and 4 memory blocks are selected from the 10 memory blocks to sequentially perform the above-described pipelining. And if the judgment result of the delay check operation of all the resistive random access memories in the first-level memory block is yes, stopping the operation of the first-level memory block, and selecting one from the remaining 6 memory blocks to replace the first-level memory block.

Fig. 12 is a diagram illustrating a method of sequentially performing operations on n memory blocks in a second order of operation.

As shown in fig. 12, the pre-read operations may be performed on the n memory blocks sequentially in the second operation order first. After the pre-reading operation of the resistive random access memory of the first-level memory block is finished, the pre-reading operation is executed on the resistive random access memory in the second-level memory block, and the pre-reading operation of the n memory blocks is finished by analogy in sequence. And in the process of executing the pre-reading operation on the (k +1) th-level memory block, executing a writing operation on the k-th-level memory block, and after the writing operation of the k-th-level memory block is finished, executing a delaying operation on the k-th-level memory. After completing the pre-reading operation of the nth-level memory block in the n memory blocks, performing a delay check operation on the resistive random access memory in the first-level memory block, and performing a write operation on the nth-level memory block; and after the verification operation of the first-level memory block is finished, performing delay verification operation on the resistive random access memory in the second-level memory block, and completing the delay verification operation of n memory blocks in the same way, wherein k is more than or equal to 1 and less than or equal to n-1.

With continued reference to fig. 12, for example, if the delay check of the resistance change memory in the first-level memory block passes, that is, the determination result of the delay check operation is yes, the operation on the first-level memory block is stopped, and one to-be-processed memory block is selected to replace the first-level memory block, so as to continue to perform the pipeline operation. As shown in fig. 12, if the latency check of the kth-level (e.g., third-level) memory block passes, the kth-level memory block may be aligned for latency to ensure that the timings of the plurality of memory blocks are normally executed, i.e., to ensure that the latency operation lasts for the preset time. For example, if the latency check of the first-level memory block passes, then a pre-read operation may be performed on the added new block after the latency check operation is performed on the nth-level memory block.

As shown in fig. 12, if the determination result of the delay verification operation of at least one resistive random access memory in the kth-level memory block is negative, in the process of performing the delay verification operation on the (k +1) th-level memory block, the write operation is continuously performed on the resistive random access memory of which the determination result of the delay verification operation in the kth-level memory block is negative, where k is greater than or equal to 1 and is less than or equal to n-1. For example, if the result of the determination of the delay verification operation of 1 resistive random access memory in the second-level memory block is negative, then in the process of performing the delay verification operation on the third-level memory block, the write operation is continuously performed on the 1 resistive random access memory in the second-level memory block.

In an embodiment of the present disclosure, if the number of times of the delay verification operation for a certain resistive random access memory reaches a preset upper limit, the write operation, the delay operation, and the delay verification operation may not be performed on the resistive random access memory any more. For example, the resistive random access memory can be ignored, and when the other resistive random access memories except the resistive random access memory in the memory block in which the resistive random access memory is located pass the delay verification, the operation of the memory block is stopped, and the memory block is replaced by a new block. For example, the preset upper limit may be set according to actual conditions, and may be, for example, 50 times, 100 times, and the like.

In one embodiment of the present disclosure, when no new memory block to be processed can be replaced after stopping the operation on the k-th-level memory block, a null operation is performed on the k-th-level memory block, so that the time elapsed for sequentially performing the operation method on the n memory blocks in the second operation order remains unchanged. The method further ensures that the time of the delay operation executed on the resistive random access memory in each memory block is not changed.

In the embodiment of the present disclosure, the delay check operation or the pre-check operation described above may be performed one or more times, for example, the judgment result of 5 times of the delay check operations determines the judgment result of the final delay check operation.

It should be understood that, although the time lengths of the write operation and the delayed check operation are shown in fig. 8A, 8B, 11A, and 11B of the present disclosure as being equal, this is only illustrative, and does not mean that the time of the write operation and the time of the delayed check operation must be equal in practice, and the time of the write operation may be greater than, equal to, or less than the time of the delayed check operation in practice, which is not limited by the embodiments of the present disclosure.

In one embodiment of the present disclosure, as shown in fig. 11A, 11B and 12, the number of stages of the pipeline operation, i.e., the number n of memory blocks, may be determined according to the predetermined time of the delay operation, the read-ahead time and the time length relationship between the pre-check and the delay check, for example. The predetermined time of the delay operation may be adjusted according to the number of stages of the different pipeline operations.

At least one embodiment of the present disclosure also provides a memory device, for example, fig. 13 shows a schematic diagram of a memory device 1300.

As shown in fig. 13, the memory device 1300 includes at least one resistive random access memory 1310, a write circuit 1320, a delay circuit 1330, and a check circuit 1340.

A write circuit 1320 for performing a write operation on the at least one resistive random access memory 1310.

The delay circuit 1330 is configured to perform a delay operation after the write operation, the delay operation lasting for a predetermined time to perform a delay.

The calibration circuit 1340 is configured to perform a delay calibration operation on the resistive random access memory 1310 after the delay operation, where the delay calibration operation includes obtaining a current stored value of the resistive random access memory and determining whether a difference between the current stored value of the resistive random access memory and a target value is within a preset error range.

In one embodiment of the present disclosure, the write circuit 1320 may include, for example, a pulse generator that generates a write pulse with which a write operation is performed on the resistance change memory. The check circuit 1340 may be a current test module configured to detect a current value output by the resistive random access memory, so as to calculate a stored value according to the current value, and then compare the stored value with a target value. It should be noted that, in the embodiment of the present disclosure, the verification circuit may perform not only the delay verification operation on the resistive random access memory, but also perform the pre-verification operation described above on the resistive random access memory.

For example, the delay circuit may be implemented as a dedicated circuit or as including a processor and a memory. For example, the memory may store a predetermined time required for performing the delay operation in advance, and when the delay operation needs to be performed, the processor may call the predetermined time from the memory to complete the delay operation.

For example, the processor may be a Central Processing Unit (CPU), a field programmable logic array (FPGA), a single chip Microcomputer (MCU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or other logic operation device with data processing capability and/or program execution capability. The memory may be implemented in any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

Fig. 14 shows a schematic diagram of another memory device 1400. As shown in fig. 14, the memory device 1400 includes at least one resistance change memory 1410, a write circuit 1420, a delay circuit 1430, a check circuit 1440, and a controller 1450.

The write circuit 1420 may receive a write signal from the controller 1450 and perform a write operation on the at least one resistance change memory 1410 according to the write signal. Write circuit 1420 may also feed back a signal to controller 1450 that the write operation is complete.

The delay circuit 1430 is configured to receive the delay signal from the controller 1450, delay the delay signal, and feed back the delayed signal to the controller 1450.

The check circuit 1440 is configured to receive a control signal from the controller 1450, and perform any one of a pre-read, a pre-check, or a delay check operation on the at least one resistive random access memory 1410 according to the control signal.

The controller 1450 is used to send a write signal to the write circuit 1420, to provide a control signal to the check circuit 1440, and to send a delay signal to the delay circuit 1430, so that the delay circuit 1430 is delayed according to the delay signal. The controller 1450 may execute the above-described determination logic, for example, to determine whether the difference between the stored value and the target value is within a preset error range.

The stored value (which may be, for example, a conductance value) of the resistive random access memory 1410 may be read by the verification circuit 1440 and transmitted to the controller 1450 so that the controller 1450 determines whether the difference of the stored value from the target value is within a preset error range.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. An operation method of a resistance change memory includes:

performing a write operation on the resistive random access memory;

performing a delay operation after the write operation, wherein the delay operation lasts for a predetermined time to perform a delay; and

and executing a delay verification operation after the delay operation, wherein the delay verification operation comprises the steps of acquiring a current stored value of the resistive random access memory and judging whether the difference between the current stored value of the resistive random access memory and a target value is within a preset error range.

2. The method of operation of claim 1, further comprising:

if the judgment result of the time delay check operation is negative, continuing to execute the writing operation, the time delay operation and the time delay check operation; or

And if the judgment result of the time delay check operation is yes, ending the operation method.

3. The method of operation of claim 1, further comprising:

performing a pre-verify operation on the resistive random access memory after the write operation and before the delay operation,

wherein the pre-verification operation comprises:

acquiring a current storage value of the resistive random access memory; and

and judging whether the difference between the current stored value of the resistive random access memory and the target value is within the preset error range.

4. The method of operation of claim 3, wherein said performing a delay operation after said write operation comprises:

if the judgment result of the pre-verification operation is negative, sequentially executing the writing operation and the pre-verification operation on the resistive random access memory after the pre-verification operation until the judgment result of the pre-verification operation is positive; and

and if the judgment result of the pre-verification operation is yes, executing the delay operation on the resistive random access memory.

5. The method of operation of any of claims 1-4, further comprising:

performing a pre-read operation on the resistive random access memory before the write operation; wherein the content of the first and second substances,

the pre-read operation comprises:

reading a current stored value of the resistive random access memory; and

and determining a write pulse adopted by the write operation according to the current stored value of the resistive random access memory.

6. A control method of a memory apparatus, wherein the memory apparatus includes a plurality of resistance change memories, the control method comprising:

respectively executing an operation method on at least part of the resistive random access memories, wherein the operation method comprises the following steps:

performing a write operation on the resistive random access memory;

7. The control method according to claim 6, wherein the performing the operation method on at least some of the plurality of resistive random access memories respectively comprises:

dividing the plurality of resistive random access memories into N memory blocks, wherein each of the N memory blocks comprises at least one resistive random access memory;

selecting N memory blocks from the N memory blocks and determining a second order of operation for the N memory blocks; and

sequentially executing the operation method on the n memory blocks in the second operation order,

the at least one resistive random access memory in each memory block executes the operation method in parallel, N is an integer greater than or equal to 2, and N is an integer which is greater than or equal to 2 and less than or equal to N.

8. The control method according to claim 7, wherein the n memory blocks are respectively determined as a first-level memory block, a second-level memory block, …, and an nth-level memory block in the second operation order, and the sequentially performing the operation method on the n memory blocks in the second operation order includes:

performing the write operation on the resistive random access memory in the first-level memory block;

after the writing operation of the resistive random access memory in the first-level memory block is finished, the delay operation is executed on the first-level memory block, the writing operation is executed on the resistive random access memory in the second-level memory block, and the writing operation of the n memory blocks is finished by analogy in sequence;

in the process of performing writing operation on the nth-level memory block, performing the delay check operation on all the resistive random access memories in the first-level memory block; and

and after the time delay verification operation of the resistive random access memory in the first-level memory block is finished, executing the time delay verification operation on the resistive random access memory in the second-level memory block, and completing the time delay verification operation of the n memory blocks in the same way.

9. The control method of claim 7, wherein the operating method further comprises:

performing a pre-read operation on the resistive random access memory before the write operation; the pre-reading operation comprises reading a current storage value of the resistive random access memory; determining a write pulse adopted by the write operation according to the current stored value of the resistive random access memory;

the method for sequentially executing the operations on the n memory blocks according to the second operation sequence comprises the following steps:

performing the pre-read operation on the resistive random access memory in the first-level memory block;

after the pre-reading operation of the resistive random access memory of the first-level memory block is finished, the pre-reading operation is executed on the resistive random access memory in the second-level memory block, and the pre-reading operation of the n memory blocks is finished by analogy in sequence;

in the process of executing the pre-reading operation on the (k +1) th-level memory block, executing the writing operation on the kth-level memory block, and after the writing operation of the kth-level memory block is finished, executing a delay operation on the kth-level memory;

after the pre-read operation of the nth-level memory block of the n memory blocks is completed, performing the delay check operation on the resistive random access memory in the first-level memory block, and performing the write operation on the nth-level memory block; and

after the time delay verification operation of the first-level memory block is finished, the time delay verification operation is executed on the resistive random access memory in the second-level memory block, and the time delay verification operation of the n memory blocks is finished by analogy,

wherein k is more than or equal to 1 and less than or equal to n-1.

10. A memory device, comprising:

at least one resistive random access memory;

a write circuit for performing a write operation on the resistance change memory;

a delay circuit for performing a delay operation after the write operation, wherein the delay operation lasts for a predetermined time to perform a delay; and

and the checking circuit is used for executing the delay checking operation after the delay operation, wherein the delay checking operation comprises the steps of acquiring the current stored value of the resistive random access memory and judging whether the difference between the current stored value of the resistive random access memory and the target value is within a preset error range.