CN115811309A - Switch driving circuit for R-2R resistance network type digital-to-analog converter - Google Patents
Switch driving circuit for R-2R resistance network type digital-to-analog converter Download PDFInfo
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- CN115811309A CN115811309A CN202211547676.3A CN202211547676A CN115811309A CN 115811309 A CN115811309 A CN 115811309A CN 202211547676 A CN202211547676 A CN 202211547676A CN 115811309 A CN115811309 A CN 115811309A
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Abstract
The invention discloses a switch driving circuit for R-2R resistance network type digital-to-analog converter, comprising: the complementary differential signal generating circuit, the synchronous circuit, the latch circuit and the current source differential switch turn off the suppression circuit at the same time; the complementary differential signal generating circuit, the synchronous circuit, the latch circuit and the current source differential switch are connected in series in sequence; the current source differential switch simultaneous turn-off suppression circuit consists of a plurality of groups of same NMOS switch tubes and a plurality of same capacitors C so as to obtain a larger slew rate; the invention can make the current source switch control signal of the R-2R resistance network type digital-to-analog converter switch at the same time under the control of the clock, prevent the phenomenon of simultaneous turn-off, reduce the clock feed-through and output burrs, and improve the matching degree of the R-2R resistance network and the conversion precision of the R-2R resistance network digital-to-analog converter.
Description
Technical Field
The invention relates to the field of digital-to-analog converters, in particular to a switch driving circuit for an R-2R resistance network type digital-to-analog converter.
Background
The existing Digital-to-analog converter (DAC) mainly adopts three structures of voltage scaling, current scaling and charge scaling. The R-2R resistor network type digital-to-analog converter structure in current scaling is widely applied to sensors such as temperature sensors due to small power consumption, compact structure and moderate precision.
However, in the R-2R resistor network type digital-to-analog converter, when the switching signals are not synchronized or the MOS transistor is used as a switch, the source voltage fluctuation and clock feedthrough thereof affect the performance of the DAC, such as conversion accuracy. Although the existing switch driving circuit can synchronize the input signals of the digital-to-analog converter, the conditions of clock feed-through, output of glitches and simultaneous disconnection of a multi-bit switch during switching exist at the same time, so that the matching degree of an R-2R resistor network and the conversion precision of an R-2R type resistor network digital-to-analog converter are influenced.
Disclosure of Invention
The purpose of the invention is as follows: it is an object of the present invention to provide a switch driving circuit for an R-2R resistor network type digital-to-analog converter to solve the problems of the background art.
The technical scheme is as follows: the invention relates to a switch driving circuit for an R-2R resistance network type digital-to-analog converter, which comprises: the complementary differential signal generating circuit, the synchronous circuit, the latch circuit and the current source differential switch turn off the suppression circuit at the same time; the complementary differential signal generating circuit, the synchronous circuit, the latch circuit and the current source differential switch are simultaneously turned off and the suppression circuit are sequentially cascaded; the current source differential switch simultaneous turn-off suppression circuit is composed of a plurality of groups of same NMOS switch tubes and a plurality of same capacitors C.
Further, the complementary differential signal generating circuit includes: a first inverter, a second inverter, and a third inverter; the input ends of the first inverter and the third inverter are connected with input signals; the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the second inverter and the output end of the third inverter constitute a differential output signal of the complementary differential signal generating circuit.
Further, the synchronization circuit includes: the first NMOS switch tube and the second NMOS switch tube are connected; the drain electrodes of the NMOS switch tube and the second NMOS switch tube are respectively connected with the output end A of the second phase inverter and the output end B of the third phase inverter, and the grid electrodes of the NMOS switch tube and the second NMOS switch tube are both connected with a clock signal clk.
Further, the latch circuit includes: a fourth inverter and a fifth inverter; the input end of the fourth inverter is connected with the source electrode of the first NMOS tube and the output end XP of the fifth inverter at the same time; and the input end of the fifth phase inverter is simultaneously connected with the source electrode of the second NMOS switching tube and the output end XN of the fourth phase inverter.
Furthermore, the current source differential switch simultaneous turn-off suppression circuit is composed of four groups of same NMOS switch tubes and two same capacitors C; each group of NMOS switch tubes consists of N NMOS tubes which are connected in parallel; the grid electrode of the first group of NMOS switching tubes is connected with the output end XP of the fifth inverter; the drain electrode of the first group of NMOS switch tubes is connected with a low power supply voltage VDDL; the source electrode of the first group of NMOS switching tubes is a first switching drive signal S a An output terminal of (a); the grid electrode of the second group of NMOS switching tubes is connected with the output end XN of the fourth phase inverter; the drain electrode of the second group of NMOS switch tubes is connected with a low power supply voltage VDDL; the source electrode of the second group of NMOS switch tubes is a second switch driving signal S b An output terminal of (a); the grid electrode of the NMOS switching tube of the third group is connected with the output end XN of the fourth phase inverter; the source electrode of the NMOS switching tube of the third group is connected with the ground GND; the drain electrode of the third group of NMOS switching tubes is connected with a first switch driving signal S a (ii) a The grid electrode of the NMOS switching tube in the fourth group is connected with the output end XP of the fifth phase inverter; the source electrode of the NMOS switch tube of the fourth group is connected with the grounding GND; the drain electrode of the NMOS switching tube of the fourth group is connected with a second switching drive signal S b (ii) a The first switch drive signal S a And a second switch drive signal S b The terminals are respectively connected in parallel with a capacitor C (namely connected to the ground through the capacitor).
Further, the current source differential switch simultaneously turns off the power supply of the suppression circuit to be half of the power supply of the complementary differential signal generation circuit.
Has the advantages that: compared with the prior art, the invention can switch the current source switch control signals of the R-2R resistance network type digital-to-analog converter at the same time under the control of the clock, prevent the phenomenon of simultaneous turn-off, reduce clock feed-through and output burrs, and improve the matching degree of the R-2R resistance network and the conversion precision of the R-2R resistance network digital-to-analog converter.
Drawings
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a circuit diagram of an inverter according to the present invention;
FIG. 3 is a circuit diagram of the current source differential switch simultaneous turn-off suppression circuit of the present invention;
FIG. 4 shows the current source differential switch driving signal (S) according to the present invention a ，S b ) And (4) a time sequence simulation diagram.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings.
As shown in fig. 1, a switch driving circuit for an R-2R resistor network type digital-to-analog converter according to the present invention includes: the complementary differential signal generating circuit 10, the synchronizing circuit 20, the latch circuit 30, and the current source differential switch simultaneous turn-off suppressing circuit 40; the complementary differential signal generating circuit 10, the synchronizing circuit 20, the latch circuit 30 and the current source differential switch simultaneous turn-off suppressing circuit 40 are cascaded in sequence.
The complementary differential signal generating circuit 10 includes: a first inverter 101, a first inverter 102, and a third inverter 103; the input ends of the first inverter 101 and the third inverter 103 are both connected with an input signal D; the output end of the first inverter 101 is connected with the input end of the second inverter 102; the output terminal a of the second inverter 102 and the output terminal B of the third inverter 103 constitute the differential output signal of the complementary differential signal generating circuit 10.
The synchronization circuit 20 includes: a first NMOS transistor 201 and a second NMOS transistor 202; the drains of the first NMOS transistor 201 and the second NMOS transistor 202 are respectively connected with the output end a of the second inverter 102 and the output end B of the third inverter 103; the gates of the NMOS transistor 201 and the second NMOS transistor 202 are both connected to the clock signal clk. The first NMOS transistor 201 and the second NMOS transistor 202 both have a size W/L =1 μm/1 μm.
The latch circuit 30 includes: a fourth inverter 301 and a fifth inverter 302; the input end of the fourth inverter 301 is connected to the source of the first NMOS transistor 201 and the output end XP of the fifth inverter 302 at the same time; the input end of the fifth inverter 302 is connected to both the source of the second NMOS transistor 202 and the output end XN of the fourth inverter 301.
The current source differential switch simultaneous turn-off suppression circuit 40 is composed of four groups of same NMOS switch tubes and two same capacitors C.
Fig. 2 shows a specific circuit of the inverter in fig. 1, which includes: the NMOS switch tube and the PMOS switch tube are formed; the source electrode of the PMOS switching tube is connected with a power supply voltage VDD, and the grid electrode of the PMOS switching tube is connected with an INPUT signal INPUT of the phase inverter and is also connected with the grid electrode of the NMOS switching tube; the drain electrode of the PMOS switch tube is connected with the drain electrode of the NMOS switch tube and is an OUTPUT signal OUTPUT of the phase inverter; the source electrode of the NMOS switch tube is grounded GND. The size of the NMOS switching tube is W/L =1 μm/1 μm, and the size of the PMOS switching tube is W/L =2 μm/1 μm.
Fig. 3 shows an implementation of the current source differential switch simultaneous turn-off suppression circuit 40 in fig. 1; the current source differential switch simultaneous turn-off suppression circuit 40 is composed of four groups of the same NMOS switch tubes and two same capacitors C, and each group of NMOS switch tubes is composed of 3 parallel NMOS tubes.
The first group of NMOS switching tubes are formed by connecting a third NMOS switching tube M4001 to a fifth NMOS switching tube M4003 in parallel; the second group of NMOS switching tubes are formed by connecting a sixth NMOS switching tube M4004 to an eighth NMOS switching tube M4006 in parallel; the third group of NMOS switch is formed by connecting a ninth NMOS switch tube M4007 to an eleventh NMOS switch tube M4009 in parallel, and the fourth group of NMOS switch tubes is formed by connecting a twelfth NMOS switch tube M4010 to a fourteenth NMOS switch tube M4012 in parallel; the drains of the first NMOS switch tube M4001 to the eighth NMOS switch tube M4006 are all connected with a low power supply VDDL; the gates of the third NMOS switch tube M4001 to the fifth NMOS switch tube M4003 are connected to the output XN of the first inverter 301 in the latch circuit 30; the gates of the sixth NMOS switch tube M4004 through the eighth NMOS switch tube M4006 are connected to the output XP of the second inverter 302 in the latch circuit 30; sources of the ninth NMOS switch tube M4007 to the fourteenth NMOS switch tube M4012 are all grounded GND; the drains of the ninth NMOS switch tube M4007 through the eleventh NMOS switch tube M4009 are connected to serve as a current source differential switch driving signal Sa end; the drains of the twelfth NMOS switch tube M4010 to the fourteenth NMOS switch tube M4012 are connected and are the drive signal Sb end of the current source differential switch; the gates of the ninth NMOS switch tube M4007 to the eleventh NMOS switch tube M4009 are connected to the output XN of the first inverter 301 in the latch circuit 30, and the gates of the twelfth NMOS switch tube M4010 to the fourteenth NMOS switch tube M4012 are connected to the output XP of the second inverter 301 in the latch circuit 30. The size of the NMOS switching tube is W/L =1 μm/1 μm; VDDL =1/2vdd =1.65v.
One end of each capacitor C is respectively connected with the switch driving signal Sa or Sb, the other end of each capacitor C is grounded, and the capacitance value is 5pF.
As can be seen from fig. 4, the time for the current source differential switch to turn off simultaneously is small, about 0.03 μ s.
Because the slew rate of the current source differential switch simultaneous turn-off suppression circuit 40 is large, clock feedthrough, output glitch, and simultaneous turn-off time of the current source differential switch can be reduced at the same time.
Claims (6)
1. A switch driver circuit for an R-2R resistor network type digital-to-analog converter, comprising: a complementary differential signal generation circuit (10), a synchronization circuit (20), a latch circuit (30) and a current source differential switch simultaneous turn-off suppression circuit (40); the complementary differential signal generating circuit (10), the synchronizing circuit (20), the latch circuit (30) and the current source differential switch simultaneous turn-off suppression circuit (40) are sequentially cascaded; the current source differential switch simultaneous turn-off suppression circuit (40) is composed of a plurality of groups of same NMOS switch tubes and a plurality of same capacitors C.
2. A switch driver circuit for a digital-to-analog converter of the R-2R resistive network type according to claim 1, characterized in that said complementary differential signal generating circuit (10) comprises: a first inverter (101), a second inverter (102), and a third inverter (103); the input ends of the first inverter (101) and the third inverter (103) are connected with an input signal (D) of the complementary differential signal generating circuit (10); the output end of the first inverter (101) is connected with the input end of the second inverter (102); an output (a) of the second inverter (102) and an output (B) of the third inverter (103) constitute a differential output signal of the complementary differential signal generating circuit (10).
3. A switch driver circuit for a digital-to-analog converter of the R-2R resistive network type according to claim 1, characterized in that said synchronization circuit (20) comprises: a first NMOS switch tube (201) and a second NMOS switch tube (202); the drains of the NMOS switch tube (201) and the second NMOS switch tube (202) are respectively connected with the output end (A) of the second inverter (102) and the output end (B) of the third inverter (103), and the gates of the first NMOS switch tube (201) and the second NMOS switch tube (202) are both connected with a clock signal clk.
4. A switch driver circuit for a digital-to-analog converter of the R-2R resistive network type according to claim 1, characterized in that said latch circuit (30) comprises: a fourth inverter (301) and a fifth inverter (302); the input end of the fourth inverter (301) is connected with the source electrode of the first NMOS switch tube (201) and the output end (XP) of the fifth inverter (302) at the same time; and the input end of the fifth inverter (302) is simultaneously connected with the source electrode of the second NMOS switch tube (202) and the output end (XN) of the fourth inverter (301).
5. The switch driving circuit for R-2R resistor network type digital-to-analog converter according to claim 1, wherein each group of NMOS switch transistors is composed of N parallel NMOS transistors; the grid electrode of the first group of NMOS switch tubes is connected with the output end XP of the fifth inverter (302); the drain electrodes of the NMOS switch tubes of the first group are connected with a low power supply Voltage (VDDL); the source of the first group of NMOS switching tubes is a first switching drive signal (S) a ) An output terminal of (a); the grid electrode of the second group of NMOS switch tubes is connected with the output end (XN) of the fourth inverter (301); the drain electrode of the NMOS switch tube of the second group is connected with a low power supply Voltage (VDDL); the source electrode of the second group of NMOS switch tubes is a second switch driving signal (S) b ) Is transported byOutputting; the grid electrode of the NMOS switch tube of the third group is connected with the output end (XN) of the fourth inverter (301); the source electrode of the NMOS switching tube of the third group is connected with the Ground (GND); the drain electrode of the NMOS switch tube in the third group is the first switch drive signal (S) a ) An output terminal of (a); the grid electrode of the NMOS switching tube in the fourth group is connected with the output end (XP) of the fifth phase inverter (302); the source electrode of the NMOS switch tube of the fourth group is connected with the Ground (GND); the drain electrode of the NMOS switching tube in the fourth group is a second switching drive signal (S) b ) An output terminal of (a); the first switch drive signal (S) a ) And a second switch drive signal (S) b ) The ends are respectively connected with a capacitor C in parallel.
6. A switch driver circuit for a digital-to-analog converter of the R-2R resistor network type according to claim 1, characterized in that said current source differential switch simultaneously turns off the supply of the suppression circuit (40) half as much as the supply of the complementary differential signal generation circuit (10).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211547676.3A CN115811309A (en) | 2022-12-05 | 2022-12-05 | Switch driving circuit for R-2R resistance network type digital-to-analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211547676.3A CN115811309A (en) | 2022-12-05 | 2022-12-05 | Switch driving circuit for R-2R resistance network type digital-to-analog converter |
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| Publication Number | Publication Date |
|---|---|
| CN115811309A true CN115811309A (en) | 2023-03-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211547676.3A Pending CN115811309A (en) | 2022-12-05 | 2022-12-05 | Switch driving circuit for R-2R resistance network type digital-to-analog converter |
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| Country | Link |
|---|---|
| CN (1) | CN115811309A (en) |
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- 2022-12-05 CN CN202211547676.3A patent/CN115811309A/en active Pending
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