CN115799310A - Groove type insulated gate bipolar transistor and preparation method thereof - Google Patents
Groove type insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- CN115799310A CN115799310A CN202211697847.0A CN202211697847A CN115799310A CN 115799310 A CN115799310 A CN 115799310A CN 202211697847 A CN202211697847 A CN 202211697847A CN 115799310 A CN115799310 A CN 115799310A
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Abstract
The invention provides a groove type insulated gate bipolar transistor and a preparation method thereof, wherein the groove type insulated gate bipolar transistor comprises an N-type silicon substrate, a first shielding gate, a second shielding gate, a control gate, an emitter, a front surface P-type well region, an N-type carrier storage layer and a highly-doped carrier storage layer; the N-type silicon substrate is provided with a groove, the front P-type well region, the N-type carrier storage layer and the emitting electrode are respectively positioned on two sides of the groove, the highly doped carrier storage layer is positioned on the left side, the emitting electrode is positioned above the front P-type well region, and the front P-type well region is positioned above the N-type carrier storage layer; the first shielding grid, the second shielding grid and the control grid are arranged in the groove, the first shielding grid and the control grid are arranged side by side, and the second shielding grid is positioned at the bottoms of the first shielding grid and the control grid; the first and second shielding grids are at the same potential as the emitter. The invention eliminates the influence of the collecting electrode on the trench gate, reduces the gate charge and improves the dynamic characteristic.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a groove type insulated gate bipolar transistor and a preparation method thereof.
Background
Insulated Gate Bipolar Transistors (IGBTs) are widely used in power electronic systems as the main switching devices, combine the high frequency characteristics of power MOSFETs with the low on-state voltage drop of BJTs, and have the characteristics of high input impedance and low switching losses. In recent years, trench type IGBTs have proven to be one of the most competitive IGBT devices due to their advantages in manufacturing, reliability, current handling capability, and the like. Compared with a planar IGBT, the groove type IGBT can greatly reduce Von. Due to the existence of the deep groove, the JFET effect can be eliminated, the channel density is increased, the carrier concentration near an interface is enhanced, and the on-resistance of a channel region is reduced.
Currently, various trench type IGBT structures and techniques have been proposed and studied to improve the performance thereof. However, the introduction of trenches also presents problems. First, the presence of the trench bottom causes the gate to drain coupling to be greater than that of a planar device, and therefore the trench device has a greater gate capacitance. With the continuous reduction of the characteristic size of the chip, the parasitic capacitance is gradually increased, the dynamic loss is continuously increased, and the application of the IGBT in the medium-high frequency field is limited. In addition, the trench also creates a strong electric field at the bottom, causing premature breakdown, which affects the stability of the device, and the carrier storage layer at the bottom of the trench also exacerbates this problem.
Disclosure of Invention
The invention aims to provide a trench type insulated gate bipolar transistor and a preparation method thereof, which can eliminate the influence of a collector on a trench gate, reduce gate charges and improve dynamic characteristics.
In order to achieve the above object, in a first aspect, the present invention provides a trench-type insulated gate bipolar transistor, including an N-type silicon substrate, a first shielding gate, a second shielding gate, a control gate, an emitter, a front P-type well region, an N-type carrier storage layer, and a highly doped carrier storage layer;
the N-type silicon substrate is provided with a groove, the front surface of the N-type silicon substrate is provided with a front surface P-type well region, an N-type carrier storage layer, a highly-doped carrier storage layer and an emitting electrode, the front surface P-type well region, the N-type carrier storage layer and the emitting electrode are respectively positioned on two sides of the groove, the highly-doped carrier storage layer is positioned on the left side of the groove, the emitting electrode is positioned above the front surface P-type well region, and the front surface P-type well region is positioned above the N-type carrier storage layer;
the first shielding grid, the second shielding grid and the control grid are arranged in the groove, the first shielding grid and the control grid are arranged side by side at intervals, and the second shielding grid is positioned at the bottoms of the first shielding grid and the control grid; wherein the first and second shielding grids are equal in potential to the emitter.
In some embodiments, the highly doped storage layer is disposed at one side of the trench and near the emitter, and the highly doped storage layer divides the front P-type well region at one side of the trench into an upper portion and a lower portion.
In some embodiments, the trench further includes a gate dielectric layer disposed therein, the gate dielectric layer separating the first shield gate, the second shield gate and the control gate.
In some embodiments, contact regions are further formed between the front P-type well region and the emitter, and the contact regions include a P + contact region and an N + contact region.
The groove type insulated gate bipolar transistor provided by the invention has the beneficial effects that: the first shielding grid and the second shielding grid on the left side and the bottom are set to be equal in potential with the emitter, so that the influence of the collector on the trench grid is eliminated, grid charges are reduced, and dynamic characteristics are improved. And a highly doped memory layer near the emitter on the left side is formed by ion implantation, the highly doped memory layer enhances the hole carrier storage effect near the emitter, reduces the voltage drop Von without affecting the breakdown characteristic of the device, and compared with the existing device, under the same Von, the Qg and the short-circuit duration of the invention are obviously improved, and the turn-off time (Toff) and the saturation current are both reduced.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a trench type insulated gate bipolar transistor, where the method is used to manufacture the above trench type insulated gate bipolar transistor, and the method includes:
injecting ions on an N-type silicon substrate to form an N-type carrier storage layer;
injecting ions above the N-type carrier storage layer to form a front P-type well region;
etching to form a first groove, and depositing a first oxidation layer in the first groove;
depositing a first polycrystalline silicon layer on the first oxide layer to form a second shielding grid;
etching the first polysilicon layer to form a second groove, and depositing a second oxide layer in the second groove;
forming a first shielding gate and a control gate which are bilaterally symmetrical in the second oxide layer;
forming a highly doped memory layer using high energy ion implantation;
doping is carried out on the front surface of the N-type silicon substrate and above the P-type well region to form a contact region, and an emitter is formed on the contact region;
and forming a back N-well region on the back of the N-type silicon substrate through N-type ion implantation, and then forming a back P-well region through P-type ion implantation, wherein the back P-well region is positioned at the bottom, and the back N-well region is positioned above the back P-well region.
In some embodiments, the forming a highly doped memory layer using high energy ion implantation comprises:
and injecting phosphorus into the P-type well region to form a highly doped storage layer, wherein the highly doped storage layer divides the front P-type well region positioned on one side of the groove into an upper part and a lower part.
In some embodiments, the forming of the first shielding gate and the control gate in the second oxide layer in bilateral symmetry includes:
etching a third groove which is symmetrical left and right on the second oxide layer;
filling a second polysilicon layer in the third groove to form a first shielding gate and a control gate; wherein the trenches include the first trench, the second trench, and the third trench.
The preparation method of the groove type insulated gate bipolar transistor has the advantages that: the first shielding grid and the second shielding grid on the left side and the bottom are set to be equal in potential with the emitter, so that the influence of the collector on the trench grid is eliminated, grid charges are reduced, and dynamic characteristics are improved. And on the left side, another highly doped storage layer close to the emitter is formed by ion implantation, the highly doped storage layer enhances the hole carrier storage effect near the emitter, reduces the voltage drop Von without influencing the breakdown characteristic of the device, and compared with the existing device, under the same Von, the Qg and the short circuit duration of the invention are obviously improved, and the turn-off time (Toff) and the saturation current are both reduced.
Drawings
FIG. 1 is a schematic structural diagram of a trench-type IGBT according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a trench-type igbt according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. As used herein, unless otherwise specified, "connected" may be directly connected or indirectly connected, i.e., through an intermediate.
In view of the problems in the prior art, an embodiment of the present invention provides a trench-type insulated gate bipolar transistor, which is shown in fig. 1 and includes an N-type silicon substrate, a first shielding gate 5, a second shielding gate 7, a control gate 6, an emitter 1, a front P-type well region 3, a contact region 2, an N-type carrier storage layer 8, and a highly doped carrier storage layer 4. A groove is formed in the N-type silicon substrate, and the bottom of the groove extends to an N-type drift region 9 on the N-type silicon substrate. The contact region 2, the front P-type well region 3, the N-type carrier storage layer 8, the highly doped carrier storage layer 4 and the emitter 1 are formed on the front surface of the N-type silicon substrate. The contact region 2 the positive P type trap district 3 the N type carrier storage layer 8 with the projecting electrode 1 is located respectively the both sides of slot, highly doped carrier storage layer 4 is in the left side of slot, just the contact region 2 with the projecting electrode 1 is located the top in positive P type trap district 3, positive P type trap district 3 is located the top of N type carrier storage layer 8. The first shielding grid 5, the second shielding grid 7 and the control grid 6 are arranged in the groove, a grid dielectric layer is filled in the groove, the first shielding grid 5, the second shielding grid 7 and the control grid 6 are separated by the grid dielectric layer, and the grid dielectric layer is an oxide formed in the groove. The first shielding gate 5 and the control gate 6 are arranged side by side at intervals, and the second shielding gate 7 is located at the bottom of the first shielding gate 5 and the control gate 6. It should be noted that the first shielding grid 5 and the second shielding grid 7 are at the same potential as the emitter 1.
In this embodiment, the first shield gate 5 and the second shield gate 7 on the left and bottom are set to be equal to the emitter 1, so as to eliminate the influence of the collector (the back P-well region 10 and the back N-well region 11 formed on the back of the N-type silicon substrate) on the trench gate, reduce the gate charge, and improve the dynamic characteristics. Wherein the doping concentration of the N-type drift region 9 is 5.9 × 10 13 cm -3 The highly doped storage layer 4 on the left has a doping concentration of 4 x 10 17 cm -3 The doping concentration of the N-type carrier storage region 8 is 1 x 10 17 cm -3 The doping concentration of the front P-type well region 3 is 3 multiplied by 10 16 cm -3 。
Optionally, the trench type igbt further includes a highly doped storage layer 4 formed by implanting phosphorus (P) ions, the highly doped storage layer 4 is formed on one side of the trench and near the emitter 1, and the highly doped storage layer 4 divides the front P-type well 3 region located on one side of the trench into an upper portion and a lower portion.
In this embodiment, the additional highly doped storage layer 4 is formed by implanting phosphorus during the formation of the emitter 1. The highly doped storage layer 4 is formed on the left side and is close to the emitter 1, the highly doped storage layer 4 enhances the hole carrier storage effect near the emitter 1, reduces the voltage drop Von without influencing the breakdown characteristic of the device, and compared with the existing device, under the same Von, the device Qg and the short circuit duration of the embodiment of the invention are remarkably improved, and the turn-off time (Toff) and the saturation current are reduced. And another blocking layer is formed by arranging the highly doped storage layer 4 to more effectively inhibit accumulation of hole carriers, so that the storage effect of the carriers can be improved, and the conduction loss is reduced.
In another embodiment of the disclosure, a method for manufacturing a trench-type igbt is provided, which is shown in fig. 2 and includes:
s201: and injecting ions on the N-type silicon substrate to form an N-type carrier storage layer.
In this step, an N-type silicon substrate is formed by an epitaxial technique, and then N-type ions, such as phosphorus (P) ions, are implanted in a depth of the N-type silicon substrate to form N-type carrier storage layers on the left and right sides. Wherein the doping concentration of the N-type carrier storage region is 1 × 10 17 cm -3 。
S202: and injecting ions above the N-type carrier storage layer to form a front P-type well region.
In this step, P-type ions, such as boron (B) ions, are implanted on the N-type silicon substrate so that a front-side P-type well region having a doping concentration of 3 × 10 is formed above the N-type carrier storage layer 16 cm -3 。
S203: and etching to form a first groove, and depositing a first oxidation layer in the first groove.
In this step, the first oxide layer covers the surface of the first trench and does not completely fill the first trench.
S204: and depositing a first polysilicon layer on the first oxide layer to form a second shielding grid.
In this step, the first polysilicon layer is deposited on the first oxide layer, the first polysilicon layer completely fills the first trench, and then the first polysilicon layer is etched back to form the second shield gate.
S205: and etching the first polysilicon layer to form a second groove, and depositing a second oxide layer in the second groove.
In this step, the first polysilicon layer forms a second trench in the etch back. A second oxide layer is then deposited within the second trench, the second oxide layer completely filling the second trench.
S206: and forming a first shielding gate and a control gate which are bilaterally symmetrical in the second oxide layer.
Specifically, in this step, a third trench is etched on the second oxide layer in a left-right symmetry manner, and then a second polysilicon layer is filled in the third trench, and then the second polysilicon layer is subjected to photolithography processing to form a first shielding gate and a control gate. It should be noted that the trenches in the above embodiments include the first trench, the second trench, and the third trench.
S207: a highly doped memory layer is formed using high energy ion implantation.
In the step, phosphorus (P) is injected into the P-type well region to form the high-doped storage layer, the high-doped storage layer divides the front P-type well region on one side of the groove into an upper part and a lower part, and the doping concentration of the high-doped storage layer is 4 multiplied by 10 17 cm -3 。
S208: and doping the front surface of the N-type silicon substrate and the upper part of the P-type well region to form a contact region, and forming an emitter on the contact region.
S209: and forming a back surface N well region on the back surface of the N-type silicon substrate through N-type ion implantation, and then forming a back surface P well region through P-type ion implantation, wherein the back surface P well region is positioned at the bottom, and the back surface N well region is positioned above the back surface P well region.
In this embodiment, the first shield gate and the second shield gate on the left side and the bottom side are set to be equal in potential to the emitter, so that the influence of the collector on the trench gate is eliminated, the gate charge is reduced, and the dynamic characteristics are improved. And on the left side, another highly doped storage layer close to the emitter is formed by ion implantation, the highly doped storage layer enhances the hole carrier storage effect near the emitter, reduces the voltage drop Von without influencing the breakdown characteristic of the device, and compared with the existing device, under the same Von, the Qg and the short circuit duration of the invention are obviously improved, and the turn-off time (Toff) and the saturation current are reduced.
The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered within the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. A trench-type insulated gate bipolar transistor is characterized by comprising an N-type silicon substrate, a first shielding gate, a second shielding gate, a control gate, an emitter, a front P-type well region, an N-type carrier storage layer and a highly-doped carrier storage layer;
the N-type silicon substrate is provided with a groove, the front surface of the N-type silicon substrate is provided with the front surface P-type well region, the N-type carrier storage layer, the highly doped carrier storage layer and the emitter, the front surface P-type well region, the N-type carrier storage layer and the emitter are respectively positioned on two sides of the groove, the highly doped carrier storage layer is positioned on the left side of the groove, the emitter is positioned above the front surface P-type well region, and the front surface P-type well is positioned above the N-type carrier storage layer;
the first shielding gate, the second shielding gate and the control gate are arranged in the trench, the first shielding gate and the control gate are arranged side by side at intervals, and the second shielding gate is positioned at the bottom of the first shielding gate and the bottom of the control gate; wherein the first and second shielding grids are equal in potential to the emitter.
2. The trench type insulated gate bipolar transistor of claim 1 wherein said highly doped storage layer is disposed on one side of said trench and adjacent to said emitter, and said highly doped storage layer divides said front side P-well region on one side of said trench into upper and lower portions.
3. The trench type insulated gate bipolar transistor of claim 1 further comprising a gate dielectric layer disposed within said trench, said gate dielectric layer separating said first shield gate, said second shield gate and said control gate.
4. The trench type insulated gate bipolar transistor of claim 1, wherein contact regions are further formed between said front P-type well region and said emitter, said contact regions comprising a P + contact region and an N + contact region.
5. A preparation method of a groove type insulated gate bipolar transistor, which is used for preparing the groove type insulated gate bipolar transistor in any one of claims 1 to 4, and comprises the following steps:
injecting ions on an N-type silicon substrate to form an N-type carrier storage layer;
injecting ions above the N-type carrier storage layer to form a front P-type well region;
etching to form a first groove, and depositing a first oxidation layer in the first groove;
depositing a first polycrystalline silicon layer on the first oxide layer to form a second shielding grid;
etching the first polysilicon layer to form a second groove, and depositing a second oxide layer in the second groove;
forming a first shielding gate and a control gate which are bilaterally symmetrical in the second oxide layer;
forming a highly doped memory layer using high energy ion implantation;
doping is carried out on the front surface of the N-type silicon substrate and above the P-type well region to form a contact region, and an emitter is formed on the contact region;
and forming a back N-well region on the back of the N-type silicon substrate through N-type ion implantation, and then forming a back P-well region through P-type ion implantation, wherein the back P-well region is positioned at the bottom, and the back N-well region is positioned above the back P-well region.
6. The method of claim 5, wherein the forming a highly doped storage layer using high energy ion implantation comprises:
and injecting phosphorus into the P-type well region to form a highly doped storage layer, wherein the highly doped storage layer divides the front P-type well region positioned on one side of the groove into an upper part and a lower part.
7. The method for preparing a semiconductor device according to claim 5, wherein the forming of the first shielding gate and the control gate in the second oxide layer in bilateral symmetry comprises:
etching a third groove which is symmetrical left and right on the second oxide layer;
filling a second polysilicon layer in the third groove to form a first shielding gate and a control gate; wherein the trenches include the first trench, the second trench, and the third trench.
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| CN202211697847.0A CN115799310A (en) | 2022-12-28 | 2022-12-28 | Groove type insulated gate bipolar transistor and preparation method thereof |
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| CN202211697847.0A CN115799310A (en) | 2022-12-28 | 2022-12-28 | Groove type insulated gate bipolar transistor and preparation method thereof |
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