CN115794705A - CHI bus memory for chip prototype rapid function verification - Google Patents

Abstract

The invention discloses a CHI bus memory for chip prototype rapid function verification, which comprises a link management module, a credit control module, a transaction processing module, a message cache module and an SRAM (static random access memory) module, wherein the message cache module is respectively connected with the link management module, the credit control module and the transaction processing module, the transaction processing module is connected with the SRAM module, and the link management module, the credit control module and the message cache module are respectively connected with a CHI bus interface.

Description

CHI bus memory for chip prototype rapid function verification

Technical Field

The invention belongs to the technical field of chip prototype rapid function verification in the technical field of computers, and particularly relates to a CHI bus memory for chip prototype rapid function verification.

Background

High performance multi-core processors or SoC chips usually contain DDR (Double data rate) Memory controllers that are connected to real-Memory DIMMs (Dual-Inline-Memory-Modules) through physical interfaces. The DDR initialization process is time-consuming and complex, and read-write memory access can be performed only after initialization is normal through power-on and initialization configuration, ZQ calibration, DQ calibration and PHY link training. The initialization configuration comprises more than 20 steps, and mainly relates to the configuration of the model, the memory capacity, the time sequence parameters and the mode register of the DDR controller memory, and a large amount of simulation verification time is consumed in the configuration process.

When the system level verification of the full chip is carried out, if the relevant functions of the memory controller are not verified, the details in the functions do not need to be paid attention to, otherwise, a large amount of verification resources are occupied and the verification efficiency is influenced. In order to solve the problems, a chip prototype needs to be quickly built to carry out functional verification, and the chip memory controller can be directly replaced by a memory model with a CHI bus by quickly positioning design defects through test excitation loosely coupled with the memory controller. The CHI bus is a fifth generation bus specification defined by ARM corporation, and provides an extensible on-chip interconnection specification, and the memory belongs to an SN (Slave Node) of the CHI bus and accepts a read-write request sent by an HN (Home Node). The CHI protocol is an evolved version of an ACE (AXI conformance protocol extension) protocol, the ACE protocol is compatible with the AXI protocol, signal level communication in a master/slave mode is used, the ACE protocol is generally applied to chips in the mobile and embedded fields, a CC conformance protocol system with a small system scale is supported, and a Snoop broadcast bus mode is supported. With more and more coherent Clusters integrated on SOC, AMBA5 introduced the CHI protocol. The CHI Protocol uses a layered packet communication Protocol, which includes a Protocol layer (Protocol), a Network layer (Network) and a Link layer (Link), supports flow control based on QoS, supports a retry mechanism, and supports a directory implementation manner and a Snoop broadcast bus manner of a CC consistency Protocol. The storage function model of the AXI/ACE bus is relatively simple to implement, but a CHI conversion AXI/ACE protocol bridge needs to be designed, more design circuits need to be additionally arranged, and the resource overhead is increased.

Disclosure of Invention

The technical problems to be solved by the invention are as follows: aiming at the design of a high-performance multi-core processor or a complex SoC (System on Chip) integrated with a standard CHI bus memory, the invention provides the CHI bus memory for Chip prototype rapid function verification, which can be used for replacing real memory controllers of complex protocols such as DDR, HBM and the like in the high-performance multi-core processor or SoC Chip and efficiently building a Chip rapid prototype System to meet the rapid verification requirement of a Chip prototype.

In order to solve the technical problems, the invention adopts the technical scheme that:

a CHI bus memory for fast functional verification of chip prototypes, comprising:

the link management module is used for managing the link state of the CHI bus;

the credit control module is used for managing the credit of each channel of the CHI bus memory;

the transaction processing module comprises a read transaction state machine and a write transaction state machine, wherein the read transaction state machine is used for processing the CHI bus request message, and the write transaction state machine is used for processing the CHI bus write request message;

the message caching module is used for caching the CHI message to provide data support for the transaction processing module;

the SRAM module is used for storing data of the CHI message;

the message cache module is respectively connected with the link management module, the credit control module and the transaction processing module, the transaction processing module is connected with the SRAM module, and the link management module, the credit control module and the message cache module are respectively connected with the CHI bus interface.

Optionally, the link management module managing the link state of the CHI bus comprises: pulling up an activation response signal of the link after receiving a link activation request of a HN main node of the CHI bus, so that the link enters a normal working state; and after receiving a link pulling-down request signal of the HN main node, pulling down an activation response signal of the link, so that the link enters an IDLE state IDLE.

Optionally, the message buffer module includes four first-in first-out buffers, namely a receive request message buffer RX _ ReqFlitFifo, a receive data message buffer RX _ datfiitfifo, a transmit data message buffer TX _ datfiitfifo, and a transmit response message buffer TX _ rspfiitfifo, and when the link is in a working state and the credit is valid, the CHI bus memory receives the CHI request message and the CHI receive data message from the CHI bus and respectively inputs the CHI request message buffer RX _ ReqFlitFifo or the receive data message buffer RX _ datfiitfififo in the message buffer module; the CHI response message and the CHI data message generated by the transaction processing module are respectively input into a sending data message buffer TX _ DatFlitFifo or a sending response message buffer TX _ RspFlitFifo in the message buffer module, when the sending data message buffer TX _ DatFlitFifo and the sending response message buffer TX _ RspFlitFifo are not empty, the CHI message buffer module judges that a link is in a normal working state, and if the credit of a sending response channel TX _ RspLink and a sending data channel TX _ DatLink calculated by the credit control module is greater than 0, the CHI message buffer module sends the messages buffered in the sending data message buffer TX _ DatFlitFifo and the sending response message buffer TX _ RspFlitFifo to a CHI bus.

Optionally, each channel of the CHI bus memory managed by the credit control module includes four channels, namely, an accept request channel RX _ ReqLink, an accept data channel RX _ DatLink, a transmit response channel TX _ rspslink, and a transmit data channel TX _ DatLink, and the credit control module further includes credit counters corresponding to the four channels respectively to manage credits of each channel; the initialization values of the credit counters of the transmission response channel TX _ RspLink and the transmission data channel TX _ DatLink are both 0, when a credit control signal TX _ RspLink _ Lgrid of the CHI bus is sampled, the credit counter of the transmission response channel TX _ RspLink is increased by 1, and when a transmission response message buffer TX _ RspFlitFifo of the CHI message buffer module transmits a message to the CHI bus, the credit counter of the transmission response channel TX _ RspLink is decreased by 1; when a credit control signal TX _ DatLink _ Lrd of the CHI bus is sampled, adding 1 to a credit counter of a sending data channel TX _ DatLink, and when a sending data message buffer TX _ DatFlitFifo of the CHI message buffer module sends a message to the CHI bus, subtracting 1 from the credit counter of the sending data channel TX _ DatLink; the initialization values of credit counters of an acceptance request channel RX _ ReqLink and an acceptance data channel RX _ DatLink are all equal to the buffer depth of a receiving request message buffer RX _ ReqFlitFifo in a CHI message buffer module, when a link enters a normal working state after activation response, a credit control module sends a credit control signal RX _ ReqLink _ Lcrd to a CHI bus, and the credit counter of the acceptance request channel RX _ ReqLink is reduced by 1; when the link works normally, the credit control module receives a request message processing completion signal sent by the transaction processing module, the credit counter of the receiving request channel RX _ ReqLink is added with 1, and the credit control module sends a credit control signal RX _ ReqLink _ Lrd to the CHI bus; when the link activation data is sent and then enters a normal working state, the credit control module sends a credit control signal RX _ DatLink _ Lrd to the CHI bus, and a credit counter receiving a data channel RX _ DatLink is subtracted by 1; when the link works normally, the credit control module receives a request message processing completion signal sent by the transaction processing module, the credit counter of the data channel RX _ DatLink is added with 1, and the credit control module sends a credit control signal RX _ DatLink _ Lrd to the CHI bus.

Optionally, the read transaction state machine of the transaction processing module has four states, namely, RD _ IDLE state, RD _ SRAM state, CREATE _ txdatafault state, and OUTPUT _ txdatafault state, where RD _ IDLE state is an IDLE state, RD _ SRAM state is a read SRAM state, CREATE _ txdatafault state is a state of generating a CHI transmit data packet, and OUTPUT _ txdatafault state is a transmit data packet buffer TX _ datfitfifo that inputs the CHI transmit data packet into the CHI packet buffer module.

Optionally, the state control process of the read transaction state machine includes: the read transaction state machine defaults to be in the RD _ IDLE state; if the transaction processing module detects that the receiving request message cache RX _ ReqFlitFifo in the CHI message cache module is not empty in the RD _ IDLE state, reading the receiving request message cache RX _ ReqFlitFifo, decoding the read message into reading operation, and switching to the RD _ SRAM state; in the RD _ SRAM state, analyzing and recording the relevant domain segment of the read request message, assigning a read counter to zero, recording the initial address of a read command and the length of a read data byte, sending the read command and the read address to an SRAM module, and switching to a CREATE _ TXDATFLIT state; generating a CHI sending data message under a CREATE _ TXDATFLIT state, and then switching to an OUTPUT _ TXDATFO state; inputting a CHI sending data message into a sending data message buffer TX _ DatFlitFifo in a CHI message buffer module under an OUTPUT _ TXDATIFO state; then accumulating the count value of the reading counter to the byte length of the read SRAM data, if the reading counter is equal to the byte length of the read data recorded in the RD _ SRAM state, judging that the reading transaction is finished, and switching to the RD _ IDLE state; otherwise, the state of CREATE _ TXDATFLIT is transferred.

Optionally, the write transaction state machine of the transaction processing module has four states: WR _ IDLE state, CREATE _ txrespfet state, WAIT _ RXDATA state, WAIT _ SRAM state, where WR _ IDLE state is IDLE state, CREATE _ txrespfet state is generating sending response message, WAIT _ RXDATA state is waiting for the receiving data message buffer RX _ datfiltfifo of the message buffer module not to be empty, WAIT _ SRAM state is inputting SRAM write control signal, write address, write data state.

Optionally, the state control process of the write transaction state machine includes: the write transaction state machine defaults to the WR _ IDLE state; if the transaction processing module detects that the receiving request message cache RX _ ReqFlitFifo in the CHI message cache module is not empty in the WR _ IDLE state, reading the receiving request message cache RX _ ReqFlitFifo, decoding the message into write operation, and switching to a CREATE _ TXRESPFLIT state; recording relevant field segments of a write request message in a CREATE _ TXRESPFLITE state, filling each field segment of a response message to be sent, generating a response message to be sent, outputting the response message to a response message sending buffer TX _ RspFlitFifo, recording an address of the write request message and a byte length of write data, setting an initialization value of a count value of a write counter to be 0, and switching to a WAIT _ RXDATA state; in the WAIT _ RXDATA state, waiting for the receiving data message cache RX _ DatFlitFifo of the CHI message cache module to be not empty, reading the receiving data message cache RX _ DatFlitFifo, resolving corresponding data according to the read receiving data message, obtaining write SRAM data, returning to the credit control module to complete a receiving data transaction, and switching to the WAIT _ SRAM state; in the WAIT _ SRAM state, outputting a write control signal, a write address and write data of the SRAM module, wherein the write address is equal to the address of a write request message recorded in a CREATE _ TXRESPFLIT state, the write data is equal to the write SRAM data obtained in the WAIT _ RXDATA state, the count value of a write counter accumulates the byte length of the output data in the SRAM module, if the write counter is equal to the write data byte length recorded in the CREATE _ TXRESPFLIT state, the write transaction is completed, a request transaction completion signal is sent to a credit control module, and the state is shifted to a WR _ IDLE state, otherwise, the state is shifted to the WAIT _ RXDATA state.

In addition, the invention also provides a chip prototype rapid function verification system, which comprises a verification device and a verified chip prototype with a storage module, wherein the storage module is the CHI bus memory for the chip prototype rapid function verification.

Optionally, the verified chip prototype with the memory module is written in an FPGA chip.

Compared with the prior art, the invention mainly has the following advantages:

1. the CHI bus memory for chip prototype rapid functional verification comprises a link management module, a credit control module, a transaction processing module, a message cache module and an SRAM module, wherein the message cache module is respectively connected with the link management module, the credit control module and the transaction processing module, the transaction processing module is connected with the SRAM module, and the link management module, the credit control module and the message cache module are respectively connected with a CHI bus interface.

2. Compared with a storage function model based on a CHI conversion AXI/ACE protocol bridge, the CHI bus memory for chip prototype rapid function verification optimizes the resources of circuit design, simplifies the circuit structure, and improves the verification resources and the verification efficiency. Meanwhile, in the whole chip verification process, the DDR controller function test is eliminated, the verification of the whole functions of the chip is facilitated, the full chip verification process is easier to deploy in a simulator and an FPGA prototype system to realize, and the full chip verification process is also suitable for the design of an SRAM memory of an SOC chip adopting a CHI bus.

Drawings

FIG. 1 is a diagram of a CHI bus memory according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating state switching of a read transaction state machine according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating state switching of a write transaction state machine according to an embodiment of the present invention.

Illustration of the drawings: 1. a link management module; 2. a credit control module; 3. a transaction processing module; 4. a message caching module; 5. an SRAM module.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

As shown in fig. 1, the CHI bus memory for chip prototype fast function verification of the present embodiment includes:

a link management module 1, configured to manage a link state of the CHI bus;

a credit control module 2, which is used for managing the credit of each channel of the CHI bus memory;

the transaction processing module 3 comprises a read transaction state machine and a write transaction state machine, wherein the read transaction state machine is used for processing a CHI bus request message, and the write transaction state machine is used for processing a CHI bus write request message;

the message caching module 4 is used for caching the CHI message to provide data support for the transaction processing module 3;

the SRAM module 5 is used for storing data of the CHI message;

the message cache module 4 is respectively connected with the link management module 1, the credit control module 2 and the transaction processing module 3, the transaction processing module 3 is connected with the SRAM module 5, and the link management module 1, the credit control module 2 and the message cache module 4 are respectively connected with the CHI bus interface.

The link management module 1 is configured to complete link management of the CHI bus and ensure that the CHI bus is in a reasonable working state, where in this embodiment, the link management module 1 manages the link state of the CHI bus and includes: pulling up an activation response signal of the link after receiving a link activation request of a HN main node of the CHI bus, so that the link enters a normal working state; and after receiving a link pulling-down request signal of the HN main node, pulling down an activation response signal of the link, so that the link enters an IDLE state IDLE.

In this embodiment, the message cache module 4 includes four first-in first-out caches, namely a receive request message cache RX _ ReqFlitFifo, a receive data message cache RX _ datfiitfifo, a send data message cache TX _ datfiitfifo, and a send response message cache TX _ rspfiitfifo, and when the link is in a working state and the credit is valid, the CHI bus memory receives the CHI request message and the CHI receive data message from the CHI bus and respectively inputs the CHI request message cache RX _ ReqFlitFifo or the receive data message cache RX _ datfiitfififo in the message cache module 4; the CHI response message and the CHI data message generated by the transaction module 3 are respectively input to the transmission data message buffer TX _ datfiltfifo or the transmission response message buffer TX _ rspfiltfifo in the message buffer module 4, when the transmission data message buffer TX _ datfiltfifo and the transmission response message buffer TX _ rspfiltfifo are not empty, the CHI message buffer module 4 determines that the link is in a normal working state, and if the credit of the transmission response channel TX _ rspelk and the transmission data channel TX _ datfiltlink calculated by the credit control module 2 is greater than 0 at this time, the CHI message buffer module 4 transmits the messages buffered in the transmission data message buffer TX _ datfiltfifo and the transmission response message buffer TX _ rspfiltfifo to the CHI bus.

As shown in fig. 1, each channel of the CHI bus memory managed by the credit control module 2 in this embodiment includes four channels, namely, an acceptance request channel RX _ ReqLink, an acceptance data channel RX _ DatLink, a transmission response channel TX _ rspslink, and a transmission data channel TX _ DatLink, each channel has an independent credit control signal Lcrd, a credit value is equal to the number of buffers capable of transmitting a packet in the transmission channel, which is determined by a packet buffer depth of the acceptance channel, credit control of the acceptance channel is realized by the credit control signal Lcrd, and an adopted pulse signal is transmitted to the other party. A CHI packet is composed of one or more micro packets (flits), for example, a request packet and a response packet are realized by one micro packet, a data packet is realized by 1 or 2 micro packets, the data packet has a carried length field segment, the carried data is unequal from 1 byte to 16 bytes, one micro packet carries maximum data 256 bit data, 2 micro packets carry maximum 512 bit data, the width of the packet buffer module 4 is the width of one micro packet, and the credit expression value is the micro packet number expressing the bufferable packet, that is, when the micro packet number in the packet is 1 or 2, the credit control module 2 can send out 1 or 2 credit control pulse signals Lcrd.

In this embodiment, the credit control module 2 further includes credit counters corresponding to the four channels respectively to manage credits of the channels; the initialization values of the credit counters of the transmission response channel TX _ rsplnk and the transmission data channel TX _ datlnk are both 0, when a credit control signal TX _ rsplnk _ Lcrd of the CHI bus is sampled, the credit counter of the transmission response channel TX _ rsplnk is incremented by 1, and when a transmission response packet buffer TX _ rspfittfifo of the CHI packet buffer module 4 transmits a packet to the CHI bus, the credit counter of the transmission response channel TX _ rsplnk is decremented by 1; when a credit control signal TX _ DatLink _ Lrd of the CHI bus is sampled, adding 1 to a credit counter of a sending data channel TX _ DatLink, and when a sending data message cache TX _ DatFlitFifo of the CHI message cache module 4 sends a message to the CHI bus, subtracting 1 from the credit counter of the sending data channel TX _ DatLink; the initialization values of the credit counters of the receiving request channel RX _ ReqLink and the receiving data channel RX _ DatLink are all equal to the buffer depth of the receiving request message buffer RX _ ReqFlitFifo in the CHI message buffer module 4, when the link enters a normal working state after activation response, the credit control module 2 sends a credit control signal RX _ ReqLink _ Lcd to the CHI bus, and the credit counter of the receiving request channel RX _ ReqLink is reduced by 1; when the link works normally, when the credit control module 2 receives a request message processing completion signal sent by the transaction processing module 3, the credit counter of the receiving request channel RX _ ReqLink is added with 1, and the credit control module 2 sends a credit control signal RX _ ReqLink _ Lcrd to the CHI bus; when the link enters a normal working state after the link activation data is sent, the credit control module 2 sends a credit control signal RX _ DatLink _ Lrd to the CHI bus, and the credit counter of the receiving data channel RX _ DatLink is reduced by 1; when the link works normally, the credit control module 2 receives a request message processing completion signal sent by the transaction module 3, adds 1 to the credit counter of the data channel RX _ datalink, and the credit control module 2 sends a credit control signal RX _ datalink _ Lcrd to the CHI bus.

The transaction processing module 3 comprises a read transaction state machine and a write transaction state machine, when the RX _ ReqFlitFifo received request message buffer in the CHI message buffer module 4 is not empty, the transaction processing module 3 reads RX _ ReqFlitFifo and decodes the read request message to obtain a read/write operation command, so as to start the read/write transaction state machine.

The read transaction state machine is used for processing the CHI bus request message, analyzing and recording a read command and an address, sending a read signal and a read address bus to the SRAM, acquiring read data from the SRAM, generating a CHI sending data message, outputting the CHI sending data message to TX _ DatFlitFifo in the CHI message cache module 4, requesting the completion of a transaction, and sending a transaction completion signal to inform the credit control module 2. Referring to fig. 2, the read transaction state machine of the transaction processing module 3 in this embodiment has four states, namely, RD _ IDLE state, RD _ SRAM state, CREATE _ txdatafault state, and OUTPUT _ txdatafault state, where RD _ IDLE state is an IDLE state, RD _ SRAM state is a read SRAM state, CREATE _ txdatafault state is a state of generating a CHI transmit data packet, and OUTPUT _ txdatafault state is a transmit data packet buffer TX _ datafltfifo for inputting a CHI transmit data packet into the CHI packet buffer module 4. As shown in fig. 2, the state control process of the read transaction state machine includes:

the read transaction state machine defaults to the RD _ IDLE state;

if the transaction processing module 3 detects that the receiving request message buffer RX _ ReqFlitFifo in the CHI message buffer module 4 is not empty in the RD _ IDLE state, reading the receiving request message buffer RX _ ReqFlitFifo, decoding the read message into a read operation, and switching to the RD _ SRAM state;

in the RD _ SRAM state, analyzing and recording the relevant field segment of the read request message, assigning a read counter to zero, recording the initial address of the read command and the length of the read data byte, sending the read command and the read address to the SRAM module 5, and switching to the CREATE _ txdatalit state;

generating a CHI sending data message under the CREATE _ TXDATFLIT state, and then switching to the OUTPUT _ TXDATFO state;

inputting a CHI sending data message into a sending data message buffer TX _ DatFlitFifo in a CHI message buffer module 4 under an OUTPUT _ TXDATIFO state; then accumulating the count value of the reading counter to the byte length of the read SRAM data, if the reading counter is equal to the byte length of the read data recorded in the RD _ SRAM state, judging that the reading transaction is finished, and switching to the RD _ IDLE state; otherwise, the CREATE _ TXDATFLIT state is entered.

In this embodiment, generating the CHI transmit data packet with the CREATE _ txdatalit state is to fill the read data output by the SRAM into the data field of the CHI transmit data packet, fill the request packet related field recorded by the RD _ SRAM state into the corresponding field, generate 1-bit CRC check bit for 8-bit data, fill the data check field of the transmit data packet, obtain the CHI transmit data packet after filling, and output the CHI transmit data packet to the TX _ datfiltfifo in the CHI packet buffer module 4.

The write transaction state machine is used for processing a CHI bus write request message, analyzing and recording a write command and an address, generating a CHI response message and outputting the CHI response message to a received data message buffer RX _ DatFlitFifo in the message buffer module 4; when the received data message buffer RX _ datfiitfifo of the message buffer module 4 is not empty, reading out the received data message of the received data message buffer RX _ datfiitfifo, analyzing the written data, inputting a SRAM write signal, a write address bus, and a write data bus; and sending a transaction completion signal to the credit control module 2 after the write transaction is completed. Referring to fig. 3, the write transaction state machine of the transaction processing module 3 has four states: WR _ IDLE state, CREATE _ txrespfault state, WAIT _ RXDATA state, and WAIT _ SRAM state, where the WR _ IDLE state is an IDLE state, the CREATE _ txrespfault state is a state where a transmission response message is generated, the WAIT _ RXDATA state is a state where the reception data message buffer RX _ datfiltfifo of the WAIT message buffer module 4 is not empty, and the WAIT _ SRAM state is a state where an SRAM write control signal, a write address, and write data are input.

As shown in fig. 2, the state control process of the write transaction state machine includes:

the write transaction state machine defaults to the WR _ IDLE state;

if the transaction processing module 3 detects that the receiving request message buffer RX _ ReqFlitFifo in the CHI message buffer module 4 is not empty in the WR _ IDLE state, reading the receiving request message buffer RX _ ReqFlitFifo, decoding the message into writing operation, and switching to a CREATE _ TXRESPFLIT state;

recording relevant domain sections of a write request message in a CREATE _ TXRESPFLIT state, filling each domain section of a response message to be sent, generating a response message to be sent, outputting the response message to a response message sending buffer TX _ RspFlitFifo, recording the address of the write request message and the byte length of write data, setting the count value initialization value of a write counter to be 0, and switching to a WAIT _ RXDATA state;

in the WAIT _ RXDATA state, waiting for the receiving data message cache RX _ DatFlitFifo of the CHI message cache module 4 to be not empty, reading the receiving data message cache RX _ DatFlitFifo, resolving corresponding data according to the read receiving data message, obtaining write SRAM data, and returning a receiving data transaction completion signal to the credit control module 2 to be switched to the WAIT _ SRAM state;

in the WAIT _ SRAM state, a write control signal, a write address and write data of the SRAM module 5 are output, the write address is equal to an address of a write request message recorded in the CREATE _ txrespfel state, the write data is equal to write SRAM data obtained in the WAIT _ RXDATA state, a count value of a write counter accumulates a byte length of the output data in the SRAM module 5, if the write counter is equal to the write data byte length recorded in the CREATE _ txrespfel state, the write transaction is completed, a request transaction completion signal is returned to the credit control module 2, and the state is switched to the WR _ IDLE state, otherwise, the state is switched to the WAIT _ RXDATA state.

To sum up, the CHI bus memory for verifying the rapid function of the chip prototype of the embodiment includes a link management module 1, a credit control module 2, a transaction processing module 3, a packet buffer module 4, and an SRAM module 5, where the link management module 1 is configured to process a CHI bus link state; the credit control module 2 maintains the credit of the four channels of the CHI bus, namely credit management of an acceptance request channel RX _ ReqLink, an acceptance data channel RX _ DatLink, a sending response channel TX _ RspLink and a sending data channel TX _ DatLink; the transaction processing module 3 comprises a read transaction state machine and a write transaction state machine, and is used for processing read and write messages of the CHI bus, analyzing commands, addresses and data, interacting the data with the SRAM, generating a data message according with the CHI protocol, outputting the data message to the message buffer module 4, and finally sending the data message to the CHI bus; the message buffer module 4 is configured to buffer the CHI bus message and provide data support for the transaction module 3. Aiming at the design of a high-performance multi-core processor or a System on Chip (SoC) integrated with a standard CHI bus memory, the CHI bus memory for Chip prototype rapid function verification of the embodiment can realize the standard CHI bus memory, is used for building a Chip rapid prototype System, meets the rapid verification requirement, can replace a real storage controller of complex protocols such as DDR, HBM and the like in the high-performance multi-core processor or the SoC Chip, simulates and accelerates the related test of a non-storage controller, and is suitable for a simulation acceleration platform and an FPGA platform.

In addition, the embodiment further provides a chip prototype rapid function verification system, which includes a verification apparatus and a verified chip prototype with a memory module, where the memory module is the CHI bus memory used in the chip prototype rapid function verification. As an optional implementation manner, the chip prototype with the memory module verified in this embodiment is written in the FPGA chip, and may also be written in other types of programmable chips to implement fast functional verification on the chip prototype.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims (10)

1. A CHI bus memory for chip prototype fast functional verification, comprising:

the link management module (1) is used for managing the link state of the CHI bus;

the credit control module (2) is used for managing the credit of each channel of the CHI bus memory;

the transaction processing module (3) comprises a read transaction state machine and a write transaction state machine, wherein the read transaction state machine is used for processing the CHI bus request message, and the write transaction state machine is used for processing the CHI bus write request message;

the message caching module (4) is used for caching the CHI message to provide data support for the transaction processing module (3);

and an SRAM module (5) for storing data of the CHI message;

the message caching module (4) is respectively connected with the link management module (1), the credit control module (2) and the transaction processing module (3), the transaction processing module (3) is connected with the SRAM module (5), and the link management module (1), the credit control module (2) and the message caching module (4) are respectively connected with the CHI bus interface.

2. The CHI bus memory for chip prototype fast function verification as claimed in claim 1, wherein the link management module (1) managing the link state of the CHI bus comprises: pulling up an activation response signal of the link after receiving a link activation request of a HN main node of the CHI bus, so that the link enters a normal working state; and after receiving a link pulling-down request signal of the HN main node, pulling down an activation response signal of the link, so that the link enters an IDLE state IDLE.

3. The CHI bus memory for chip prototype fast function verification according to claim 2, wherein the message buffer module (4) comprises four first-in first-out buffers of a receive request message buffer RX _ ReqFlitFifo, a receive data message buffer RX _ datfiitfifo, a transmit data message buffer TX _ datfiitfifo and a transmit response message buffer TX _ rspfiitfifo, and when the link is in an active state and the credit is valid, the CHI bus memory receives the CHI request message and the CHI receive data message from the CHI bus and inputs the CHI request message buffer RX _ ReqFlitFifo or the receive data message buffer RX _ datfiitfifo in the message buffer module (4); the CHI response message and the CHI data message generated by the transaction processing module (3) are respectively input into a sending data message buffer TX _ DatFlitFifo or a sending response message buffer TX _ RspFlitFifo in the message buffer module (4), when the sending data message buffer TX _ DatFlitFifo and the sending response message buffer TX _ RspFlitFifo are not empty, the CHI message buffer module (4) judges that a link is in a normal working state, and when the credit of a sending response channel TX _ RspLink and a sending data channel TX _ DatLink calculated by the credit control module (2) is more than 0, the CHI message buffer module (4) sends the messages buffered in the sending data message buffer TX _ DatFlitFifo and the sending response message buffer TX _ RspFlitFifo to a CHI bus.

4. The CHI bus memory for chip prototype fast function verification as claimed in claim 3, wherein the credit control module (2) manages the CHI bus memory with four channels including an accept request channel RX _ ReqLink, an accept data channel RX _ DatLink, a transmit response channel TX _ rspslink and a transmit data channel TX _ DatLink, and the credit control module (2) further includes credit counters corresponding to the four channels to manage credits of the channels; the initialization values of credit counters of the transmission response channel TX _ RspLink and the transmission data channel TX _ DatLink are both 0, when a credit control signal TX _ RspLink _ Lcrd of a CHI bus is sampled, the credit counter of the transmission response channel TX _ RspLink is added with 1, and when a transmission response message cache TX _ RspFlitFifo of the CHI message cache module (4) transmits a message to the CHI bus, the credit counter of the transmission response channel TX _ RspLink is subtracted with 1; when a credit control signal TX _ DatLink _ Lrd of a CHI bus is sampled, adding 1 to a credit counter of a sending data channel TX _ DatLink, and subtracting 1 from the credit counter of the sending data channel TX _ DatLink when a sending data message buffer TX _ DatFlitFifo of a CHI message buffer module (4) sends a message to the CHI bus; the initialization values of credit counters of an acceptance request channel RX _ ReqLink and an acceptance data channel RX _ DatLink are equal to the buffer depth of a reception request message buffer RX _ ReqFlitFifo in a CHI message buffer module (4), when a link enters a normal working state after activation response, a credit control module (2) sends a credit control signal RX _ ReqLink _ Lcrd to a CHI bus, and the credit counter of the acceptance request channel RX _ ReqLink is reduced by 1; when the link works normally, the credit control module (2) receives a request message processing completion signal sent by the transaction processing module (3), the credit counter of the request channel RX _ ReqLink is added with 1, and the credit control module (2) sends a credit control signal RX _ ReqLink _ Lgrid to the CHI bus; when the link activation data is sent and then enters a normal working state, the credit control module (2) sends a credit control signal RX _ DatLink _ Lrd to the CHI bus, and a credit counter of the receiving data channel RX _ DatLink is reduced by 1; when the link works normally, the credit control module (2) receives the request message processing completion signal sent by the transaction processing module (3), the credit counter of the data channel RX _ DatLink is added with 1, and the credit control module (2) sends a credit control signal RX _ DatLink _ Lgrid to the CHI bus.

5. The CHI bus memory for chip prototype fast function verification as claimed in claim 4, wherein the read transaction state machine of the transaction processing module (3) has four states, RD _ IDLE state, RD _ SRAM state, CREATE _ TXDATFLLIT state and OUTPUT _ TXDATIFO state, wherein RD _ IDLE state is IDLE state, RD _ SRAM state is read SRAM state, CREATE _ TXDATFLIT state is generate CHI send data message state, OUTPUT _ TXDATIFO state is send data message buffer TX _ DatFlitFin for inputting the send CHI send data message into the CHI message buffer module (4).

6. The CHI bus memory for chip prototype fast function verification as claimed in claim 5, wherein the state control process of the read transaction state machine comprises: the read transaction state machine defaults to be in the RD _ IDLE state; if the transaction processing module (3) detects that the receiving request message cache RX _ ReqFlitFifo in the CHI message cache module (4) is not empty in the RD _ IDLE state, reading the receiving request message cache RX _ ReqFlitFifo, decoding the read message into a read operation, and switching to the RD _ SRAM state; in the RD _ SRAM state, analyzing and recording relevant field segments of the read request message, assigning a read counter to be zero, recording an initial address of a read command and the length of a read data byte, sending the read command and the read address to an SRAM module (5), and switching to a CREATE _ TXDATFLIT state; generating a CHI sending data message under the CREATE _ TXDATFLIT state, and then switching to the OUTPUT _ TXDATFO state; inputting a transmission CHI transmission data message into a transmission data message buffer TX _ DatFlitFifo in a CHI message buffer module (4) in an OUTPUT _ TXDATIFO state; then accumulating the count value of the reading counter to the byte length of the read SRAM data, if the reading counter is equal to the byte length of the read data recorded in the RD _ SRAM state, judging that the reading transaction is finished, and switching to the RD _ IDLE state; otherwise, the state of CREATE _ TXDATFLIT is transferred.

7. The CHI bus memory for chip prototype fast function verification according to claim 6, wherein the write transaction state machine of the transaction module (3) has four states in total: a WR _ IDLE state, a CREATE _ TXRESPFLIT state, a WAIT _ RXDATA state and a WAIT _ SRAM state, wherein the WR _ IDLE state is an IDLE state, the CREATE _ TXRESPFLIT state is used for generating a sending response message, the WAIT _ RXDATA state is used for waiting for a receiving data message buffer RX _ DatFlitFifo of the message buffer module (4) to be empty, and the WAIT _ SRAM state is used for inputting SRAM writing control signals, writing addresses and writing data.

8. The CHI bus memory for chip prototype fast function verification as claimed in claim 7, wherein the state control process of the write transaction state machine comprises: the write transaction state machine defaults to the WR _ IDLE state; if the transaction processing module (3) detects that the receiving request message cache RX _ ReqFlitFifo in the CHI message cache module (4) is not empty in the WR _ IDLE state, reading the receiving request message cache RX _ ReqFlitFifo, decoding the message into write operation, and switching to a CREATE _ TXRESPFLIT state; recording relevant domain sections of a write request message in a CREATE _ TXRESPFLIT state, filling each domain section of a response message to be sent, generating a response message to be sent, outputting the response message to a response message sending buffer TX _ RspFlitFifo, recording the address of the write request message and the byte length of write data, setting the count value initialization value of a write counter to be 0, and switching to a WAIT _ RXDATA state; in the WAIT _ RXDATA state, waiting for the receiving data message cache RX _ DatFlitFifo of the CHI message cache module (4) to be not empty, reading the receiving data message cache RX _ DatFlitFifo, resolving corresponding data according to the read receiving data message, obtaining write SRAM data, returning to the credit control module (2) to complete a receiving data transaction, and switching to the WAIT _ SRAM state; in the WAIT _ SRAM state, outputting a write control signal, a write address and write data of an SRAM module (5), wherein the write address is equal to the address of a write request message recorded in a CREATE _ TXRESPFLIT state, the write data is equal to the write SRAM data obtained in the WAIT _ RXDATA state, the counting value of a write counter accumulates the byte length of the output data in the SRAM module (5), if the write counter is equal to the write data byte length recorded in the CREATE _ TXRESPFLIT state, the write transaction processing is completed, a request transaction completion signal is sent to a credit control module (2), and the state is shifted to a WR _ IDLE state, otherwise, the state is shifted to the WAIT _ RXDATA state.

9. A chip prototype rapid functional verification system comprising a verification device and a verified chip prototype with a memory module, wherein the memory module is the CHI bus memory for rapid functional verification of chip prototypes according to any one of claims 1 to 8.

10. The chip prototype fast function verification system according to claim 9, wherein the verified chip prototype with memory modules is written in an FPGA chip.

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