CN115791818A - Silicon wafer defect detection method - Google Patents
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Abstract
The invention relates to a method for detecting silicon chip defects, which comprises the following steps: cutting the silicon wafer to be detected into two sub silicon wafers to be detected; carrying out metal pollution treatment on two sub silicon wafers to be detected; and carrying out different heat treatments on the two to-be-detected sub silicon wafers, and judging the defects of the to-be-detected silicon wafers according to whether the two to-be-detected sub silicon wafers show copper pollution patterns or not. And cutting the silicon wafer to be detected into two sub silicon wafers to be detected, carrying out different heat treatments on the two sub silicon wafers to be detected, and judging the pv region and the pi region accurately if the two sub silicon wafers to be detected have different results according to the characteristics of the pv region and the pi region.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for detecting silicon wafer defects.
Background
During the single crystal growth by the MCZ method, various crystal-originated defects are generally generated. Such as crystal originated defects (COP), flow Pattern Defects (FPD), oxidation Induced Stacking Faults (OiSF), direct Surface Oxidation Defects (DSOD), etc. The quality of the ingot was classified into the fields of vacancy defect accumulation zone v-rich, direct Surface Oxidation Defect (DSOD), boundary p-band, vacancy point defect zone pv, interstitial point defect zone pi, b-band and interstitial defect accumulation zone i-rich according to the type of defects and the manner of accumulation. The accumulation of these defects causes not only a breakdown voltage failure of the oxide film of the silicon substrate but also a PN junction leakage, a short circuit of the trench capacitor, or an insulation failure, and reduces the yield of the integrated circuit. Therefore, it is required to control the crystal quality in the point defect region by the temperature in the crystal pulling furnace and the crystal growth rate. Further, it is also very important to evaluate and judge the crystal field quickly and accurately. The v-rich field and the i-rich field can be rapidly judged by a method of preferential etching, but the judgment of other fields has limitation.
Disclosure of Invention
In order to solve the technical problem, the invention provides a method for detecting silicon wafer defects, which solves the problem that pv and pi cannot be accurately judged.
In order to achieve the purpose, the embodiment of the invention adopts the technical scheme that: a method for detecting silicon chip defects comprises the following steps:
cutting the silicon wafer to be detected into two sub silicon wafers to be detected;
carrying out metal pollution treatment on two sub silicon wafers to be detected;
and carrying out different heat treatments on the two to-be-detected sub silicon wafers, and judging the defects of the to-be-detected silicon wafers according to whether the two to-be-detected sub silicon wafers show copper pollution patterns or not.
Optionally, the two to-be-detected sub silicon wafers include a first sub silicon wafer and a second sub silicon wafer, the two to-be-detected sub silicon wafers are subjected to different heat treatments, and the defect of the to-be-detected silicon wafer is determined according to whether the two to-be-detected sub silicon wafers show a copper pollution pattern, and the method specifically includes:
continuously carrying out heat treatment on the first sub silicon wafer twice to enable vacancy type point defects to form cluster-like defects so as to adsorb copper complexes, and enable the surface of the first sub silicon wafer not to form copper pollution patterns;
and carrying out primary heat treatment on the second sub silicon wafer, so that the second sub silicon wafer can form a copper pollution pattern on a region without cluster-like defects.
Optionally, the two to-be-detected sub silicon wafers are subjected to different heat treatments, and the defects of the to-be-detected silicon wafers are judged according to whether the two to-be-detected sub silicon wafers show copper pollution patterns, and the method specifically includes the following steps:
if no copper pollution pattern appears on the first sub-silicon wafer and the second sub-silicon wafer, determining the areas corresponding to the silicon wafer to be detected as a v-rich area and an i-rich area;
if the first sub-silicon wafer does not have a copper pollution pattern and the second sub-silicon wafer has the copper pollution pattern, determining that the corresponding area on the silicon wafer to be detected is a pv area;
if the first sub-silicon wafer and the second sub-silicon wafer both have copper pollution patterns, determining that the region corresponding to the silicon wafer to be detected is a pi region;
and when the copper pollution patterns on the two sub silicon wafers to be detected are dispersedly arranged, determining whether the silicon wafers to be detected have COP defects or not by using a DSOD method.
Optionally, the conditions for performing two heat treatments on the first sub-silicon wafer continuously include: the temperature is 800-950 ℃, and the heating time is 50-250 minutes; and the temperature is 950 to 1050 ℃, and the heating time is 50 to 200 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: 950-1050 ℃ and the heating time is 50-200 minutes.
Optionally, when the oxygen concentration on the silicon wafer to be detected is greater than 11.5, the conditions for performing the heat treatment on the first sub-silicon wafer twice continuously include: the temperature is 870 ℃, and the heating time is 220 minutes; and, the temperature is 1000 ℃, and the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature is 980 ℃, and the heating time is 190 minutes;
when the oxygen concentration on the silicon wafer to be detected is between 10.5 and 11.5, the conditions for continuously carrying out two times of heat treatment on the first sub-silicon wafer comprise the following steps: the temperature is 870 ℃, and the heating time is 120 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature is 1000 ℃, and the heating time is 120 minutes;
when the oxygen concentration on the silicon wafer to be detected is between 9.5 and 10.5, the conditions for continuously carrying out the heat treatment twice on the first sub-silicon wafer comprise the following steps: the temperature is 870 ℃, and the heating time is 85 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature is 1000 ℃, and the heating time is 55 minutes;
when the oxygen concentration on the silicon wafer to be detected is less than 9.5, the conditions for continuously carrying out the heat treatment twice on the first sub-silicon wafer comprise that: the temperature is 870 ℃, and the heating time is 85 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature was 940 ℃ and the heating time was 50 minutes.
Optionally, the two to-be-detected sub silicon wafers are subjected to different heat treatments, and the defects of the to-be-detected silicon wafers are judged according to whether the two to-be-detected sub silicon wafers show copper pollution patterns, wherein the steps include:
acquiring an image of a to-be-detected sub silicon wafer, performing binarization processing on the image, and acquiring the width of an area of a copper pollution pattern on the surface of the to-be-detected sub silicon wafer in the radial direction of the to-be-detected sub silicon wafer according to the binarized image;
and if the width of the area of the copper pollution pattern in the radial direction of the to-be-detected sub-silicon wafer is larger than a preset value, judging that the area of the copper pollution pattern is a COP free area.
Optionally, the metal contamination treatment is performed on two to-be-detected sub silicon wafers, and the method specifically includes:
and immersing two sub silicon wafers to be detected into a buffered oxidant solution dissolved with copper nitrate, wherein the concentration of copper ions is 3-8 ppmw.
Optionally, before the step of performing metal contamination treatment on the two to-be-detected sub silicon wafers, the method further comprises the following steps:
and carrying out HF cleaning on the two to-be-detected sub silicon wafers.
The invention has the beneficial effects that: and cutting the silicon wafer to be detected into two sub silicon wafers to be detected, carrying out different heat treatments on the two sub silicon wafers to be detected, and judging the pv region and the pi region accurately if the two sub silicon wafers to be detected have different results according to the characteristics of the pv region and the pi region.
Drawings
FIG. 1 is a schematic flow chart of a method for detecting defects in a silicon wafer according to an embodiment of the present invention;
FIG. 2 is a first schematic diagram showing the images of the surfaces of the silicon wafers to be inspected, which are obtained after different heat treatments according to the embodiment of the present invention;
FIG. 3 is a second schematic diagram of an image of the surface of a to-be-detected sub silicon wafer obtained after different heat treatments in the embodiment of the present invention;
FIG. 4 is a third schematic diagram showing the images of the surfaces of the silicon wafers to be inspected, which are obtained after different heat treatments according to the embodiment of the present invention;
FIG. 5 is a fourth schematic diagram showing the images of the surfaces of the silicon wafers to be tested obtained after different heat treatments in the embodiment of the present invention;
FIG. 6 is a fifth schematic view showing the surface images of the silicon wafer to be inspected, obtained after different heat treatments in the embodiment of the present invention;
FIG. 7 is a sixth schematic view showing an image of the surface of a silicon wafer to be inspected, which is obtained after different heat treatments in the embodiment of the present invention;
FIG. 8 is a schematic diagram seven showing images of the surfaces of the silicon wafers to be inspected, which are obtained after different heat treatments in the embodiment of the present invention;
FIG. 9 is a schematic view eight of images of the surface of a to-be-inspected daughter silicon wafer obtained after different heat treatments in the example of the present invention;
FIG. 10 is a schematic view nine of images of the surface of a silicon wafer to be inspected, which are obtained after different heat treatments in the embodiment of the present invention;
FIG. 11 shows a schematic view obtained after recognition of the image of FIG. 10;
fig. 12 is a schematic diagram of the graph in fig. 11 after the binarization processing.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Various Grown-in defects are generated in the Grown single crystal silicon ingot, and these Grown-in defects become a problem in the device fabrication process. Representative of these primary defects are: dislocation clusters that occur in a region where interstitial silicon is dominant (hereinafter also referred to as "I region") by growth under a low pulling condition, and Crystal Originated grains (COP) that occur in a region where vacancies are dominant (hereinafter also referred to as "V region") by growth under a high pulling condition. In addition, a defect called an Oxidation induced Stacking Fault (OSF) exists in the vicinity of the boundary between the I region and the V region, the defect being distributed in a ring shape.
The distribution of these crystal defects in the grown single crystal silicon ingot depends on the pulling rate V of the crystal and the temperature gradient G of the solid-liquid interface. When the pulling rate V is high, the single crystal silicon ingot is controlled by a COP occurrence region which is a crystal region where COPs are detected, and when V is decreased, an OSF latent nucleus region which develops (becomes surface) as an annular OSF region when a specific oxidation heat treatment is performed is formed.
When the pulling rate V is further decreased, an oxygen precipitation promoting region (hereinafter also referred to as "Pv region") which is a crystal region where oxygen precipitates exist and COP is not detected, an oxygen precipitation suppressing region (hereinafter also referred to as "Pi region") which is a crystal region where oxygen precipitation is not easily caused and COP is not detected, and a dislocation cluster region which is a crystal region where dislocation clusters are detected are formed.
In the silicon wafer produced from the single crystal silicon ingot exhibiting such a defect distribution based on V/G, the OSF region, the Pv region and the Pi region other than the COP-generating region and the dislocation cluster region are all defect-free regions (COP-free regions) in which grown-in defects are extremely small. In addition, a DSOD region, which is a region where Direct Surface Oxide Defect (DSOD) is likely to occur, exists immediately above the Defect-free region. DSOD is a minute COP about 10 to 20nm in diameter detected by Cu decoration treatment.
As the production method of the silicon wafer mostly adopts the Czochralski method, and the growth process is rotating and pulling, the defect distribution of the silicon wafer is basically the same along the radial direction. Therefore, when the silicon wafer is subjected to defect detection, the silicon wafer to be detected can be cut into a plurality of sub silicon wafers to be detected along the diameter direction of the silicon wafer to be detected, and then the sub silicon wafers to be detected are subjected to defect detection.
Fig. 1 is a schematic flow chart of the silicon wafer defect detection method in this embodiment. The method for detecting the silicon wafer defects in the embodiment comprises the following steps:
cutting the silicon wafer to be detected into two sub silicon wafers to be detected;
carrying out metal pollution treatment on two sub silicon wafers to be detected;
and carrying out different heat treatments on the two to-be-detected sub silicon wafers, and judging the defects of the to-be-detected silicon wafers according to whether the two to-be-detected sub silicon wafers show copper pollution patterns or not.
The Pv and pi regions have the following properties:
pv region: the Pv region has a large number of vacancy type point defects, and therefore, the following expressions are made when different heat treatments are respectively performed: after the first heat treatment, the vacancy is enlarged and oxygen nuclei are formed at the vacancy positions; after the second step of heat treatment, oxygen nuclei grow up to form cluster-like defects and adsorb the copper complex, so that the copper complex cannot diffuse to the surface, namely, a copper pollution pattern cannot be formed; and the first heat treatment (i.e., the oxygen nucleus formation step) is omitted, no oxygen nuclei are amplified, i.e., no cluster-like defects are formed, and the copper complex is not adsorbed, and thus can diffuse to the surface, i.e., a copper contamination pattern is formed.
Pi region: unlike the vacancy type point defects, the Pi region has a large number of interstitial type point defects, and even if the first heat treatment is performed to form oxygen nuclei, the oxygen nuclei cannot be formed because there is no site where the oxygen nuclei are generated (i.e., vacancies). Therefore, in the Pi region, no matter which heat treatment method is performed, the copper complex is not adsorbed and smoothly diffused to the surface of the silicon wafer, namely, a copper pollution pattern is formed.
According to the characteristics, carrying out different heat treatments on two sub-silicon wafers to be detected, wherein the two sub-silicon wafers to be detected comprise a first sub-silicon wafer and a second sub-silicon wafer, and if no copper pollution pattern appears on the first sub-silicon wafer and a copper pollution pattern appears on the second sub-silicon wafer, determining that a corresponding area on the silicon wafer to be detected is a pv area;
and if the first sub-silicon wafer and the second sub-silicon wafer both have copper pollution patterns, determining that the region corresponding to the silicon wafer to be detected is a pi region.
In an exemplary embodiment, the two to-be-detected sub silicon wafers include a first sub silicon wafer and a second sub silicon wafer, the two to-be-detected sub silicon wafers are subjected to different heat treatments, and the defect of the to-be-detected silicon wafer is determined according to whether the two to-be-detected sub silicon wafers show a copper pollution pattern, which specifically includes:
continuously carrying out heat treatment on the first sub silicon wafer twice to enable vacancy type point defects to form cluster-like defects so as to adsorb copper complexes, and enable the surface of the first sub silicon wafer not to form copper pollution patterns;
and carrying out primary heat treatment on the second sub silicon wafer, so that the second sub silicon wafer can form a copper pollution pattern on a region without cluster-like defects.
The first silicon wafer is subjected to the second heat treatment by raising the temperature between the first heat treatments, without interruption, and the temperature of the first heat treatment is lower than the temperature of the second heat treatment.
In the step of performing the first heat treatment on the second silicon wafer, the first heat treatment of the two consecutive heat treatments on the first silicon wafer is omitted and the second heat treatment is performed as it is, but the temperature and time for performing the second heat treatment of the two consecutive heat treatments on the first silicon wafer may be the same as or different from the temperature and time for performing the first heat treatment on the second silicon wafer, and the temperature for performing the first heat treatment of the two consecutive heat treatments on the first silicon wafer may be lower than the temperature for performing the first heat treatment on the second silicon wafer.
In an exemplary embodiment, by using the method for detecting defects of a silicon wafer in this embodiment, not only the pv region and the pi region may be determined, but also other regions may be determined. Wherein:
v-rich zone: since the v-rich region has a large number of cluster vacancy type defects, the copper complex is very easily adsorbed by the internal defects and does not diffuse to the surface as long as the heat treatment is performed, whether the heat treatment is performed on both sides continuously or only once; therefore, when the pattern is observed under a highlight lamp, the pattern with copper pollution-free surface can be found;
i-rich zone: since the i-rich region has a large number of cluster-like interstitial defects, the copper complex is very easily adsorbed by internal defects as long as the heat treatment is performed, whether the heat treatment is performed on both sides continuously or only once; since the point defects in this area have already been clustered, sporadic copper contamination patterns can still be seen diffusing to the surface. Therefore, even in the case of copper complex adsorption, the surface is free from copper contamination pattern, in which the density of the i-rich region is slightly higher than that of the Pv region.
In summary, in this embodiment, different heat treatments are performed on two to-be-detected sub silicon wafers, and the defect of the to-be-detected silicon wafer is determined according to whether the two to-be-detected sub silicon wafers show a copper contamination pattern, which specifically includes:
if the first sub silicon wafer and the second sub silicon wafer do not have copper pollution patterns, determining that the defects of the silicon wafer to be detected are v-rich and i-rich;
if the first sub-silicon wafer does not have a copper pollution pattern and the second sub-silicon wafer has the copper pollution pattern, determining that the corresponding area on the silicon wafer to be detected is a pv area;
and if the first sub-silicon wafer and the second sub-silicon wafer both have copper pollution patterns, determining that the corresponding area on the silicon wafer to be detected is a pi area.
Fig. 2 to 9 are schematic diagrams of the sub-silicon wafers to be detected after different heat treatments, respectively, wherein the left sub-silicon wafer is the first sub-silicon wafer after two consecutive heat treatments, and the right sub-silicon wafer is the second sub-silicon wafer after one heat treatment.
In comparison with the two continuous heat treatments of the left-side sub-silicon wafer, the two continuous heat treatments of the left-side sub-silicon wafer are equivalent to the omission of the two continuous heat treatments of the left-side sub-silicon wafer, namely the direct heat treatment of the right-side sub-silicon wafer.
Illustratively, the conditions under which the first sub-wafer is successively subjected to the heat treatments twice include: the temperature is 800-950 ℃, the heating time is 50-250 minutes, the temperature is 950-1050 ℃, and the heating time is 50-200 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: 950-1050 ℃ and the heating time is 50-200 minutes.
It should be noted that, the setting of the temperature and the time for performing the heat treatment on the sub-silicon wafer to be detected is different according to the oxygen concentration of the silicon wafer to be detected, and several setting manners in the present embodiment are described below.
In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be inspected is greater than 11.5, the conditions under which the first sub-silicon wafer is subjected to the heat treatment twice in succession include: the temperature is 870 ℃, the heating time is 220 minutes and 1000 ℃, and the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature was 980 ℃ and the heating time was 190 minutes.
In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be tested is between 10.5 and 11.5, the conditions for performing the heat treatment twice on the first sub-silicon wafer in succession include: the temperature is 870 ℃, and the heating time is 120 minutes; and the temperature is 1000 ℃ and the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature was 1000 ℃ and the heating time was 120 minutes.
In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be tested is between 9.5 and 10.5, the conditions for performing the heat treatment twice on the first sub-silicon wafer in succession include: the temperature is 870 ℃, and the heating time is 85 minutes; and the temperature is 1000 ℃, and the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature was 1000 ℃ and the heating time was 55 minutes.
In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be detected is less than 9.5, the conditions for performing the heat treatment twice on the first sub-silicon wafer in succession include: the temperature is 870 ℃, and the heating time is 85 minutes; and the temperature is 1000 ℃ and the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature was 940 ℃ and the heating time was 50 minutes.
Note that the Band region is a handover region, and depending on the COP, a small amount of copper contamination pattern may appear or a pattern without copper contamination may occur. In order to accurately identify the region, in this embodiment, the method for performing different thermal treatments on two sub silicon wafers to be detected and determining the defect of the silicon wafer to be detected according to whether the two sub silicon wafers to be detected show the copper pollution pattern further includes:
and when the copper pollution patterns on the two sub silicon wafers to be detected are relatively dispersed or no copper pollution patterns exist, determining whether the silicon wafers to be detected have COP areas or not by using a DSOD method.
The DSOD test method is a method for testing small-size COP (Crystal originated Defect) distribution, and the DSOD detection method specifically comprises the following operations: carrying out high-temperature thermal oxidation on the prepared polished silicon wafer to grow an oxide film with a specific thickness; etching the local oxide film on the back of the silicon wafer by using HF acid (hydrofluoric acid) to achieve the purpose of electric conduction; cleaning and drying the etched silicon wafer; a Dummy silicon wafer (debugging silicon wafer) is adopted to ensure that enough copper ions exist in the electrolyte solution; carrying out copper precipitation on the oxide film on the front surface of the silicon wafer to be evaluated; and finally, evaluating the silicon wafer defects through the quantity and distribution of copper deposited on the silicon wafer defect parts. Therefore, for small-size primary defects, the accuracy of the DSOD detection result is of great significance to the evaluation of the quality of the silicon wafer.
By the judgment method, the silicon wafer to be detected after heat treatment shows a copper pollution pattern no matter in a Pv area or a Pi area. While other areas do not have this feature. Based on the phenomenon, the quantitative detection method can be optimized by a qualitative judgment method of the surface copper pollution pattern and is used for mass production. Namely: the density of the copper pollution patterns on the surface of the silicon wafer is scanned for calculation, and the width of the copper pollution patterns is measured to judge whether the silicon wafer is in a Pv region or a Pi region (namely a COP Free region).
Since the i-rich region point defects have been clustered, it can still be seen that sporadic copper contamination patterns have diffused to the surface. In order to eliminate interference, in this embodiment, the two to-be-detected sub silicon wafers are subjected to different heat treatments, and the defects of the to-be-detected silicon wafers are determined according to whether the two to-be-detected sub silicon wafers show copper pollution patterns, and the method includes the following steps:
acquiring an image of a to-be-detected sub silicon wafer, performing binarization processing on the image, and acquiring the width of an area of a copper pollution pattern on the surface of the to-be-detected sub silicon wafer in the radial direction of the to-be-detected sub silicon wafer according to the binarized image; for example, considering the result that the density is lower than a fixed value as no copper contamination pattern, the image appears black; the result of the density being higher than this value is regarded as a copper contamination pattern on the surface, and the image appears white.
And if the width of the area of the copper pollution pattern in the radial direction of the to-be-detected sub-silicon wafer is larger than a preset value, judging that the area of the copper pollution pattern is a COP free area.
Fig. 10 is a schematic view showing an original scanned image, fig. 11 is a schematic view showing the original scanned image after being recognized, and fig. 12 is a schematic view showing the original scanned image after being subjected to binarization processing. This makes it possible to more clearly distinguish each defective region.
In an exemplary embodiment, the present invention further provides a copper contamination pattern analysis apparatus, which includes a closed and dark chamber, and a high-brightness light source for scanning an image, and specifically includes an image scanning unit, an image recognition unit, and a binarization processing unit.
In an exemplary embodiment, the metal contamination treatment of two silicon wafers to be detected specifically includes:
immersing two silicon wafers to be detected into a Buffered Oxidant (BOE) solution dissolved with copper nitrate, wherein the concentration of copper ions is 3-8 ppmw.
In an exemplary embodiment, before the step of subjecting the two pieces of silicon wafers to be detected to metal contamination treatment, the method further comprises the following steps:
and (3) carrying out HF (hydrofluoric acid) (the hydrofluoric acid can react with oxides on the surfaces of the silicon wafers) cleaning on the two silicon wafers to be detected so as to remove the pollution on the surfaces of the silicon wafers to be detected.
In an exemplary embodiment, after the step of subjecting the two pieces of silicon wafers to be detected to metal contamination treatment, the method further includes:
and washing the two sub silicon wafers to be detected by using ultrapure water to remove the residual copper ions on the surfaces of the two sub silicon wafers to be detected, and completely drying.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (8)
1. A method for detecting silicon chip defects is characterized by comprising the following steps:
cutting the silicon wafer to be detected into two sub silicon wafers to be detected;
carrying out metal pollution treatment on two sub silicon wafers to be detected;
and carrying out different heat treatments on the two silicon wafers to be detected, and judging the defects of the silicon wafers to be detected according to whether the two silicon wafers to be detected show copper pollution patterns or not.
2. The method for detecting silicon wafer defects according to claim 1, wherein the two sub-silicon wafers to be detected comprise a first sub-silicon wafer and a second sub-silicon wafer, the two sub-silicon wafers to be detected are subjected to different heat treatments, and defects of the silicon wafers to be detected are judged according to whether the two sub-silicon wafers to be detected show copper contamination patterns, and the method specifically comprises the following steps:
continuously carrying out heat treatment on the first sub silicon wafer twice to enable vacancy type point defects to form cluster-like defects so as to adsorb copper complexes, and enable the surface of the first sub silicon wafer not to form copper pollution patterns;
and carrying out primary heat treatment on the second sub silicon wafer, so that the second sub silicon wafer can form a copper pollution pattern on a region without cluster-like defects.
3. The method for detecting silicon wafer defects according to claim 2, wherein the two sub-silicon wafers to be detected are subjected to different heat treatments, and the defects of the silicon wafers to be detected are judged according to whether the two sub-silicon wafers to be detected show copper contamination patterns, and specifically comprises:
if no copper pollution pattern appears on the first sub-silicon wafer and the second sub-silicon wafer, determining the areas corresponding to the silicon wafer to be detected as a v-rich area and an i-rich area;
if the first sub-silicon wafer does not have the copper pollution pattern and the second sub-silicon wafer has the copper pollution pattern, determining that the corresponding area on the silicon wafer to be detected is a pv area;
if the first sub-silicon wafer and the second sub-silicon wafer both have copper pollution patterns, determining that the region corresponding to the silicon wafer to be detected is a pi region;
and when the copper pollution patterns on the two sub silicon wafers to be detected are dispersedly arranged, determining whether the silicon wafers to be detected have COP defects or not by using a DSOD method.
4. The method for detecting silicon wafer defects according to claim 2, wherein the conditions under which the first sub-wafer is subjected to the heat treatment twice in succession include: the temperature is 800-950 ℃, and the heating time is 50-250 minutes; and the temperature is 950-1050 ℃, and the heating time is 50-200 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: 950-1050 ℃ and the heating time is 50-200 minutes.
5. The method for detecting silicon wafer defects according to claim 2, wherein the conditions under which the first sub-wafer is subjected to the heat treatment twice in succession include: the temperature is 870 ℃, and the heating time is 220 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature is 980 ℃, and the heating time is 190 minutes;
when the oxygen concentration on the silicon wafer to be detected is more than 11.5, the conditions for continuously carrying out the heat treatment twice on the first sub-silicon wafer comprise the following steps: the temperature is 870 ℃, and the heating time is 220 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature is 980 ℃, and the heating time is 190 minutes;
when the oxygen concentration on the silicon wafer to be detected is between 10.5 and 11.5, the conditions for continuously carrying out the heat treatment twice on the first sub-silicon wafer comprise that: the temperature is 870 ℃, and the heating time is 120 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature is 1000 ℃, and the heating time is 120 minutes;
when the oxygen concentration on the silicon wafer to be detected is between 9.5 and 10.5, the conditions for continuously carrying out the heat treatment twice on the first sub-silicon wafer comprise that: the temperature is 870 ℃, and the heating time is 85 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature is 1000 ℃, and the heating time is 55 minutes;
when the oxygen concentration on the silicon wafer to be detected is less than 9.5, the conditions for continuously carrying out the heat treatment twice on the first sub-silicon wafer comprise the following steps: the temperature is 870 ℃, and the heating time is 85 minutes; and, the temperature is 1000 ℃, the heating time is 120 minutes; the conditions for carrying out the primary heat treatment on the second sub-silicon wafer comprise: the temperature was 940 ℃ and the heating time was 50 minutes.
6. The method for detecting silicon wafer defects according to claim 1, wherein the step of judging the defects of the silicon wafer to be detected comprises:
acquiring an image of a to-be-detected sub silicon wafer, performing binarization processing on the image, and acquiring the width of an area of a copper pollution pattern on the surface of the to-be-detected sub silicon wafer in the radial direction of the to-be-detected sub silicon wafer according to the binarized image;
and if the width of the area of the copper pollution pattern in the radial direction of the to-be-detected sub-silicon wafer is larger than a preset value, judging that the area of the copper pollution pattern is a COP free area.
7. The method for detecting the defects of the silicon wafer according to claim 1, wherein the metal contamination treatment is performed on the two sub-silicon wafers to be detected, and specifically comprises:
and immersing two sub silicon wafers to be detected into a buffered oxidant solution dissolved with copper nitrate, wherein the concentration of copper ions is 3-8 ppmw.
8. The method for detecting silicon wafer defects according to claim 1, further comprising the following steps before the two pieces of the sub-silicon wafers to be detected are subjected to metal contamination treatment:
and cleaning the two to-be-detected sub silicon wafers by using HF.
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