CN115777141A - 无插入物多芯片模块 - Google Patents

无插入物多芯片模块 Download PDF

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Publication number
CN115777141A
CN115777141A CN202180048434.7A CN202180048434A CN115777141A CN 115777141 A CN115777141 A CN 115777141A CN 202180048434 A CN202180048434 A CN 202180048434A CN 115777141 A CN115777141 A CN 115777141A
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China
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chip
base film
chips
substrate
module
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CN202180048434.7A
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E.莱奥班东
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International Business Machines Corp
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International Business Machines Corp
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Abstract

提供了无插入物多芯片模块。在一个方面，无插入物多芯片模块包括：基板；设置在基板上的基膜；和压入基膜的芯片，其中芯片的顶面共面。例如，芯片可以具有不同的厚度，并被压入基膜中不同的深度，使得芯片的顶面共面。具有后段制程(BEOL)金属布线的互连层可以存在于芯片上方的晶片上。还提供了形成无插入物多芯片模块的方法。

Description

无插入物多芯片模块
技术领域
本发明涉及多芯片模块技术，尤其涉及无插入物多芯片模块(interposer-lessmulti-chip module)及其加工技术。
背景技术
在集成电路(IC)封装设计中，硅(Si)插入物通常插在芯片和封装基板(substrate)之间。这些Si插入物将芯片相互连接和/或连接到下面的封装基板。Si插入物的使用是提供异质IC组件的高性能集成的领先工艺。
然而，Si插入物实施的一个显著缺点是成本。也就是说，硅通孔(through siliconvia，TSV)工艺经常被用于制造硅插入物，这增加了制造复杂性并抬高了生产成本。此外，Si插入物的使用需要多个接合(bond)步骤。例如，单独芯片、多个芯片模块等首先安装到Si插入物上。然后必须将Si插入物接合到封装基板上。这些多个接合步骤再次增加了制造的复杂性并提高了生产成本。
因此，需要改进的插入物设计及其使用技术。
发明内容
本发明提供无插入物多芯片模块及其加工技术。在本发明的一个方面，提供了一种无插入物的多芯片模块。无插入物多芯片模块包括：基板；设置在基板上的基膜；和压入基膜的芯片，其中芯片的顶面共面。
在本发明的另一方面，提供了另一种无插入物多芯片模块。无插入物多芯片模块包括：基板；设置在基板上的基膜；压入基膜的芯片，其中芯片具有变化的厚度，并且其中芯片压入基膜不同的深度，使得芯片的顶面共面；以及存在于晶片上芯片上方的互连层，其中互连层包括后段制程(BEOL)金属布线。
在本发明的另一方面，提供了一种形成无插入物多芯片模块的方法。该方法包括：在基板上沉积基膜；将芯片放置在基膜上方的基板上；使用加压机将芯片压入基膜，使得芯片的顶面共面；以及固化基膜以交联基膜。
在本发明的又一方面，提供了形成无插入物多芯片模块的另一种方法。该方法包括：在基板上沉积基膜；将芯片放置在基膜上方的基板上，其中芯片具有变化的厚度；使用加压机将芯片压入基膜，其中加压机将具有不同厚度的芯片压入基膜不同深度，使得芯片的顶面共面；固化基膜；以及在芯片上方的晶片上形成互连层，其中互连层包括BEOL金属布线。
通过参考以下详细说明和附图，可更全面地理解本发明，以及本发明的其他特征和优点。
附图说明
图1为根据本发明的实施例的用于形成无插入物多芯片模块的示例性方法的示意图；
图2是示出根据本发明的实施例的具有用于集成在本无插入物多芯片模块上的金属着陆垫(landing pad)的芯片的俯视图；
图3是示出根据本发明的实施例的具有用于芯片的对准标记的示例性基板的俯视图；
图4是示出了根据本发明的实施例的已经沉积到基板上的(未固化)基膜的截面图；
图5是示出了根据本发明的实施例的已经放置在基膜上的基板上的芯片的俯视图；
图6是示出根据本发明的实施例的具有不同厚度的芯片的截面图；
图7是横截面图，其示出了根据本发明的实施例的加压设备(presser device)，该加压设备用于将芯片压入基膜中，以使各种芯片高度变平，使得芯片的顶面共面，之后基膜被固化；
图8是示出根据本发明的实施例的具有后段制程(back-end of line，BEOL)金属布线的互连层的截面图，该互连层已经形成在基膜和芯片上方的基板上；
图9是示出根据本发明的实施例的已经形成在与BEOL金属布线接触的互连层上的焊料凸块(solder bump)的截面图；
图10是示出了根据本发明的实施例的已经被切割成多个片段(segment)的基板的截面图，每个片段包含至少两个芯片；
图11是示出了根据本发明的实施例的其上放置有芯片的基板的截面图，该基板位于已经设置在固定位置台(stage)上的基膜之上，并且已经朝向该台降低加压设备以首先接触具有最大厚度的芯片；
图12是示出了根据本发明的实施例的加压设备已经降低靠近工作台以接下来接触具有第二大厚度的芯片的横截面图；
图13是示出了根据本发明的实施例的加压设备已经降低到更靠近工作台以接下来接触具有第三大厚度的芯片的横截面图；和
图14是示出了根据本发明的实施例的加压设备已经被降低甚至更靠近工作台以接下来接触具有最小厚度的芯片的横截面图。
具体实施方式
如上文所述，常规硅(Si)插入物技术通常涉及使用硅通孔(TSV)工艺和多个接合步骤(即，将芯片和/或芯片模块接合至插入物，然后将插入物接合至封装基板)。这两个因素都增加了制造的复杂性并抬高了生产成本。
有利的是，本文提供了新型多芯片模块设计，完全消除了对插入件的需求(本文也称为“无插入物多芯片模块”)。因此，利用本无插入物多芯片模块设计，消除了TSV和对多个接合步骤的需要，从而简化了整个IC集成。简化了集成过程，降低了整体制造的复杂性，从而降低了生产成本。
如下文所述，实施本无插入物多芯片模块设计的一个挑战是芯片厚度可能不同。因此，当沉积到模块的基板上时，芯片将产生具有不平坦形貌的非平面表面，这证明难以进行后续的金属化工艺。然而，在此已经发现，如果首先将诸如旋涂玻璃、环氧树脂和/或聚酰亚胺的柔韧基膜沉积到基板上，那么可以使用加压设备来平整芯片，从而形成用于金属化的平面表面(planar surface)。也就是说，通过这种方法，柔韧的基膜用于适应芯片之间的厚度差异，由此较厚的芯片比较薄的芯片更大量地压入基膜中，反之亦然。
现在通过参考图1的方法100提供本技术的概述。在步骤102中，将(未固化的)基膜沉积到基板上。根据示例性实施例，基板是半导体晶片(wafer)，诸如硅(Si)晶片。可选地，基板可以由其他材料(诸如二氧化硅(S1O2)、聚合物叠层等)形成。可以采用流延工艺(casting process)(诸如旋涂或喷涂)将基膜均匀沉积在基板上。根据示例性实施例，基膜被沉积在基板上，厚度为约5微米(μm)至约20μm以及其间的范围。
一般而言，基膜包括柔韧的材料，以适应芯片间的厚度变化。“柔韧的”是指未固化的基膜在受到压力时可以改变其形状。因此，当不同厚度的芯片被压入基膜时(见下文)，较厚的芯片可以被进一步压入基膜，从而使它们的高度一致。基膜的另一个要求是它具有与芯片和基板相似的热膨胀系数(CTE)。因此，当基膜和基板随后被加热以固化基膜时，基膜不会将应变施加到芯片或基板上。根据示例性实施例，小于或等于大约3倍(3X)(例如从大约2X到大约3X)的CTE差被认为是“相似的”。仅作为示例，用于基膜的合适材料包括但不限于旋涂玻璃和/或掺杂聚合物。例如，旋涂玻璃包括分散在溶剂中的二氧化硅(SiO2)(和可选的掺杂剂)。在沉积之后，执行退火以去除溶剂并固化旋涂玻璃。
在步骤104中，将芯片放置在基膜上方的基板上。如下面将详细描述的，芯片优选地包含面朝上的金属着陆垫，用于连接到稍后将在工艺中形成的后段制程(BEOL)布线(见下文)。值得注意的是，放置在基板上的芯片的厚度会有一些变化。因此，放置的芯片将在基板的顶部产生非平面表面。不平坦的表面对于随后的BEOL处理是不理想的。
因此，在步骤106中，使用加压设备将芯片物理压入可压缩基膜。加压设备在与芯片的界面处包括横跨(span)多个芯片的平面表面(例如，加压设备横跨所有芯片)。由于该平面表面跨多个芯片的顶部施加力，较厚的芯片将比较薄的芯片被压入基膜更深。也就是说，施加力至少直到加压设备的平面表面接触最薄芯片的顶部。然而，如果需要的话，在这一点上，可以继续按压以将最薄的芯片进一步沉入基膜中。结果是跨芯片的顶部形成了平面表面。自然，这需要将芯片压入基膜的不同深度。也就是说，较厚的芯片将比较薄的芯片在基膜中被压到更大的深度。
在步骤108中，固化基膜。固化将使基膜交联(crosslink)，从而设置芯片在基板上的位置(包括由加压机跨芯片的顶部形成的平面表面)。仅作为示例，通过在约100℃至约500℃及其之间范围的温度处对基膜退火约1小时至约5小时及其之间范围的持续时间来进行固化。
在步骤110中，采用金属化技术在芯片上方的硅晶片上形成BEOL金属布线和焊料凸块。BEOL金属布线接触芯片的顶部的金属着陆垫，并且还提供芯片之间的桥接。如下面将详细描述的，该BEOL金属化可以包括将电介质沉积到芯片(现在具有共面的顶面)上的基板上，并在电介质中形成金属线。具有金属线的电介质在本文也可以称为“互连层”。可以采用受控塌陷芯片连接(C4)工艺在与金属布线接触的互连层上形成焊料凸块。所得到的结构，即具有设置在(固化的)基膜中不同深度的芯片和芯片上的BEOL金属布线的基板，在本文被称为无插入物多芯片模块。
在步骤112中，可将基板切割成多个片段，每个片段包含至少两个芯片。可以采用标准的晶片切割技术。每个片段单独用作其包含的芯片的无插入物多芯片模块。
鉴于方法100中的上述概述，现参照图2-图14描述用于形成无插入物多芯片模块的本技术的示例性实施方式。如图2所示，本发明的无插入物多芯片模块允许不同尺寸(包括不同厚度)的不同类型(例如，存储器、逻辑等)芯片(这里标记为“芯片1”和“芯片2”)的异质集成(见下文)。为了描述的方便和清楚，在本示例中示出了两种芯片类型。然而，应当理解，本技术可以用比所示更多或更少的芯片类型来实现，包括仅使用单一类型芯片的情况。此外，芯片1和芯片2一般表示公共封装内从单个芯片到多个芯片的任何东西(以及任何相关联的组件，诸如电阻器、电容器等)。
如图2所示，芯片(芯片1和芯片2)上可具有对准标记202。在这个特定的示例中，对准标记202被放置在芯片的角落中。仅作为示例，可以使用标准光刻和蚀刻工艺在芯片1和芯片2上形成对准标记202。如下面将详细描述的，在使用基板上的对应的对准标记将芯片放置在基板上的过程中，将使用对准标记202。
如图2所示，芯片(芯片1和芯片2)的顶面上各有多个面朝上的金属着陆垫204。如下文将详细描述的，这些金属着陆垫204将用于将芯片连接到将在工艺中稍后形成的互连层。可以使用所谓的“镶嵌(damascene)”或“双镶嵌(dual damascene)”工艺来形成金属着陆垫204，由此首先在电介质中图案化诸如沟槽和/或通孔的特征(镶嵌工艺)或特征的组合(双镶嵌工艺)。然后用诸如铜(Cu)、钴(Co)、钌(Ru)和/或钨(W)的接触金属填充(一个或多个)特征。可以采用诸如蒸发、溅射或电化学电镀的工艺将接触金属沉积到特征中。在沉积接触金属之前，(一个或多个)特征可以衬有扩散阻挡层(未示出)。用于扩散阻挡层的合适材料包括但不限于钛(Ti)、钽(Ta)、氮化钛(TiN)和/或氮化钽(TaN)。
然后提供基板300。参见图3。根据示例性实施例，基板300是半导体晶片，诸如体硅或绝缘体上硅(SOI)晶片。可选地，基板可以由其他材料(诸如二氧化硅(SiO2)、聚合物叠层等)形成。SOI晶片包括通过掩埋绝缘体与下面的基板分离的SOI层。当掩埋绝缘体是氧化物时，这里将其称为掩埋氧化物或BOX。如图3所示，对准标记302存在于基板300上。如上所述，这些对准标记302对应于芯片上的对准标记202。因此，当芯片放置在基板300上时，通过将芯片上的对准标记202与基板300上的对准标记302对准，可以实现适当的定位。仅举例来说，可以使用标准的光刻和蚀刻工艺在基板300上形成对准标记302。
接下来，将(未固化的)基膜402沉积在基板300上。参见图4。图4提供了沿线A-A'穿过基板300的截面图(见图3)。通常，基膜402可以包括当芯片被压入基膜402时能够适应芯片之间厚度变化的任何材料。基膜的另一个要求是它具有与基板300和芯片的热膨胀系数(CTE)相似的热膨胀系数。因此，当基膜402和基板300稍后被加热以固化基膜402时，没有应变被施加到基板300或芯片上。满足这些要求的基膜的合适材料包括但不限于旋涂玻璃和/或掺杂聚合物。
如上所述，可采用旋涂或喷涂等流延工艺将基膜402均匀沉积在基板300上。根据示例性实施例，基膜402具有从大约5pm到大约20pm的厚度以及其间的范围。
如图5所示，然后将芯片(芯片1和芯片2)放置于基膜402上方的基板300上(thesubstrate 300over the base film 402)。根据示例性实施例，使用拾取和放置机器将芯片放置在基板300上。如上所述，这种放置由芯片上的对准标记202和基板300上的相应对准标记302引导。
如图6所示，碎片具有不同的厚度。图6提供了沿线B-B'(见图5)穿过基板300和芯片(芯片1和芯片2)的截面图。厚度的这种变化可以是由设计(即，不同的芯片、公共封装内的多个芯片等被生产成具有包括厚度在内的不同尺寸)和/或由于工艺变化造成的。
关于工艺变化，如图6所示，同一类型芯片(芯片1或芯片2)的实例可具有不同的厚度。例如，在本示例中，第一芯片1(给定参考数字602)具有厚度T1，并且第二芯片1(给定参考数字606)具有厚度T2，其中T1>T2。同样，第一芯片2(给定参考数字604)具有厚度T3，并且第二芯片2(给定参考数字608)具有厚度T4，其中T3<T4。此外，在本例中，T4>T1>T3>T2。稍后将参考这些厚度尺寸来描述将芯片压入基膜402中以创建跨芯片的顶面的共面表面的过程。
如图6所示，所放置的芯片位于基膜402的顶部，由于芯片之间的厚度变化，跨芯片的顶面形成非共面表面。例如，最厚的芯片/芯片608在基膜402上方具有最高的顶面，接着是芯片602，等等。因此，放置的芯片将在基板顶部产生非平面表面。如果可能的话，试图在基膜402上方的不同高度形成到这些芯片的BEOL金属布线将是极其困难的。
因此，接下来使用加压设备702将芯片压入基膜402中，以拉平各种芯片高度。参见图7。图7提供了沿线B-B'(见图5)穿过基板300和芯片(芯片1和芯片2)的截面图。即，如图7所示，加压设备702在与芯片的界面处包括平坦的平面表面704。在本示例中，平面表面704横跨基板300上的所有芯片602-608。因为该平面表面跨多个芯片的顶部施加力，所以较厚的芯片将比较薄的芯片被压入基膜402更深。例如，如上所述，芯片602、604、606和608分别具有厚度T1、T3、T2和T4，其中T4>T1>T3>T2。因此，芯片602、604、606和608被分别压入基膜402中的深度为D1、D3、D2和D4，其中D4>D1>D3>D2。为了获得跨芯片的顶部的共面表面，施加向下的力，至少直到加压设备702接触最薄芯片的顶部。然而，如果需要的话，压制可以继续超过该点，以便将芯片进一步沉入基膜中。
上文提供了基膜402的示例性厚度值。然而，基膜402的厚度基本上取决于芯片之间的厚度差异。换个角度来看，为了跨芯片的顶部获得共面的表面，基膜402必须至少与最厚芯片和最薄芯片之间的厚度差一样厚。即，基膜402的厚度TBASE FILM大于或等于具有最大厚度的芯片的厚度减去具有最小厚度的芯片的厚度。使用图7中提供的示例作为说明，芯片608在芯片中具有最大的厚度T4，而芯片606在芯片中具有最小的厚度T2。在这种情况下，基膜402的厚度是TBASE FILM≥T4-T2基膜。这样，在加压设备702接触最薄的芯片之前，最厚的芯片可以被压入基膜的量为T4-T2。
将芯片压入基膜402后，固化基膜402。如上所述，固化将使基膜交联，从而设置芯片在基板上的(共面)定位。根据示例性实施例，基膜402的固化通过在约100℃至约500℃及其之间范围的温度处对基板300/基膜402退火约1小时至约5小时及其之间范围的持续时间来进行。
然后在基膜402上方的基板300和芯片上形成互连层802。参见图8。图8提供了沿线B-B'(见图5)穿过基板300和芯片(芯片1和芯片2)的截面图。如图8所示，互连层802包括沉积在基膜402和芯片上的基板300上的电介质804，以及形成在电介质804中的BEOL金属布线806。
合适的电介质804材料包括但不限于氧化物低k材料，诸如氧化硅(SiOx)和/或氧化物超低k层间电介质(ULK-ILD)材料，例如，具有小于2.7的介电常数k。相比之下，二氧化硅(SiO2)的介电常数k值为3.9。合适的超低k介电材料包括但不限于多孔有机硅酸盐玻璃(pSiCOH)。可以使用诸如化学气相沉积(CVD)、原子层沉积(ALD)或物理气相沉积(PVD)的工艺来沉积电介质804，之后可以使用诸如化学机械抛光(CMP)的工艺来平坦化电介质804。值得注意的是，虽然电介质804被描绘为单层，但是电介质804可以包括可选地由不同电介质材料形成的多层。
与金属着陆垫204类似，可使用镶嵌或双镶嵌工艺在电介质804中形成BEOL金属布线806，从而首先在电介质804中图案化诸如沟槽和/或通孔的特征(镶嵌工艺)或特征的组合(双镶嵌工艺)。然后用诸如Cu、Co、Ru和/或w的接触金属填充(一个或多个)特征。可以采用诸如蒸发、溅射或电化学电镀的工艺将接触金属沉积到特征中。在沉积接触金属之前，(一个或多个)特征可以衬有扩散阻挡层(未示出)。如上所述，用于扩散阻挡层的合适材料包括但不限于Ti、Ta、TiN和/或TaN。
如图8所示，BEOL金属布线806接触芯片的顶部的金属着陆垫204。同样如图8所示，金属布线也可以提供芯片之间的桥接。
如图9所示，可采用C4工艺在与BEOL金属布线806接触的互连层802上形成焊料凸块902。图9提供了沿线B-B'(见图5)穿过基板300和芯片(芯片1和芯片2)的截面图。所得到的结构，即在基膜402和具有BEOL金属布线806的芯片上的互连层802中具有不同深度的芯片的基板，在这里被称为无插入物多芯片模块。
最后，如图10所示，可将基板300切割成多个片段1002。每个片段1002包含至少两个芯片。可以采用标准的晶片切割技术。如上所述，每个片段1002单独用作其包含的芯片的无插入物多芯片模块片上插入物。
现在通过参考图11-图14进一步说明加压设备702的动作。与上述结构相似的结构将被相似地编号。如图11所示，在基膜402上放置有芯片602-608的基板300被放置在固定位置的台1102上。即，当加压设备702的位置朝向(或远离)台1102移动时，台1102的位置保持固定。根据示例性实施例，柱(post)1104将加压设备702连接到机械压力机(未示出)，该机械压力机向下/向上朝向/远离台1102致动加压设备702。
当加压设备702向台1102降低时，加压设备702的平面表面704将首先接触芯片中具有最大厚度T4的芯片608。参见图11。即，如上所述，芯片602、604、606和608分别具有厚度T1、T3、T2和T4，其中T4>T1>T3>T2。
当加压设备702降低至更靠近台1102时，加压设备702的平面表面704将接触芯片中厚度T1第二大的芯片602。参见图12。如图12所示，使加压设备702与芯片602接触的这一动作将芯片608压入基膜402中。
继续使加压设备702向下靠近台1102，加压设备702的平面表面704接下来将与芯片604接触，芯片604在芯片中具有第三大厚度T3。参见图13。如图13所示，使加压设备702与芯片604接触的这一动作将芯片602压入基膜，并将芯片608进一步压入基膜402。
将加压设备702进一步向台1102降低，加压设备702的平面表面704将最终与芯片中厚度T2最小的芯片606接触。参见图14。如图14所示，这种使加压设备702与芯片606接触的动作将芯片604压入基膜，并将芯片602和608进一步压入基膜402。
尽管本文描述了本发明的说明性实施例，但应理解，本发明不限于这些精确的实施例，本领域技术人员可在不脱离本发明范围的情况下进行各种其他变更和修改。

Claims (22)

1.一种无插入物多芯片模块，包括：
基板；
设置在所述基板上的基膜；以及
压入所述基膜的芯片，其中所述芯片的顶面共面。
2.根据权利要求1所述的模块，包括：
互连层，存在于所述芯片上方的所述晶片上，其中所述互连层包括后段制程(BEOL)金属布线，
其中所述芯片具有不同的厚度，并且其中所述芯片被压入所述基膜中不同的深度，使得所述芯片的顶面共面。
3.根据权利要求1或权利要求2所述的模块，其中所述基膜包括选自包括以下各项的组的材料：旋涂玻璃、掺杂聚合物及其组合。
4.根据权利要求1所述的模块，其中所述基膜是交联的。
5.根据权利要求1所述的模块，其中所述芯片具有不同的厚度。
6.根据权利要求1所述的模块，其中所述晶片包括硅(Si)晶片。
7.根据权利要求1所述的模块，其中所述芯片包括面朝上的金属着陆垫。
8.根据权利要求2所述的模块，其中所述芯片包括面朝上的金属着陆垫，并且其中所述BEOL金属布线接触所述面朝上的金属着陆垫。
9.根据权利要求2所述的模块，其中所述BEOL金属布线提供所述芯片之间的桥接。
10.根据权利要求2所述的模块，还包括：
焊料凸块，存在于与所述金属布线接触的所述互连层上。
11.一种形成无插入物多芯片模块的方法，所述方法包括：
在基板上沉积基膜；
将芯片放置在所述基膜上方的所述基板上；
使用加压机将所述芯片压入所述基膜，使得所述芯片的顶面共面；以及
固化所述基膜以交联所述基膜。
12.根据权利要求10的方法，其中所述芯片具有不同的厚度，所述方法包括：
在所述芯片上方的所述晶片上形成互连层，其中所述互连层包括BEOL金属布线。
13.根据权利要求10或权利要求11所述的方法，其中所述基膜包括选自包括以下各项的组的材料：旋涂玻璃、掺杂聚合物及其组合。
14.根据权利要求10所述的方法，其中所述加压机包括横跨所述芯片的全部的平面表面。
15.根据权利要求10所述的方法，其中所述芯片具有不同的厚度。
16.根据权利要求10所述的方法，其中所述芯片包括面朝上的金属着陆垫。
17.根据权利要求10所述的方法，其中固化所述基膜包括在约100℃至约500℃及其之间范围的温度处对所述晶片退火约1小时至约5小时及其之间范围的持续时间。
18.根据权利要求11所述的方法，其中所述加压机包括横跨所述芯片的全部的平面表面。
19.根据权利要求11所述的方法，其中所述芯片包括面朝上的金属着陆垫，并且其中所述BEOL金属布线接触所述面朝上的金属着陆垫。
20.根据权利要求11所述的方法，其中所述BEOL金属布线提供所述芯片之间的桥接。
21.根据权利要求11的方法，还包括：
在与所述金属布线接触的互连层上形成焊料凸块。
22.根据权利要求11所述的方法，还包括：
将所述基板切割成多个片段，其中所述多个片段中的每一个包括所述芯片中的至少两个。
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