CN115763588A - Manufacturing method of back-polished heterojunction cell of P-type microcrystalline silicon emitter - Google Patents
Manufacturing method of back-polished heterojunction cell of P-type microcrystalline silicon emitter Download PDFInfo
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- CN115763588A CN115763588A CN202211498685.8A CN202211498685A CN115763588A CN 115763588 A CN115763588 A CN 115763588A CN 202211498685 A CN202211498685 A CN 202211498685A CN 115763588 A CN115763588 A CN 115763588A
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Abstract
The invention discloses a manufacturing method of a back-polished heterojunction cell of a P-type microcrystalline silicon emitter, which comprises the steps of adopting an N-type monocrystalline silicon wafer with one suede surface and one polished surface, depositing a suede intrinsic amorphous silicon layer and a doped microcrystalline N layer on the suede surface, depositing a polished surface intrinsic amorphous silicon layer and a P-type microcrystalline silicon emitter on the polished surface, plating transparent conductive oxide films (ITO) on the two surfaces, and screen-printing silver gate electrodes on the transparent conductive oxide films to form the heterojunction cell of the back-side P-type microcrystalline silicon emitter; the contact between the back-polished silicon wafer and the microcrystalline silicon film layer is better, the thickness of the emitter film layer can be effectively reduced, the crystallization rate of the microcrystalline silicon layer is improved, and the adjustment of the emitter band gap is facilitated, so that the conversion efficiency of the battery is improved, the energy consumption of production is reduced, the production beat is improved, and the economic benefit is improved.
Description
Technical Field
The invention relates to the field of solar cell manufacturing, in particular to a manufacturing method of a back-polished heterojunction cell of a P-type microcrystalline silicon emitter.
Background
The heterojunction battery has various natural advantages of high conversion efficiency, high double-sided rate, almost no light-induced attenuation, good temperature characteristic, capability of using a thin silicon wafer and the like due to the unique double-sided symmetrical structure and the excellent passivation effect of the amorphous silicon layer, and has a short manufacturing process flow and a wide future prospect.
The two sides of the conventional single crystal heterojunction cell are both provided with textured structures, when light irradiates the front side, secondary reflection is generated in the textured structures on the surface, but the light penetrating through a silicon wafer cannot be utilized.
The P-type microcrystalline silicon has the characteristics of high conductivity, continuously adjustable band gap and easiness in uniform doping; research shows that, on one hand, to obtain a P-type microcrystalline silicon film with high conductivity and high crystallization rate, the thickness of a hatching layer needs to be reduced, and the growth condition of the film needs to be far away from the phase change domain of amorphous silicon/microcrystalline silicon; on the other hand, in the heterojunction cell, the P layer should be as thin as possible, and the performance of the cell is in a downward trend on the whole with the increase of the thickness of the microcrystalline silicon layer, wherein the influence on the short-circuit current is the largest; the thickness is increased, which inevitably influences the absorption of the monocrystalline silicon wafer to light and the appearance of a large number of defects in the material; meanwhile, the increase of the thickness also influences the diffusion and the drift of the photon-generated carriers, so that a large number of photon-generated carriers are compounded in the film layer, and the short-circuit current has an obvious descending trend; when the short-circuit current is reduced, the reduction of the open-circuit voltage is influenced, and the filling factor and the conversion efficiency of the battery are reduced.
Disclosure of Invention
The invention aims to provide a manufacturing method of a back-polished heterojunction cell of a P-type microcrystalline silicon emitter, which improves the utilization rate of light, constructs a thinner P-type microcrystalline silicon film, improves the conversion efficiency of the cell and reduces the production energy consumption.
In order to solve the problems, the invention adopts the following technical scheme:
a back-polished heterojunction cell of a P-type microcrystalline silicon emitter comprises an N-type monocrystalline silicon wafer with one polished surface, a polished surface intrinsic amorphous silicon passivation layer, a textured surface intrinsic amorphous silicon passivation layer, a P-type microcrystalline silicon emitter, a doped microcrystalline N layer, a back ITO layer, a front ITO layer, a back screen printing silver gate electrode and a front screen printing silver gate electrode, wherein one polished surface and one polished surface are arranged on the heterojunction cell; the polished surface of the N-type monocrystalline silicon wafer is a backlight surface, and the suede surface is an illuminated surface; the polished surface amorphous silicon passivation layer, the P-type microcrystalline silicon emitter, the back ITO layer and the back screen printing silver gate electrode are sequentially positioned below the polished surface of the N-type monocrystalline silicon wafer; the textured amorphous silicon passivation layer, the doped microcrystalline N layer, the front ITO layer and the front screen printing silver gate electrode are sequentially positioned above the textured surface of the N-type monocrystalline silicon piece.
The manufacturing method of the back-polished heterojunction cell of the P-type microcrystalline silicon emitter comprises the following steps:
the method comprises the following steps that firstly, single-side texturing is conducted on an N-type monocrystalline silicon wafer, wherein a textured surface is an illuminated surface, and a polished surface is a back surface;
depositing an intrinsic amorphous silicon passivation layer on the polished surface;
depositing an intrinsic amorphous silicon passivation layer and a doped microcrystalline N layer on the suede in sequence;
depositing a doped P-type microcrystalline silicon emitter on the polished surface;
depositing a transparent conductive film ITO layer on the suede and the polished surface in a magnetron sputtering mode;
and sixthly, preparing the metal silver grid line electrode on the front side and the back side in a screen printing mode.
Preferably, in step 1, after polishing one surface of the N-type monocrystalline silicon, a SiNx mask with a thickness of 100-140nm is used, and then the SiNx protective layer is removed after texturing the other surface with alkali (KOH).
Preferably, step 2 uses RF radio frequency, plate type PECVD equipment, deposited polishing surface intrinsic amorphous silicon layer is thinner than suede intrinsic amorphous silicon layer by 15% -25%.
Preferably, step 3 is to deposit the intrinsic amorphous silicon layer on the textured surface using RF radio frequency, plate-type PECVD equipment.
Preferably, step 4 deposits a P-type microcrystalline silicon emitter on the polished-face intrinsic amorphous silicon layer using an RF radio frequency, plate PECVD apparatus, the P-type microcrystalline silicon emitter having a thickness of 12-18nm.
Preferably, in the step 5, plate-type PVD equipment is adopted to perform front and back ITO film coating, the thickness of the front film layer is about 100nm, the optimal adjustment can be performed according to the electrical property and the film color, and the thickness of the back ITO film layer is reduced by 10-20%.
Preferably, the monocrystalline silicon wafer is subjected to screen printing in the step 6, slurry of the screen printing is low-temperature silver paste, then the monocrystalline silicon wafer subjected to screen printing is sent into a curing furnace to be cured, the curing temperature is 190 ℃, and double-sided power generation can be realized.
By adopting the technical scheme, the invention has the beneficial effects that:
the silicon heterojunction battery adopts a mask method to obtain an N-type monocrystalline silicon wafer with a polished back surface, an intrinsic amorphous silicon passivation layer and a doped microcrystalline N layer are deposited on the surface of a suede surface, and the intrinsic amorphous silicon passivation layer and a P-type microcrystalline silicon emitter with high crystallization rate are deposited on the polished surface, so that the battery absorbs more light, and the short-circuit current, the open-circuit voltage and the filling factor of the battery are improved.
The back-polished heterojunction cell of the P-type microcrystalline silicon emitter has the beneficial effects that: the open-circuit voltage of the battery piece can be increased to above 749mv, the short-circuit current can be increased to above 9780mA, and the battery conversion efficiency can be increased to above 24.8%. The production takt time of the battery is also improved, and the production energy consumption is reduced, so that the economic benefit of production is improved.
Drawings
FIG. 1 is a schematic diagram of a back-polished heterojunction cell with a P-type microcrystalline silicon emitter;
description of reference numerals:
1-N type monocrystalline silicon wafer;
2-polishing the intrinsic amorphous silicon passivation layer of the surface;
3-textured intrinsic amorphous silicon passivation layer;
a 4-P type microcrystalline silicon emitter;
5-doping a microcrystalline N layer;
6-back ITO layer;
7-front side ITO layer;
8-screen printing silver grid electrode on the back surface;
9-front screen printing silver grid electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, the prior art is capable of
All other embodiments obtained by the person skilled in the art without making any inventive step are within the scope of protection of the present invention.
Examples
As shown in fig. 1, a back-polished heterojunction cell of a P-type microcrystalline silicon emitter is characterized by comprising an N-type monocrystalline silicon wafer 1 with one polished surface and one polished surface, a polished surface intrinsic amorphous silicon passivation layer 2, a textured surface intrinsic amorphous silicon passivation layer 3, a P-type microcrystalline silicon emitter 4, a doped N layer 5, a back ITO layer 6, a front ITO layer 7, a back screen-printed silver gate electrode 8 and a front screen-printed silver gate electrode 9; the polished surface of the N-type monocrystalline silicon wafer 1 is a backlight surface, and the suede surface is an illuminated surface; the polished surface amorphous silicon passivation layer 2, the P-type microcrystalline silicon emitter 4, the back ITO layer 6 and the back screen printing silver gate electrode 8 are sequentially positioned below the polished surface of the N-type monocrystalline silicon wafer 1; the textured amorphous silicon passivation layer 3, the doped microcrystalline N layer 5, the front ITO layer 7 and the front screen printing silver gate electrode 9 are sequentially positioned above the textured surface of the N-type monocrystalline silicon wafer 1. Since the polishing surface is about 30% smaller than the effective area of the texturing surface, the thickness of the film in contact with the polishing surface should be reduced.
In the specific embodiment, the thickness of the polished intrinsic amorphous silicon passivation layer 2 is reduced by about 10-25% compared with the textured intrinsic amorphous silicon passivation layer 3, the thickness of the P-type microcrystalline silicon emitter 4 is reduced by about 20-30% compared with the doped microcrystalline P layer of the double-sided textured monocrystalline silicon heterojunction battery, and the thickness of the back ITO layer 6 is reduced by about 10-20% compared with the front ITO layer 7. The back polishing cell of the P-type microcrystalline silicon emitter can improve the utilization rate of light, the polished surface can effectively reduce the thickness of a film layer, the crystallization rate of P-type microcrystalline silicon is improved, and the conversion efficiency of the cell is improved.
For the silicon wafer with back polishing, the light penetrating through the silicon wafer can be reflected back to the suede surface more effectively, the light penetration is reduced, and the light utilization rate is improved. Meanwhile, the contact between the polished surface and the emitter P-type microcrystalline silicon layer is better, the structure is smoother, the effective contact thickness of the film layer is larger, the reduction of the thickness of a hatching layer is facilitated, the crystallization rate of microcrystalline silicon is improved, the thickness of the film layer of the P-type microcrystalline silicon can be effectively reduced, and the conversion efficiency of the cell is improved. The thinning of the film layer also reduces the deposition time of the film, improves the production beat and efficiency, reduces the gas consumption, reduces the energy consumption of production and improves the economic benefit of production.
The preparation method of the back polishing heterojunction battery of the P-type microcrystalline silicon emitter specifically comprises the following steps:
(1) And (2) putting the N-type monocrystalline silicon wafer 1 into a KOH solution with the concentration of 30-50%, performing back polishing treatment at the temperature of 50-85 ℃ for 5-10min, and testing the surface reflectivity of the silicon wafer to be higher than 45%.
(2) Using tubular PECVD, adopting RF radio frequency power supply with power of 0-5000W and process gas of 0-13313pa, siH of 0.1-1L/min 4 0.02-0.1L/min NH 3 0.2-0.7L/min N 2 The deposition temperature is 100-400 ℃, the back surface of the N-type monocrystalline silicon wafer 1 is masked, and 100-140nm SiN is deposited on the back surface of the silicon wafer x A film.
(3) Using a texturing cleaning machine to etch the masked N-type single-crystal silicon wafer 1 by 30% -50% KOH,2% -5% of a texturing additive by an alkali texturing method (KOH solution), at a solution temperature of 75-85 ℃, for a reaction time of 5-12min, and a test texture reflectivity of less than 12%; and then removing the back mask layer by using an HF acid solution with the concentration of 5-20%, wherein the reaction time is 1.5-30min, and the reflectivity of the polished surface is higher than 45% by testing.
(4) Manufacturing polished surface intrinsic amorphous silicon passivationLayer 2: using PECVD equipment, adopting an RF power supply with the power of 0-8000W, depositing a polishing surface intrinsic amorphous silicon passivation layer 2 with the thickness of 3-6nm on the polishing surface of an N-type monocrystalline silicon wafer 1, and using 0.2-3L/min SiH under the pressure of 40-400pa of process gas 4 H of 2-20L/min 2 The deposition temperature is 100-170 ℃.
(5) Manufacturing a suede intrinsic amorphous silicon passivation layer 3 and a doped microcrystalline N layer 5: using PECVD equipment and an RF power supply with the power of 0-12000W to deposit a textured intrinsic amorphous silicon passivation layer 3 with the thickness of 5-8nm on the textured surface of an N-type monocrystalline silicon wafer 1, and using SiH of 0.2-3L/min under the pressure of 40-400pa of process gas 4 H of 2-20L/min 2 The deposition temperature is 100-170 ℃; then depositing a 10-15nm doped microcrystalline N layer 5 on the textured intrinsic amorphous silicon passivation layer 3 in a second chamber, wherein the process gas is SiH at 0.2-3L/min under the pressure of 300-450pa 4 H of 3-50L/min 2 pH of 0 to 1L/min 3 And 0-0.2L/min CO 2 The deposition temperature is 130-170 ℃.
(6) Manufacturing a polished surface P type microcrystalline silicon emitter 4: using PECVD equipment, adopting an RF power supply with the power of 0-20000W, firstly depositing a hatching layer with the thickness of about 2-3nm on the polishing surface intrinsic amorphous silicon layer 2 of the N-type monocrystalline silicon wafer 1, and using SiH with the process gas pressure of 40-450pa and the pressure of 0.2-3L/min 4 H of 3-50L/min 2 Then depositing a P-type microcrystalline silicon emitter 4 with the thickness of about 12-18nm on the hatching layer under the conditions of high dilution ratio, high power and high gas pressure, wherein the pressure of the process gas is 300-450pa, and SiH is 0.2-1L/s 4 20-50L/min of H 2 0-1L/min of B2H6 and 0-0.2L/min of CO 2 The deposition temperature is 130-150 ℃; wherein B is 2 H 6 And CO 2 The gradient doping is carried out, the thickness of the P-type microcrystalline silicon emitter 4 is reduced by 20-30% compared with that of a double-sided textured battery piece, the process time is correspondingly reduced by 20-30%, and the production energy consumption is reduced.
(7) Plating a transparent oxide film layer: plating with plate PVD equipment and magnetron sputtering method, using ITO layers on both sides, magnetron sputtering with power supply working power of 3-6kw and pressure of 0.3-0.4pa, 2% -10% 2 The thickness of the front ITO layer 7 is about 100nm, the thickness of the back ITO layer 6 is reduced by 10% -20% compared with the thickness of the front ITO layer 7, and the production energy consumption is reduced.
(8) And (3) screen printing and silver paste solidification are carried out on the front side and the back side of the cell, the solidification temperature is 130-180 ℃, and the Ag metal grid line is obtained.
Table 1 lists the efficiency comparison of the heterojunction solar cell provided by the present invention with a conventional heterojunction solar cell, as follows:
| Isc | Voc | FF | Eta | |
| existing heterojunction solar cells | 100％ | 100％ | 100％ | 100％ |
| Solar cell of the embodiment of the application | 100.4％ | 100.2％ | 100.3％ | 101.3％ |
The results show that the heterojunction solar cell provided by the invention has more excellent performance in electrical performance.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. A back-polished heterojunction cell of a P-type microcrystalline silicon emitter is characterized by comprising an N-type monocrystalline silicon wafer (1) with one polished surface and one polished surface, a polished surface intrinsic amorphous silicon passivation layer (2), a textured surface intrinsic amorphous silicon passivation layer (3), a P-type microcrystalline silicon emitter (4), a doped microcrystalline N layer (5), a back ITO layer (6), a front ITO layer (7), a back screen-printed silver gate electrode (8) and a front screen-printed silver gate electrode (9); the polished surface of the N-type monocrystalline silicon wafer (1) is a backlight surface, and the suede surface is an illuminated surface; the polished surface intrinsic amorphous silicon passivation layer (2), the P-type microcrystalline silicon emitter (4), the back ITO layer (6) and the back screen printing silver gate electrode (8) are sequentially located below the polished surface of the N-type monocrystalline silicon wafer (1); the textured amorphous silicon passivation layer (3), the doped microcrystalline N layer (5), the front ITO layer (7) and the front screen printing silver gate electrode (9) are sequentially positioned above the textured surface of the N-type monocrystalline silicon piece (1).
2. A manufacturing method of a back-polished heterojunction cell of a P-type microcrystalline silicon emitter is characterized by comprising the following steps:
firstly, single-side texturing is carried out on an N-type monocrystalline silicon wafer, wherein the textured surface is an illuminated surface, and the polished surface is a back surface;
depositing an intrinsic amorphous silicon passivation layer on the polished surface;
depositing an intrinsic amorphous silicon passivation layer and a doped microcrystalline N layer on the suede in sequence;
depositing a doped P-type microcrystalline silicon emitter on the polished surface;
depositing a transparent conductive film ITO layer on the suede and the polished surface in a magnetron sputtering mode;
and sixthly, preparing the metal silver grid line electrode on the front side and the back side in a screen printing mode.
3. The method for manufacturing a back-polished heterojunction cell with a P-type microcrystalline silicon emitter as claimed in claim 2, wherein the thickness of the polished intrinsic amorphous silicon passivation layer (2) is 15% -25% thinner than the textured intrinsic amorphous silicon passivation layer (3).
4. A method for manufacturing a back-polished heterojunction cell with a P-type microcrystalline silicon emitter as claimed in claim 2, wherein the P-type microcrystalline silicon emitter (4) has a thickness of 12-18nm.
5. The method for manufacturing a back-polished heterojunction cell with a P-type microcrystalline silicon emitter as claimed in claim 2, wherein the thickness of the back ITO layer (6) is reduced by 10% -20% compared with the thickness of the front ITO layer (7).
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| CN202211498685.8A CN115763588A (en) | 2022-11-28 | 2022-11-28 | Manufacturing method of back-polished heterojunction cell of P-type microcrystalline silicon emitter |
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