CN115763524A - Vertically enhanced beta-Ga 2 O 3 UMOSFET device and preparation method thereof - Google Patents

Vertically enhanced beta-Ga 2 O 3 UMOSFET device and preparation method thereof Download PDF

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CN115763524A
CN115763524A CN202211470105.4A CN202211470105A CN115763524A CN 115763524 A CN115763524 A CN 115763524A CN 202211470105 A CN202211470105 A CN 202211470105A CN 115763524 A CN115763524 A CN 115763524A
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beta
layer
highly doped
groove
epitaxial layer
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马永健
唐文博
张晓东
张宝顺
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Suzhou Institute of Nano Tech and Nano Bionics of CAS
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Suzhou Institute of Nano Tech and Nano Bionics of CAS
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Abstract

The invention discloses a vertical enhanced beta-Ga 2 O 3 A UMOSFET device and a method of making the same. The vertically enhanced beta-Ga 2 O 3 The UMOSFET device comprises an epitaxial structure, a source electrode, a drain electrode and a grid electrode, wherein the source electrode, the drain electrode and the grid electrode are arranged in a matched mode with the epitaxial structure, the epitaxial structure comprises a gallium oxide substrate, a gallium oxide drift layer, a current carrier depletion region and a highly-doped gallium oxide epitaxial layer which are arranged in a laminated mode, electrons in the current carrier depletion region are depleted, a groove-shaped structure bottom is arranged in the gallium oxide drift layer, the source electrode is arranged on the highly-doped gallium oxide epitaxial layer and forms ohmic contact with the highly-doped gallium oxide epitaxial layer, and the drain electrode is arranged on the gallium oxide substrate and forms ohmic contact with the gallium oxide substrate. Embodiments of the invention provideA vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can control the threshold voltage by regulating and controlling the injection concentration of N ions and other compensation acceptor materials, so that the condition of mistaken opening can be effectively avoided.

Description

Vertically enhanced beta-Ga 2 O 3 UMOSFET device and preparation method thereof
Technical Field
The invention particularly relates to a vertically enhanced beta-Ga 2 O 3 A UMOSFET device and a preparation method thereof belong to the technical field of semiconductors.
Background
Compared with wide bandgap semiconductors such as GaN and SiC, beta-phase gallium oxide (beta-Ga) 2 O 3 ) Has an ultra-wide band gap of-4.9 eV, a high critical breakdown field of 8MV/cm, a Baliga optimal plot (BFOM) of 3444 times, and a melt-growable beta-Ga 2 O 3 Advantage of the substrate of beta-Ga 2 O 3 Becoming an important member of the new generation of power and radio frequency electronics. Over the last years, some beta-Ga-based compositions have been reported 2 O 3 The lateral and vertical devices of (a). But to fully utilize beta-Ga 2 O 3 In two major advantages of the material, the vertical device has better electric field distribution, and the highly doped low-resistance beta-Ga is utilized 2 O 3 Self-supporting substrates, capable of extremely high breakdown voltages and low on-resistance, have proven beneficial in terms of breakdown voltage, dynamic characteristics, and reliability among other things in the device transition from lateral to vertical for many material systems (including, for example, si, siC, and GaN). Due to p-type beta-Ga 2 O 3 The lack of doping techniques has limited the development of bipolar power devices, requiring more effort to implement high performance enhancement mode (E-mode) transistors. Due to this great challenge, β -Ga 2 O 3 The research on E-mode vertical transistors is rare.
At present beta-Ga 2 O 3 The main structures of vertical transistors are only two, respectively fin field effect transistors (finfets) and Current Aperture Vertical Electron Transistors (CAVETs). The structure of a FinFET is shown in FIG. 1, since p-Ga is currently available 2 O 3 The method has not been realized, the necessity of p-type material can be avoided by adopting the fin-type grid, and Ga is firstly used 2 O 3 Obtaining a layer of highly doped Ga on the drift layer by means of epitaxy or ion implantation 2 O 3 Thin film, then electron beam lithography and ICP etch technique in Ga 2 O 3 Etching a fin-shaped structure on the drift layer, and finally depositing grid metal and source drain metal to successfully prepare the vertical Ga with the fin-shaped grid structure 2 O 3 A MOSFET device. The structure of a Current Aperture Vertical Electron Transistor (CAVET) is shown in FIG. 2. The CAVET device mainly utilizes an ion injection mode to inject Mg ions or N ions into Ga 2 O 3 Forming a current blocking layer in the drift layer by epitaxial or ion implantation of Si in Ga 2 O 3 Forming highly doped Ga on the upper end of the drift layer 2 O 3 The film is convenient to form ohmic contact with the source electrode, and finally, grid metal and source and drain metal are deposited to successfully prepare the vertical Ga with the planar grid structure 2 O 3 A MOSFET device.
However, the fin gate structure of a fin field effect transistor (FinFET) causes the gate oxide field stress at the corner of a trench to be intensified, so that the reliability of the device is influenced, and the voltage endurance capability of the device is reduced. In addition, the small size of the fin-type grid has high requirements on photoetching and etching processes and great process difficulty. Furthermore, the gate dielectric is deposited on the side wall and the bottom of the fin-type gate, so that the parasitic effect of high capacitance and three-dimensional profile is caused. The planar gate adopted by a Current Aperture Vertical Electron Transistor (CAVET) has a simple process, avoids damage caused by dry etching, and can obtain a high-quality MOS interface, but because electrons in a gate depletion channel layer lead to limited thickness of a high-concentration channel layer, and a current hole in a CAVET structure also limits the improvement of current density and is difficult to meet the requirement of high breakdown voltage. In addition, the CAVET device also has the problem of gate-source leakage. Furthermore, these devices operate in accumulation mode, it is difficult to guarantee a sufficient threshold voltage to prevent false turn-on, and normally-off operation in inversion mode is considered a necessary condition for achieving a suitable threshold voltage (power MOSFET is usually ≧ 3V).
Disclosure of Invention
The invention mainly aims to provide a vertically enhanced beta-Ga 2 O 3 A UMOSFET device and a method for making the same, thereby overcoming the deficiencies in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 A UMOSFET device comprising:
β-Ga 2 O 3 a drift layer having a first face and a second face arranged oppositely,
a carrier depletion region formed in the beta-Ga 2 O 3 The surface layer region on one side of the first surface of the drift layer is located;
highly doped beta-Ga 2 O 3 An epitaxial layer formed on the carrier depletion region and the highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is higher than that of the beta-Ga 2 O 3 A drift layer;
a groove-shaped structure with a notch arranged at the highly doped beta-Ga 2 O 3 The surface and the bottom of the epitaxial layer are arranged on the beta-Ga 2 O 3 In the drift layer;
a dielectric layer continuously covering the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the groove wall of the groove-shaped structure are arranged;
at least partial region of the grid is continuously covered on the groove wall of the groove-shaped structure, and the grid is isolated from the groove wall of the groove-shaped structure by a dielectric layer;
source electrode disposed at highly doped beta-Ga 2 O 3 On the epitaxial layer and with said highly doped beta-Ga 2 O 3 Forming an ohmic contact on the epitaxial layer;
drain electrode of beta-Ga 2 O 3 The second surface of the drift layer is electrically connected.
The embodiment of the invention also provides a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device comprises the following steps:
providing beta-Ga 2 O 3 A drift layer to the beta-Ga 2 O 3 Injecting compensation acceptor material into the surface layer region on one side of the first surface of the drift layer and activating the compensation acceptor material so as to enable the beta-Ga to be in contact with the surface layer region 2 O 3 Electron depletion in the surface region of the drift layer to form carriersThe depletion region is formed in the semiconductor substrate,
forming highly doped beta-Ga on the carrier depletion region 2 O 3 Epitaxial layer of said highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is higher than that of the beta-Ga 2 O 3 A drift layer;
manufacturing a groove-shaped structure, and arranging a notch of the groove-shaped structure at the highly doped beta-Ga 2 O 3 The surface and the bottom of the epitaxial layer are arranged on the beta-Ga 2 O 3 In the drift layer;
manufacturing a dielectric layer, and continuously covering the highly doped beta-Ga with the dielectric layer 2 O 3 The surface of the epitaxial layer and the groove wall of the groove-shaped structure are arranged;
manufacturing a source electrode, a drain electrode and a grid electrode, wherein at least partial area of the grid electrode is continuously covered on the groove wall of the groove-shaped structure, and the grid electrode is isolated from the groove wall of the groove-shaped structure by a dielectric layer; the source electrode is arranged at the highly doped beta-Ga 2 O 3 On the epitaxial layer and with said highly doped beta-Ga 2 O 3 Forming an ohmic contact on the epitaxial layer; the drain electrode and the beta-Ga 2 O 3 The second surface of the drift layer is electrically combined with the first surface, and the second surface and the first surface are arranged in a back-to-back mode.
Compared with the prior art, the invention has the advantages that:
1) The embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 UMOSFET device with implant into beta-Ga 2 O 3 N ions and the like in the drift layer are used as compensation acceptors to realize electron depletion, and the vertically enhanced beta-Ga is successfully prepared 2 O 3 The UMOSFET device is a vertically enhanced beta-Ga device relative to a FinFET device 2 O 3 The UMOSFET device has the advantages of small process difficulty, small capacitance and parasitic effect and controllable threshold voltage; compared with a CAVET device, the vertically enhanced beta-Ga provided by the embodiment of the invention 2 O 3 The UMOSFET device has high current density and small gate-source leakage current, and can work under high voltage;
2) The embodiment of the invention provides vertical reinforcementForm beta-Ga 2 O 3 The preparation method of the UMOSFET device can control the threshold voltage by regulating and controlling the injection concentration of N ions and other compensation acceptor materials, thereby effectively avoiding the situation of mistaken opening;
3) The embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can improve the voltage resistance of the device by optimizing the shape of the groove-shaped structure.
Drawings
FIG. 1 is a schematic diagram of a fin field effect transistor (FinFET) structure;
FIG. 2 is a schematic diagram of a Current Aperture Vertical Electron Transistor (CAVET) structure;
FIG. 3 is a vertically enhanced beta-Ga provided in an exemplary embodiment of the present invention 2 O 3 A schematic diagram of a UMOSFET device;
FIG. 4 is a vertically enhanced beta-Ga provided in an exemplary embodiment of the present invention 2 O 3 The preparation flow structure schematic diagram of the UMOSFET device;
FIG. 5a is a vertically enhanced beta-Ga provided in an exemplary embodiment of the present invention 2 O 3 A transfer output curve of the UMOSFET device;
FIG. 5b is a vertically enhanced beta-Ga provided in an exemplary embodiment of the present invention 2 O 3 A transfer output curve of the UMOSFET device;
FIG. 6a and FIG. 6b show N ion implantation concentrations of 5 × 10 18 cm -3 In the embodiment of the invention, the vertically enhanced beta-Ga is provided 2 O 3 An output curve and a transfer curve of the UMOSFET device;
FIG. 6c and FIG. 6d show N ion implantation concentrations of 1 × 10 19 cm -3 In the embodiment of the invention, the vertically enhanced beta-Ga is provided 2 O 3 An output curve and a transfer curve of the UMOSFET device;
FIGS. 7a and 7b show the N ion implantation concentrations of 5X 10 18 cm -3 、1×10 19 cm -3 In the embodiment of the invention, the vertical directionEnhanced beta-Ga 2 O 3 Breakdown curve of a UMOSFET device;
FIGS. 8a and 8b respectively illustrate a vertically enhanced beta-Ga provided in the embodiment of the present invention 2 O 3 The groove-like structure in a UMOSFET device has a U-shaped, inverted trapezoidal, breakdown curve.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
The embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 A UMOSFET device comprising:
β-Ga 2 O 3 a drift layer having a first face and a second face arranged oppositely,
a carrier depletion region formed in the beta-Ga 2 O 3 The surface layer region on one side of the first surface of the drift layer is located;
highly doped beta-Ga 2 O 3 An epitaxial layer formed on the carrier depletion region and the highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is higher than that of the beta-Ga 2 O 3 A drift layer;
a groove-shaped structure with a notch arranged at the highly doped beta-Ga 2 O 3 The surface and the bottom of the epitaxial layer are arranged on the beta-Ga 2 O 3 In the drift layer;
a dielectric layer continuously covering the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the groove wall of the groove-shaped structure are arranged;
at least partial region of the grid is continuously covered on the groove wall of the groove-shaped structure, and the grid is isolated from the groove wall of the groove-shaped structure by a dielectric layer;
source electrode disposed on highly doped beta-Ga 2 O 3 On the epitaxial layer and with said highly doped beta-Ga 2 O 3 Forming an ohmic contact on the epitaxial layer;
drain electrode of beta-Ga 2 O 3 The second surface of the drift layer is electrically bonded.
In one embodiment, the carrier depletion region is formed from the beta-Ga 2 O 3 And the surface layer region on the side of the first surface of the drift layer is formed by conversion after the compensation acceptor material is injected.
In a specific embodiment, the compensated acceptor material includes, but is not limited to, N ions or Mg ions, etc.
In one embodiment, the concentration of compensated acceptor material in the carrier depletion region is 1 × 10 18 cm -3 ～1×10 19 cm -3 。
In one embodiment, the thickness of the carrier depletion region is 300-600 nm, and the beta-Ga 2 O 3 The thickness of the drift layer is 4-10 μm.
In one embodiment, the highly doped β -Ga 2 O 3 The doping concentration of the epitaxial layer is 1 x 10 19 cm -3 ～5×10 19 cm -3 。
In one embodiment, the highly doped β -Ga 2 O 3 The thickness of the epitaxial layer is 100-300 nm.
In a particular embodiment, the depth of the groove-like structures is 800 to 1000nm.
In a specific embodiment, the groove-like structure is a U-shaped groove, a V-shaped groove, an inverted trapezoidal groove or the like.
In one embodiment, the vertically enhanced β -Ga 2 O 3 The UMOSFET device further includes beta-Ga 2 O 3 Substrate of said beta-Ga 2 O 3 A drift layer disposed on the beta-Ga 2 O 3 The drain electrode is arranged on the beta-Ga substrate 2 O 3 The substrate is far away from the beta-Ga 2 O 3 On one side surface of the drift layer and with said beta-Ga 2 O 3 The substrate forms an ohmic contact.
In one embodiment, the highly doped β -Ga 2 O 3 Carrier concentration of epitaxial layer > beta-Ga 2 O 3 Carrier concentration of substrate > beta-Ga 2 O 3 Carrier concentration of the drift layer.
In one embodiment, the beta-Ga 2 O 3 Substrate, beta-Ga 2 O 3 Drift layer, highly doped beta-Ga 2 O 3 The conductive type of the epitaxial layer is n type, and the carrier depletion region is a high resistance layer.
The embodiment of the invention also provides a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device comprises the following steps:
providing beta-Ga 2 O 3 A drift layer to the beta-Ga 2 O 3 Injecting compensation acceptor material into the surface layer region on one side of the first surface of the drift layer and activating the compensation acceptor material so as to enable the beta-Ga to be in contact with the surface layer region 2 O 3 Electrons in the surface layer region of the drift layer are depleted to form a carrier depletion region,
forming highly doped beta-Ga on the carrier depletion region 2 O 3 Epitaxial layer of said highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is higher than that of the beta-Ga 2 O 3 A drift layer;
manufacturing a groove-shaped structure, and arranging a notch of the groove-shaped structure at the highly doped beta-Ga 2 O 3 The surface and the bottom of the epitaxial layer are arranged on the beta-Ga 2 O 3 In the drift layer;
manufacturing a dielectric layer, and continuously covering the highly doped beta-Ga with the dielectric layer 2 O 3 The surface of the epitaxial layer and the groove wall of the groove-shaped structure are arranged;
manufacturing a source electrode, a drain electrode and a grid electrode, wherein at least partial area of the grid electrode is continuously covered on the groove wall of the groove-shaped structure, and the grid electrode is isolated from the groove wall of the groove-shaped structure by a dielectric layer; the source electrode is arranged at the highly doped beta-Ga 2 O 3 On the epitaxial layer and with said highly doped beta-Ga 2 O 3 Forming an ohmic contact on the epitaxial layer; the drain electrode and the beta-Ga 2O 3 The second surface of the drift layer is electrically combined with the first surface, and the second surface and the first surface are arranged in a back-to-back mode.
In one embodiment, the vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device comprises the following steps: to the beta-Ga 2 O 3 Injecting compensation acceptor material into the surface layer region on one side of the first surface of the drift layer, activating the compensation acceptor material, and then annealing for 30-60 min at 1000-1200 ℃ to activate the compensation acceptor material and deplete electrons in the surface layer region.
In a specific embodiment, the compensated acceptor material includes, but is not limited to, N ions or Mg ions, etc.
In one embodiment, the concentration of compensated acceptor material in the carrier depletion region is 1 × 10 18 cm- 3 ～1×10 19 cm -3 。
In one embodiment, the vertically enhanced β -Ga 2 O 3 The preparation method of the UMOSFET device comprises the following steps: first of all, the beta-Ga 2 O 3 Forming an ion-implanted sacrificial layer on the first side of the drift layer, and then the beta-Ga 2 O 3 And injecting a compensation acceptor material into the surface layer region on one side of the first surface of the drift layer.
In one embodiment, the material of the ion implantation sacrificial layer includes, but is not limited to, silicon oxide, etc.
In one embodiment, the thickness of the ion-implanted sacrificial layer is 50 to 200nm.
In one embodiment, the vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device comprises the following steps: directly epitaxially growing a highly doped beta-Ga 2O3 epitaxial layer on the carrier depletion region, or epitaxially growing beta-Ga on the carrier depletion region 2 O 3 Epitaxial layer, implanting ions to form the beta-Ga 2 O 3 Conversion of epitaxial layers to highly doped beta-Ga 2 O 3 An epitaxial layer.
Illustratively, the β -Ga may be grown by MOCVD (metal organic chemical vapor deposition), CVD (chemical vapor deposition), MBE (molecular beam epitaxy), or the like 2 O 3 Epitaxial layer or heightDoping with beta-Ga 2 O 3 An epitaxial layer.
In one embodiment, the preparation method comprises: to the beta-Ga 2 O 3 Implanting Si ions into the epitaxial layer to implant the beta-Ga 2 O 3 Conversion of epitaxial layers to highly doped beta-Ga 2 O 3 An epitaxial layer.
In one embodiment, the highly doped β -Ga 2 O 3 The doping concentration of the epitaxial layer is 1 x 10 19 cm -3 ～5×10 19 cm -3 。
In one embodiment, the highly doped β -Ga 2 O 3 The thickness of the epitaxial layer is 100-300 nm.
In a specific embodiment, the highly doped β -Ga may be doped by ICP (inductively coupled plasma etching), RIE (deep reactive ion etching) or the like 2 O 3 And processing the gate region of the epitaxial layer to form the groove-shaped structure.
In a particular embodiment, the depth of the groove-like structures is 800 to 1000nm.
In a specific embodiment, the groove-shaped structure is a U-shaped groove, a V-shaped groove, an inverted trapezoidal groove or the like.
In one embodiment, the beta-Ga 2 O 3 The drift layer is arranged in beta-Ga 2 O 3 The drain electrode is arranged on the beta-Ga substrate 2 O 3 The substrate is far away from the beta-Ga 2 O 3 On one side surface of the drift layer and with said beta-Ga 2 O 3 The substrate forms an ohmic contact.
In one embodiment, the highly doped β -Ga 2 O 3 Carrier concentration of epitaxial layer > beta-Ga 2 O 3 Carrier concentration of substrate > beta-Ga 2 O 3 Carrier concentration of the drift layer.
In one embodiment, the beta-Ga 2 O 3 Substrate, beta-Ga 2 O 3 Drift layer, highly doped beta-Ga 2 O 3 The conductive type of the epitaxial layer is n type, and the carrier depletion regionIs a high resistance layer.
As will be described in further detail with reference to the accompanying drawings and specific embodiments, it should be noted that, in the embodiments of the present invention, the epitaxial growth process and apparatus such as MOCVD, CVD, or MBE, the ion implantation process and apparatus, the etching process and apparatus, the annealing process and apparatus, and the like may be known to those skilled in the art, and the selection of different process modes, different types of process apparatuses, and the like may not affect the implementation and effect of the embodiments of the present invention.
In a more typical embodiment, a vertically enhanced beta-Ga 2 O 3 UMOSFET device As shown in FIG. 3, the vertically enhanced beta-Ga 2 O 3 The UMOSFET device comprises an epitaxial structure and a source electrode 50, a drain electrode 60 and a gate electrode 70 which are matched with the epitaxial structure;
the epitaxial structure comprises beta-Ga arranged in a stacked manner 2 O 3 Substrate 10, beta-Ga 2 O 3 Drift layer 20, carrier depletion region 30 and highly doped beta-Ga 2 O 3 An epitaxial layer 40, electrons in the carrier depletion region 30 being depleted, the highly doped β -Ga 2 O 3 The region of the epitaxial layer 40 corresponding to the gate 70 is provided with a groove-shaped structure, and the notch of the groove-shaped structure is arranged at the highly doped beta-Ga 2 O 3 The surface and the bottom of the epitaxial layer 40 are arranged on the beta-Ga 2 O 3 In the drift layer 20, at least a partial region of the gate 70 is continuously covered on the groove wall of the groove-shaped structure, the gate 70 is isolated from the groove wall of the groove-shaped structure by a dielectric layer 80, and the source 50 is arranged on the highly doped beta-Ga 2 O 3 On the epitaxial layer 40 and with said highly doped beta-Ga 2 O 3 The epitaxial layer 40 forms an ohmic contact; the drain 60 is disposed at beta-Ga 2 O 3 Substrate 10 is back-to-back with beta-Ga 2 O 3 One side surface of the drift layer 20 and the beta-Ga 2 O 3 The substrate 10 forms an ohmic contact; wherein the beta-Ga is 2 O 3 Substrate 10, beta-Ga 2 O 3 Drift layer 20 and highly doped beta-Ga 2 O 3 The conductivity type of the epitaxial layer 40 is n-type, and the carrier depletion region 30 is a high resistance layer.
In this example, the highly doped β -Ga 2 O 3 Carrier concentration of epitaxial layer 40 > hetero beta-Ga 2 O 3 Carrier concentration of substrate 10 > hetero beta-Ga 2 O 3 The carrier concentration of the drift layer 20.
In the present embodiment, the carrier depletion region 30 is formed by the β -Ga 2 O 3 The surface layer region on the first surface side of the drift layer 20 is formed by injecting a compensation acceptor material, which may be N ions or Mg ions, and the concentration of the compensation acceptor material in the carrier depletion region 30 is 1 × 10 18 cm -3 ～1×10 19 cm -3 (ii) a The thickness of the carrier depletion region 30 is 300-600 nm, and the beta-Ga 2 O 3 The thickness of the drift layer 20 is 4-10 μm.
In this example, the highly doped β -Ga 2 O 3 The doping concentration of the epitaxial layer 40 is 1 × 10 19 cm -3 ～5×10 19 cm -3 Said highly doped beta-Ga 2 O 3 The thickness of the epitaxial layer is 100-300 nm.
In this embodiment, the depth of the groove-like structure is larger than the highly doped β -Ga 2 O 3 The sum of the thicknesses of the epitaxial layer 40 and the carrier depletion region 30 is less than the highly doped beta-Ga 2 O 3 Epitaxial layer 40, carrier depletion region 30 and beta-Ga 2 O 3 The sum of the thicknesses of the drift layer 20, preferably, the depth of the groove-shaped structure is 800-1000 nm; illustratively, the groove-like structure can be a U-shaped groove, a V-shaped groove, an inverted trapezoidal groove or the like.
According to the embodiment of the invention, the vertically enhanced beta-Ga is prepared and obtained by depleting electrons in a drift layer by using an N ion and other compensation acceptor material injection technology 2 O 3 A UMOSFET device; specifically, N ions or Mg ions or the like serving as a compensation acceptor may be implanted into β -Ga 2 O 3 Realizing electron depletion in the drift layer and then realizing the electron-depleted beta-Ga 2 O 3 Outside the surface of the drift layerIn a layer of high concentration of beta-Ga 2 O 3 The film facilitates the formation of the subsequent ohmic contact of the source electrode; meanwhile, a groove-shaped structure with a U-shaped structure and the like is obtained by utilizing ICP etching, so that a dielectric layer and grid metal are conveniently deposited; when a forward voltage is applied to the gate, electron accumulation occurs at the sidewalls of the trench until the device turns on. The invention depletes beta-Ga by using ion implantation technology 2 O 3 Electrons in the drift layer realize vertically enhanced beta-Ga 2 O 3 UMOSFET device for lifting Ga 2 O 3 The performance and reliability of the base power device are of great significance.
The key point of the invention is that the current density and breakdown voltage of the device can be optimized by regulating and controlling the injection concentration of the compensation acceptor material, thereby meeting the application of various scenes; the implantation concentration of the compensated acceptor material is 1 × 10 18 cm -3 ～1×10 19 cm -3 。
Example 1
Referring to FIG. 4, a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 600nm on the first surface and 1 × 10 18 cm -3 The first side is back-to-back beta-Ga 2 O 3 One side surface of the substrate 10, the same as below;
4) Annealing at 1100 deg.C for 30 minutes using a tube annealing furnace or the like to activate N ions to thereby form beta-Ga 2 O 3 Forming beta-Ga with a thickness of 600nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 Electricity in the high resistance layer 30The daughter is depleted;
5) By MOCVD on beta-Ga 2 O 3 High doping (doping concentration of 1 × 10) with thickness of 100nm epitaxially on the surface of the high-resistance layer 30 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by utilizing ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The film is used as a dielectric layer 80 and is coated with Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and lift-off stripping process is adopted to strip the metal, so as to prepare the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Adopting electron beam evaporation and other modes to deposit Ni/Au metal (50/150 nm) on the dielectric layer 80 as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device a.
Example 2
Referring to FIG. 4, a vertical enhancementForm beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 600nm on the first surface and having a thickness of 5 × 10 18 cm -3 The N ion concentration of (a);
4) Annealing at 1100 deg.C for 30 minutes using a tube annealing furnace or the like to activate N ions to thereby form beta-Ga 2 O 3 Forming beta-Ga with a thickness of 600nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) By MOCVD on beta-Ga 2 O 3 High doping (doping concentration of 1 × 10) with thickness of 100nm epitaxially on the surface of the high-resistance layer 30 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by utilizing ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga by using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The film is used as a dielectric layer 80 and is coated with Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and metal stripping is carried out by lift-off stripping process, thus preparing the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Adopting electron beam evaporation and other modes to deposit Ni/Au metal (50/150 nm) on the dielectric layer 80 as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device B.
Example 3
Referring to FIG. 4, a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 600nm on the first surface and 1 × 10 19 cm -3 The N ion concentration of (a);
4) Annealing at 1100 deg.C for 30 minutes using a tube annealing furnace or the like to activate N ions to thereby form beta-Ga 2 O 3 Forming beta-Ga with a thickness of 600nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) MiningBy MOCVD on beta-Ga 2 O 3 High doping (doping concentration of 1 × 10) with a thickness of 100nm epitaxially on the surface of the high-resistance layer 30 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by utilizing ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga by using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The film is used as a dielectric layer 80 and is coated with Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and lift-off stripping process is adopted to strip the metal, so as to prepare the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Ni/Au metal (50/150 nm) is deposited on the dielectric layer 80 by adopting electron beam evaporation and other modes to be used as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device C.
Example 4
Referring to FIG. 4, a vertically enhanced beta-Ga 2 O 3 Preparation of UMOSFET deviceThe method can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 300nm on the first surface and 3 × 10 18 cm -3 The N ion concentration of (a);
4) Annealing at 1200 deg.C for 30 minutes using a tube annealing furnace or the like to activate N ions to thereby heat the beta-Ga 2 O 3 Forming beta-Ga with a thickness of 300nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) By MOCVD on beta-Ga 2 O 3 High doping (doping concentration of 1 × 10) with thickness of 100nm epitaxially on the surface of the high-resistance layer 30 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by utilizing ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga by using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The film is used as a dielectric layer 80 and is coated with Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) By means of electron beam evaporationFront side of the structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and metal stripping is carried out by lift-off stripping process, thus preparing the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Ohmic contact with the substrate;
10 Adopting electron beam evaporation and other modes to deposit Ni/Au metal (50/150 nm) on the dielectric layer 80 as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device D.
Example 5
Referring to FIG. 4, a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting the compensated acceptor material such as Mg ions to a distance of beta-Ga by using an ion implanter 2 O 3 The drift layer 20 is formed at 300nm on the first surface and 1 × 10 18 cm -3 (ii) Mg ion concentration;
4) Annealing at 1000 ℃ for 30 minutes using a tube annealing furnace or the like to activate Mg ions to thereby form beta-Ga 2 O 3 Forming beta-Ga with a thickness of 300nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) By MOCVD on beta-Ga 2 O 3 High resistance layer 30 surface epitaxial 100nm thick high doping (doping concentration 1X 10) 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by utilizing ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga by using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The thin film is used as a dielectric layer 80 and is made of Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (with a thickness of 50/150 nm), and metal stripping is carried out by adopting a 1ift-off stripping process, so as to prepare a source electrode 50 and a drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Adopting electron beam evaporation and other modes to deposit Ni/Au metal (50/150 nm) on the dielectric layer 80 as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device E.
Example 6
Referring to FIG. 4, a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with the thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 600nm on the first surface and having a thickness of 5 × 10 18 cm -3 The N ion concentration of (a);
4) Annealing at 1200 ℃ for 30 minutes using a tube annealing furnace or the like to activate N ions, thereby obtaining a beta-Ga solution 2 O 3 Forming beta-Ga with a thickness of 600nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) By MOCVD on beta-Ga 2 O 3 High doping (doping concentration of 1 × 10) with thickness of 100nm epitaxially on the surface of the high-resistance layer 30 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga by using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The film is used as a dielectric layer 80 and is coated with Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and metal stripping is carried out by lift-off stripping process, thus preparing the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Adopting electron beam evaporation and other modes to deposit Ni/Au metal (50/150 nm) on the dielectric layer 80 as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device F.
Example 7
Referring to FIG. 4, a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 600nm on the first surface and 1 × 10 19 cm -3 The N ion concentration of (a);
4) Annealing at 1200 ℃ for 30 minutes using a tube annealing furnace or the like to activate N ions, thereby obtaining a beta-Ga solution 2 O 3 Forming beta-Ga with a thickness of 600nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) By MOCVD on beta-Ga 2 O 3 High doping (doping) with a thickness of 100nm on the surface of the high-resistance layer 30The impurity concentration is 1X 10 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga by using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The thin film is used as a dielectric layer 80 and is made of Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and metal stripping is carried out by lift-off stripping process, thus preparing the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Adopting electron beam evaporation and other modes to deposit Ni/Au metal (50/150 nm) on the dielectric layer 80 as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and noted as device G.
Comparative example 1
Vertical enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 600nm on the first surface and 1.5 × 10 19 cm -3 The N ion concentration of (a);
4) Annealing at 1100 deg.C for 30 min using a tube annealing furnace or the like to activate N ions to thereby heat the beta-Ga 2 O 3 Forming beta-Ga with a thickness of 600nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) By MOCVD on beta-Ga 2 O 3 High doping (doping concentration of 1 × 10) with thickness of 100nm epitaxially on the surface of the high-resistance layer 30 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by utilizing ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga by using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The film is used as a dielectric layer 80 and is coated with Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 High resistanceSurface of layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and lift-off stripping process is adopted to strip the metal, so as to prepare the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Adopting electron beam evaporation and other modes to deposit Ni/Au metal (50/150 nm) on the dielectric layer 80 as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device H.
Comparative example 2
Vertical enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can comprise the following steps:
1) Will have a thickness of 10 μm of beta-Ga 2 O 3 beta-Ga of drift layer 20 2 O 3 Carrying out organic cleaning on the substrate 10;
2) By PECVD (plasma enhanced chemical vapor deposition) and the like on beta-Ga 2 O 3 Growing SiO with the thickness of 100nm on the first surface of the drift layer 20 2 The film is used as an ion implantation sacrificial layer;
3) Injecting N-ion and other compensation acceptor materials to a distance of beta-Ga by adopting an ion implanter 2 O 3 A drift layer 20 formed at 600nm on the first surface and having a thickness of 5 × 10 17 cm -3 The N ion concentration of (a);
4) Annealing at 1100 deg.C for 30 minutes using a tube annealing furnace or the like to activate N ions to thereby form beta-Ga 2 O 3 Forming beta-Ga with a thickness of 600nm in the drift layer 20 2 O 3 High resistance layer 30 of beta-Ga 2 O 3 The electrons in the high-resistance layer 30 are depleted;
5) By MOCVD on beta-Ga 2 O 3 High doping (doping concentration of 1 × 10) with thickness of 100nm epitaxially on the surface of the high-resistance layer 30 19 cm -3 ～5×10 19 cm -3 )β-Ga 2 O 3 An epitaxial layer 40, thereby forming an epitaxial structure;
6) Highly doped beta-Ga by utilizing ICP etching technology 2 O 3 A U-shaped groove structure with the depth of 800 nm-1000 nm is carved in the grid region on the surface of the epitaxial layer 40, and the notch of the groove structure is arranged on the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the bottom of the groove are positioned in beta-Ga 2 O 3 Wet etching repair is carried out in the drift layer 20;
7) Highly doped beta-Ga using ALD (atomic layer deposition) equipment 2 O 3 A 40nm thick layer of Al is deposited on the epitaxial layer 40 and the surface of the groove-shaped structure 2 O 3 The thin film is used as a dielectric layer 80 and is made of Al 2 O 3 Opening the source region of the thin film to expose the highly doped beta-Ga 2 O 3 An epitaxial layer 40;
8) Adopting electron beam evaporation and other modes on the front surface of the epitaxial structure (highly doped beta-Ga) 2 O 3 Epitaxial layer 40 faces away from beta-Ga 2 O 3 Surface of high-resistance layer) and back surface (. Beta. -Ga) 2 O 3 Substrate back to beta-Ga 2 O 3 The surface of the drift layer) is deposited with Ti/Au metal (the thickness is 50/150 nm), and metal stripping is carried out by lift-off stripping process, thus preparing the source electrode 50 and the drain electrode 60 of the device;
9) Rapid annealing of the sample using RTP (rapid annealing furnace) or the like to achieve the source electrode 50 and highly doped beta-Ga 2 O 3 Epitaxial layer 40, drain 60 and beta-Ga 2 O 3 Substrate ohmic contact;
10 Ni/Au metal (50/150 nm) is deposited on the dielectric layer 80 by adopting electron beam evaporation and other modes to be used as a grid 70 of the device, thereby obtaining the vertically enhanced beta-Ga 2 O 3 A UMOSFET device and denoted as device I.
Comparative example 3
Vertical enhanced beta-Ga 2 O 3 The fabrication method of the UMOSFET device is substantially the same as that of example 1, except that: step 3) and step 4) in comparative example 3 were performed to prepare an electron blocking layer by Mg diffusion using Mg-doped spin-on-glass (spin-on-glass) as a doping source.The device obtained in comparative example 3 was denoted as device I.
Comparative example 4
Comparative example 4 is a FinFET device as shown in fig. 1, denoted as a device.
Comparative example 5
Comparative example 5 is a CAVET device as shown in fig. 2, denoted as device K.
Comparative example 6
The enhanced gallium oxide MOSFET obtained by the preparation method disclosed in CN 110571275A is denoted as device L.
The vertically enhanced beta-Ga provided in embodiments 1 to 7 of the present invention 2 O 3 The transfer output curve of the UMOSFET device is shown in FIG. 5a, and the threshold voltage (V) of the device can be seen th ) Is 7.6V (defined as the current reaching 1A/cm) 2 The time device is started), the device is proved to realize the enhanced characteristic, and the threshold voltage is in a safe region, so that the condition of mistakenly starting the device is avoided; the vertically enhanced beta-Ga provided in embodiments 1 to 7 of the present invention 2 O 3 The transfer output curve of the UMOSFET device is shown in FIG. 5b, and after the current spreading is considered, the current density of the device can reach 219.3A/cm 2 Much higher than the current density of CAVET devices. The N ion implantation concentration, the annealing temperature and the annealing time all affect the threshold voltage and the saturation current density value.
Specifically, when the N ion implantation concentration is 5 × 10 18 cm -3 The output curve of the device is shown in FIG. 6a, when the N ion implantation concentration is 5X 10 18 cm -3 The transfer curve of the device is shown in fig. 6 b; when the N ion implantation concentration is 1 × 10 19 cm -3 The output curve of the device is shown in FIG. 6c, when the N ion implantation concentration is 1X 10 19 cm -3 The device transfer curve of (a) is shown in fig. 6 d. Wherein FIGS. 6a and 6C correspond to the output curves of device B and device C, respectively, where device B is at V DS =10V and V GS Saturation current density at =15V is about 7 times that of device C (neither device takes into account current spreading effects when calculating current density); the main reason why the current density difference is significant is that the difference of N ion implantation concentration affects Ga 2 O 3 The number of freely movable electrons in the drift layer affects the resistivity of the channel layer, resulting in a change in current density. FIGS. 6B and 6d are transfer curves for device B and device C, respectively, defining device current densities up to 1A/cm 2 When the device is started, the threshold voltages of the device B and the device C are respectively 4.2V and 10.7V, the change of the threshold voltage of the device is also caused by the change of the concentration of N ions, and when the injection concentration of the N ions is higher, enough electrons can be accumulated on the side wall of the U-shaped groove by a higher grid voltage to enable the device to be conducted.
FIGS. 7a and 7b show that the N ion implantation concentration is 5X 10 18 cm -3 、1×10 19 cm -3 The breakdown curves of the device B and the device C show that the breakdown voltage of the device C is slightly higher than that of the device B, although Ga is at present 2 O 3 The breakdown voltage of UMOSFET devices is still relatively low, but Ga 2 O 3 The UMOSFET device also belongs to the initial development stage, and the voltage resistance can be greatly improved through a subsequent optimization scheme. According to the current data, the characteristics of low threshold voltage, high current density and low breakdown voltage of a device prepared by low N ion injection concentration can be predicted, and the device can be applied to the aspects of low power and low voltage, such as electronic switches and the like; the device prepared by high N ion implantation concentration has the characteristics of high threshold voltage, low current density and higher breakdown voltage, and can be applied to low-power medium-high voltage aspects such as low-power high-voltage auxiliary power supplies.
Specifically, the influence of the annealing temperature on the device is similar to the implantation concentration, and after the N ion implantation is performed, annealing at 1100 ℃ is required for 30 minutes to activate the N ion, but since the N ion is relatively stable and the activation efficiency is not very high, the effect of increasing the annealing temperature or time to improve the activation efficiency of the N ion at the same N ion implantation concentration is similar to the effect of directly increasing the N ion implantation concentration. Except that increasing the N ion implant concentration introduces more implant damage that affects device leakage and electron mobility, while increasing the anneal temperature or anneal time reduces device damage. Ga 2 O 3 The U-shaped trench in the UMOSFET device is obtained by dry etching, but dry etchingEtching damage to the side wall of the U-shaped groove can be caused by etching, electron mobility is influenced, saturation current density is reduced, the quality of an MOS interface is influenced by the etching damage of the interface, threshold voltage in the period is influenced, and the situation can be changed if a better interface processing method can be selected. In addition, the area of the bottom of the U-shaped groove close to the side wall is often in a 90-degree shape because the process problem cannot obtain an arc shape, so that the field intensity of the area is concentrated to cause the breakdown of a device grid, and the voltage resistance of the device is influenced. If the bottom of the U-shaped groove is replaced by the region of the side wall of the inverted trapezoid structure, the obtuse angle will be formed, the electric field strength in the region can be greatly reduced, and the voltage resistance of the device can be improved, and fig. 8a and 8b respectively show Ga having the U-shaped groove and the inverted trapezoid groove 2 O 3 Breakdown curve of MOSFET device.
Accordingly, the characterization curves of the devices formed in examples 1 and 4 to 7 can be referred to the characterization curves of the devices B and C formed in examples 2 and 3.
The working principle of the invention is to inject N ions into Ga by utilizing the ion injection technology 2 O 3 In the drift layer, ga is depleted by capturing electrons with N ions 2 O 3 Electrons in the drift layer achieve the purpose of blocking source-drain current, and enough electrons can be accumulated on the side wall of the U-shaped groove after a certain grid voltage is applied, so that the device is conducted. Thus, the concentration of N ion implantation controls the number of trapped electrons, indirectly affecting the number of freely movable electrons and thus the threshold voltage and current density of the device.
Compared with the devices obtained in comparative examples 1-6, the vertically enhanced beta-Ga provided by the embodiment of the invention 2 O 3 The key of the preparation method of the UMOSFET device is to realize beta-Ga based on the ion implantation technology 2 O 3 The electrons in the drift layer are used up, and the vertically enhanced beta-Ga is successfully prepared 2 O 3 A UMOSFET device; moreover, the current density and the breakdown voltage of the device can be optimized by regulating and controlling the injection concentration of N ions, so that the application of various scenes is met; and, by optimizing the annealing temperature, implantation concentration, better interface treatment method and optimizing the U-shaped groove shapeThe device performance is greatly improved in the modes of the like; meanwhile, the embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device gets rid of beta-Ga 2 O 3 Dependence of the UMOSFET device on p-type material is beta-Ga 2 O 3 The power device provides a new implementation path.
The embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 UMOSFET device with implant into beta-Ga 2 O 3 N ions and the like in the drift layer are used as compensation acceptors to realize electron depletion, and the vertically enhanced beta-Ga is successfully prepared 2 O 3 The UMOSFET device is a vertically enhanced beta-Ga device relative to a FinFET device 2 O 3 The UMOSFET device has the advantages of small process difficulty, small capacitance and parasitic effect and controllable threshold voltage; compared with a CAVET device, the embodiment of the invention provides a vertically enhanced beta-Ga device 2 O 3 The UMOSFET device has high current density and small gate-source leakage current, and can work under high voltage.
The embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 Specifically, when the injection concentration of N ions is higher, more electrons can be captured in an injection region to form a high-resistance region with better effect, namely the number of electrons which can move freely in the region is extremely small, so that a large amount of electrons can be attracted to gather on the side wall of a U-shaped groove to form electron accumulation, and the conduction of the device is promoted; on the contrary, when the N ion injection concentration is lower, a smaller grid voltage can attract enough electrons to gather. Such as: the N ion implantation concentration is 1 × 10 18 cm -3 The grid voltage needs 4V device to be conducted, namely the threshold voltage is 4V, if the N ion implantation concentration is 1 multiplied by 10 19 cm -3 The gate voltage needs 6V devices to turn on, i.e. the threshold voltage is 6V.
The embodiment of the invention provides a vertically enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device can improve the voltage resistance of the device by optimizing the shape of the groove-shaped structure.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (10)

1. Vertical enhanced beta-Ga 2 O 3 A UMOSFET device, comprising:
β-Ga 2 O 3 a drift layer having a first face and a second face arranged oppositely,
a carrier depletion region formed in the beta-Ga 2 O 3 The surface layer region on one side of the first surface of the drift layer is located;
highly doped beta-Ga 2 O 3 An epitaxial layer formed on the carrier depletion region and the highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is higher than that of the beta-Ga 2 O 3 A drift layer;
a groove-shaped structure with a notch arranged at the highly doped beta-Ga 2 O 3 The surface and the bottom of the epitaxial layer are arranged on the beta-Ga 2 O 3 In the drift layer;
a dielectric layer continuously covering the highly doped beta-Ga 2 O 3 The surface of the epitaxial layer and the groove wall of the groove-shaped structure are arranged;
at least partial region of the grid is continuously covered on the groove wall of the groove-shaped structure, and the grid is isolated from the groove wall of the groove-shaped structure by a dielectric layer;
source electrode disposed on highly doped beta-Ga 2 O 3 On the epitaxial layer and with said highly doped beta-Ga 2 O 3 Forming an ohmic contact on the epitaxial layer;
drain electrode of beta-Ga 2 O 3 The second surface of the drift layer is electrically connected.
2. Vertically enhanced beta-Ga according to claim 1 2 O 3 A UMOSFET device characterized by: the carrier depletion region is formed by the beta-Ga 2 O 3 The surface layer region on one side of the first surface of the drift layer is formed by conversion after compensation acceptor materials are injected;
preferably, the compensated acceptor material comprises N ions or Mg ions;
preferably, the concentration of the compensated acceptor material in the carrier depletion region is 1 × 10 18 cm -3 ～1×10 19 cm -3 ；
And/or the thickness of the carrier depletion region is 300-600 nm, and the beta-Ga 2 O 3 The thickness of the drift layer is 4-10 μm.
3. Vertically enhanced beta-Ga according to claim 1 2 O 3 A UMOSFET device, characterized by: the highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is 1 x 10 19 cm -3 ～5×10 19 cm -3 ；
And/or, the highly doped beta-Ga 2 O 3 The thickness of the epitaxial layer is 100-300 nm.
4. Vertically enhanced beta-Ga according to claim 1 2 O 3 A UMOSFET device characterized by: the depth of the groove-shaped structure is 800-1000 nm;
preferably, the groove-shaped structure is a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove.
5. Vertically enhanced beta-Ga according to claim 1 2 O 3 A UMOSFET device characterized by further comprising beta-Ga 2 O 3 Substrate of said beta-Ga 2 O 3 A drift layer disposed on the beta-Ga 2 O 3 The drain electrode is arranged on the beta-Ga substrate 2 O 3 The substrate is far away from the beta-Ga 2 O 3 One side surface of the drift layerAnd with said beta-Ga 2 O 3 Forming an ohmic contact on the substrate;
preferably, the highly doped beta-Ga 2 O 3 Carrier concentration of epitaxial layer > beta-Ga 2 O 3 Carrier concentration of substrate > beta-Ga 2 O 3 The carrier concentration of the drift layer;
preferably, the beta-Ga 2 O 3 Substrate, beta-Ga 2 O 3 Drift layer, highly doped beta-Ga 2 O 3 The conductive type of the epitaxial layer is n type, and the carrier depletion region is a high resistance layer.
6. Vertical enhanced beta-Ga 2 O 3 The preparation method of the UMOSFET device is characterized by comprising the following steps:
providing beta-Ga 2 O 3 A drift layer to the beta-Ga 2 O 3 Injecting a compensation acceptor material into the surface layer region on the side of the first surface of the drift layer and activating the compensation acceptor material to convert the beta-Ga 2 O 3 Electrons in the surface layer region of the drift layer are depleted to form a carrier depletion region,
forming highly doped beta-Ga on the carrier depletion region 2 O 3 Epitaxial layer of said highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is higher than that of the beta-Ga 2 O 3 A drift layer;
manufacturing a groove-shaped structure, and arranging a notch of the groove-shaped structure at the highly doped beta-Ga 2 O 3 The surface and the bottom of the epitaxial layer are arranged on the beta-Ga 2 O 3 In the drift layer;
manufacturing a dielectric layer, and continuously covering the highly doped beta-Ga with the dielectric layer 2 O 3 The surface of the epitaxial layer and the groove wall of the groove-shaped structure are arranged;
manufacturing a source electrode, a drain electrode and a grid electrode, wherein at least partial area of the grid electrode is continuously covered on the groove wall of the groove-shaped structure, and the grid electrode is isolated from the groove wall of the groove-shaped structure by a dielectric layer; the source electrode is arranged at the highly doped beta-Ga 2 O 3 On the epitaxial layer, andthe highly doped beta-Ga 2 O 3 Forming an ohmic contact on the epitaxial layer; the drain electrode and the beta-Ga 2 O 3 The second surface of the drift layer is electrically combined with the first surface, and the second surface and the first surface are arranged in a back-to-back mode.
7. Vertically enhanced beta-Ga according to claim 6 2 O 3 The preparation method of the UMOSFET device is characterized by comprising the following steps: to the beta-Ga 2 O 3 Injecting a compensation acceptor material into a surface layer region on one side of the first surface of the drift layer, activating the compensation acceptor material, and then annealing for 30-60 min at 1000-1200 ℃ to activate the compensation acceptor material and exhaust electrons in the surface layer region;
preferably, the compensated acceptor material comprises N ions or Mg ions;
preferably, the concentration of the compensated acceptor material in the carrier depletion region is 1 × 10 18 cm 3 ～1×10 19 cm -3 。
8. Vertically enhanced beta-Ga according to claim 6 or 7 2 O 3 The preparation method of the UMOSFET device is characterized by comprising the following steps: first of all, the beta-Ga 2 O 3 Forming an ion-implanted sacrificial layer on the first side of the drift layer, and removing the beta-Ga 2 O 3 Injecting compensation acceptor materials into the surface layer region on one side of the first surface of the drift layer;
preferably, the material of the ion implantation sacrificial layer comprises silicon oxide;
preferably, the thickness of the ion implantation sacrificial layer is 50 to 200nm.
9. Vertically enhanced beta-Ga according to claim 7 2 O 3 The preparation method of the UMOSFET device is characterized by comprising the following steps: epitaxially growing highly doped beta-Ga directly on the carrier depletion region 2 O 3 Epitaxial layer, or firstly, epitaxially growing beta-Ga on the carrier depletion region 2 O 3 Epitaxial layer, and ion implantation methodFormula (II) is 2 O 3 Conversion of epitaxial layers to highly doped beta-Ga 2 O 3 An epitaxial layer;
preferably, the preparation method comprises the following steps: to the beta-Ga 2 O 3 Implanting Si ions into the epitaxial layer to implant the beta-Ga 2 O 3 Conversion of epitaxial layers to highly doped beta-Ga 2 O 3 An epitaxial layer;
preferably, the highly doped beta-Ga 2 O 3 The doping concentration of the epitaxial layer is 1 x 10 19 cm -3 ～5×10 19 cm -3 ；
And/or, the highly doped beta-Ga 2 O 3 The thickness of the epitaxial layer is 100-300 nm.
10. Vertically enhanced beta-Ga according to claim 7 2 O 3 The preparation method of the UMOSFET device is characterized by comprising the following steps: the depth of the groove-shaped structure is 800-1000 nm;
preferably, the groove-shaped structure is a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove;
and/or, the beta-Ga 2 O 3 A drift layer arranged in the beta-Ga 2 O 3 The drain electrode is arranged on the beta-Ga substrate 2 O 3 The substrate is far away from the beta-Ga 2 O 3 On one side surface of the drift layer and with said beta-Ga 2 O 3 Forming ohmic contact on the substrate;
preferably, the highly doped beta-Ga 2 O 3 Carrier concentration of epitaxial layer > beta-Ga 2 O 3 Carrier concentration of substrate > beta-Ga 2 O 3 The carrier concentration of the drift layer;
preferably, the beta-Ga 2 O 3 Substrate, beta-Ga 2 O 3 Drift layer, highly doped beta-Ga 2 O 3 The conductive type of the epitaxial layer is n type, and the carrier depletion region is a high resistance layer.
CN202211470105.4A 2022-11-22 2022-11-22 Vertically enhanced beta-Ga 2 O 3 UMOSFET device and preparation method thereof Pending CN115763524A (en)

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