CN115733473A - Method and device for correcting phase difference of PWM (pulse-Width modulation) signal based on zero-crossing detection signal, storage medium and electronic equipment - Google Patents

Abstract

The embodiment of the application discloses a method and a device for correcting a phase difference of a PWM signal based on a zero-crossing detection signal, a storage medium and electronic equipment, and belongs to the field of signal processing. This application can real-time regulation two way PWM signal's duty cycle, reach the stable effect that keeps at 180 of phase difference of real time control two way PWM signal, can increase whole switching power supply's power, can also reduce switching power supply's loss under the critical conduction mode, the performance index of the system of improvement to and reduce switching power supply's ripple voltage and current distortion rate, promote whole switching power supply's power density and efficiency.

Description

Method and device for correcting phase difference of PWM (pulse-Width modulation) signal based on zero-crossing detection signal, storage medium and electronic equipment

Technical Field

The present disclosure relates to the field of signal processing, and more particularly, to a method and an apparatus for correcting a phase difference of a PWM signal based on a zero-crossing detection signal, a storage medium, and an electronic device.

Background

A Power Factor Correction (PFC) circuit is a circuit commonly used in a switching Power supply, and is used to adjust a relationship between active Power and apparent Power of the switching Power supply, that is, a ratio of the active Power divided by the apparent Power. The PFC circuit is divided into according to the state of its inductor current: a CCM (current continuous mode) PFC circuit, a CRM (current critical conduction mode) PFC circuit, and a DCM (current discontinuous mode) PFC circuit; whether the PFC circuit is provided with a rectifier bridge or not is divided into a bridge PFC circuit and a bridgeless PFC circuit. With the pursuit of the power density and the power factor of the switching power supply, the staggered PFC circuit becomes a common design, the staggered PFC circuit means that two PFC circuits with the same structure are connected in parallel, and in order to further improve the efficiency of the switching power supply, the staggered PFC circuit usually adopts a critical conduction mode (current CRM control), that is, a power tube is turned on until a certain time, the power tube is turned off, the inductive current gradually decreases due to the inductive follow current function, and when the inductive current decreases to zero, the power tube is turned on again, and the process is repeated. In the mode, the power tube is opened near zero current, the opening loss of the power tube is greatly reduced, but the switching frequency is changed, so that the control difficulty is increased while the loss is reduced, meanwhile, in order to reduce current ripples and reduce the current distortion rate, two paths of PWM signals with the phase difference of 180 are usually provided for the staggered PFC circuit, however, in the actual work of the power supply, due to the influence of factors such as signal interference, circuit component errors and the like, two paths of ZCD signals are continuously staggered and overlapped, so that the phase difference of the two paths of PWM signals is periodically and circularly changed between 0 and 360 degrees. If no corresponding control method and strategy exist, the two paths of PWM signals cannot be stably kept near 180 degrees.

Disclosure of Invention

The method, the device, the storage medium and the electronic equipment for correcting the phase difference of the PWM signals based on the zero-crossing detection signals can accurately generate two paths of PWM signals which are staggered by 180 degrees. The technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a method for correcting a phase difference of a PWM signal based on a zero-crossing detection signal, where the method includes:

after the power is on, indicating a first counter, a second counter, a third counter, a fourth counter, a first PWM signal generator, a second PWM signal generator, a third PWM signal generator, a fourth PWM signal generator, a first zero-crossing detection circuit and a second zero-crossing detection circuit to start working;

resetting the count value of the first counter and the count value of the fourth counter upon detection of a first zero-cross signal generated by the first zero-cross detection circuit, and generating a first interrupt signal based on a reset operation of the fourth counter;

resetting the count value of the second counter when a second zero-crossing signal generated by the second zero-crossing detection circuit is detected;

reading a current count value CNT3 (i) of the third counter in response to the first interrupt signal generated at the ith time, and determining a current period value P _ PWM1 (i) of the first counter according to the CNT3 (i); reading a current count value CNT2 (i) of the second counter, taking the read current count value CNT2 (i) as a current phase angle error value E _ CNT1 (i) between the first and second PWM signal generators;

calculating a first adjustment amount Adj _ CMP1 (i) according to (E _ CNT1 (i) -P _ PWM1 (i)/2) × Kx;

if Adj _ CMP1 (i) is greater than the preset maximum step size limiting coefficient MAX _ SET;

updating Adj _ CMP1 (i) to MAX _ SET;

if Adj _ CMP1 is smaller than a preset minimum step limiting coefficient MIN _ SET, updating Adj _ CMP1 (i) to MIN _ SET;

adjusting a current duty cycle of the first PWM signal generator and a current duty cycle of the second PWM signal generator with the updated Adj _ CMP1 (i); where, PWM1_ CMP (i) = Duty1 (i) -Adj _ CMP1 (i), and PWM2_ CMP (i) = Duty2 (i) + Adj _ CMP1 (i).

In a second aspect, an embodiment of the present application provides an apparatus for correcting a phase difference of a PWM signal based on a zero-crossing detection signal, the apparatus including:

the indicating unit is used for indicating the first counter, the second counter, the third counter, the fourth counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the fourth PWM signal generator, the first zero-crossing detection circuit and the second zero-crossing detection circuit to start working after being electrified;

a reset unit configured to reset a count value of the first counter and a count value of the fourth counter when the first zero-cross signal generated by the first zero-cross detection circuit is detected, and generate a first interrupt signal based on a reset operation of the fourth counter;

the reset unit is further configured to reset a count value of the second counter when a second zero-crossing signal generated by the second zero-crossing detection circuit is detected;

the interrupt processing unit is used for responding to the first interrupt signal generated at the ith time, reading the current count value CNT3 (i) of the third counter, and determining the current period value P _ PWM1 (i) of the first counter according to the CNT3 (i); reading a current count value CNT2 (i) of the second counter, taking the read current count value CNT2 (i) as a current phase angle error value E _ CNT1 (i) between the first PWM signal generator and the second PWM signal generator;

a calculation unit configured to calculate a first adjustment amount Adj _ CMP1 (i) according to (E _ CNT1 (i) -P _ PWM1 (i)/2) × Kx;

an updating unit, configured to update Adj _ CMP1 (i) to MAX _ SET if Adj _ CMP1 (i) is greater than a preset maximum step size limiting coefficient MAX _ SET; if Adj _ CMP1 is smaller than a preset minimum step limiting coefficient MIN _ SET, updating Adj _ CMP1 (i) to MIN _ SET;

an adjusting unit for adjusting the current duty cycle of the first PWM signal generator and the current duty cycle of the second PWM signal generator using the updated Adj _ CMP1 (i); where PWM1_ CMP (i) = Duty1 (i) -Adj _ CMP1 (i), and PWM2_ CMP (i) = Duty2 (i) + Adj _ CMP1 (i).

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-mentioned method steps.

In a fourth aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.

The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:

the method has the advantages that the PWM signal generators and the counters which play an auxiliary role are introduced, the PWM signals output by the PWM signal generators and the count values of the counters are used as references, and the interruption signals trigger the calculation and adjustment of the duty ratio adjustment quantity of the two PWM signals.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a PFC circuit according to an embodiment of the present disclosure;

fig. 2 is another schematic structural diagram of a PFC circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of a method for correcting a phase difference of a PWM signal based on a zero-crossing detection signal according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another process for correcting the phase difference of the PWM signals according to the embodiment of the present application;

FIG. 5 is a timing diagram of signals provided by an embodiment of the present application;

FIG. 6 is a timing diagram of another signal provided by an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating an effect of correcting a phase difference of PWM signals according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a device according to the present application;

fig. 9 is a schematic structural diagram of an electronic device provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a two-phase interleaved PFC circuit, and the two-phase interleaved PRC circuit of the present application may be a bridgeless two-phase interleaved PFC circuit or a bridged two-phase interleaved PFC circuit.

Referring to the bridgeless two-phase interleaved PFC circuit (PFC circuit for short) shown in fig. 1, the PFC circuit does not include a rectifier bridge, and includes an AC power supply AC, a first inductor L1, a second inductor L2, a first power tube M1, a second power tube M2, a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, and a dc capacitor C1. The connection relationship of each component in the PFC circuit is shown in fig. 1, which is not described herein again, the power tube in the PFC circuit may be an MOS tube, and the turn-on time of the first power tube M1, the second power tube M2, the fifth power tube M5, and the sixth power tube M6 is short, which is called a fast power tube; the third power tube M3 and the fourth power tube M4 have longer turn-on time, and are called slow power tubes. The first inductor L1, the fifth power tube M5, the first power tube M1 and the third power tube M3 form a main circuit, and the second inductor L2, the sixth power tube, the second power tube M2 and the fourth power tube M4 form a slave circuit. The master PWM signal generator inputs a master PWM signal to a power tube of the master circuit, and the slave PWM signal generator inputs a slave PWM signal to a power tube of the slave circuit.

Referring to fig. 2, the two-phase interleaved PFC circuit with a bridge includes: the power supply comprises rectifier bridges (D01-D04), a first inductor L1, a first diode D1, a first power tube Q1, a second inductor L2, a second diode D2 and a second power tube Q2. The first inductor L1, the first diode D1 and the first power tube Q1 form a main circuit, and the second inductor L2, the second diode D2 and the second power tube Q2 form a slave circuit. The master PWM signal generator inputs a master PWM signal (PWM 1) to the first power transistor Q1, and the slave PWM signal generator inputs a slave PWM signal (PWM 2) to the second power transistor.

It should be noted that the method for correcting the phase difference of the PWM signal based on the zero-crossing detection signal provided in the embodiments of the present application is generally performed by an apparatus.

It should be understood that the number and connection relationships of the electrical devices in fig. 1 are merely illustrative. Other numbers of components and connections may be required according to implementation requirements.

The method for correcting the phase difference of the PWM signal based on the zero-crossing detection signal according to the embodiment of the present application will be described in detail with reference to fig. 3.

Referring to fig. 3, a flowchart of a method for correcting a phase difference of a PWM signal based on a zero-crossing detection signal is provided according to an embodiment of the present application. As shown in fig. 2, the method of the embodiment of the present application may include the steps of:

s301, after power is on, indicating a first counter, a second counter, a third counter, a fourth counter, a first PWM signal generator, a second PWM signal generator, a third PWM signal generator, a fourth PWM signal generator, a first zero-crossing detection circuit and a second zero-crossing detection circuit to start working.

After the PFC circuit is powered on, the processor indicates each device to start working.

The first PWM signal generator is used for generating a main PWM signal and sending the main PWM signal to a power tube of a main circuit, and the first counter is used for counting the PWM signals generated by the first PWM signal generator. The second PWM signal generator is used for generating a slave PWM signal and sending the slave PWM signal to a power tube of the slave circuit, and the second counter is used for counting the PWM signal generated by the second PWM generator. The third PWM signal generator is used to output an auxiliary PWM signal, and the third counter is used to count the PWM signal generated by the third PWM signal generator. The fourth PWM signal generator is for generating an auxiliary PWM signal, and the fourth counter is for counting the PWM signals generated by the fourth PWM signal generator. The fifth PWM signal generator is for generating an auxiliary PWM signal, and the fifth counter is for counting the PWM signals generated by the fifth PWM signal generator. The method for counting by each counter in the application can be as follows: when a rising edge of the PWM signal is detected, the count value is incremented by 1.

The first zero-crossing detection circuit is used for detecting the current value of the inductor in the main circuit, and when the current value is equal to 0, a first zero-crossing signal is output to the processor. The second zero-crossing detection circuit is used for detecting the current value of the inductor in the slave circuit, and when the current value is equal to 0, a second zero-crossing signal is output to the processor.

S302, upon detecting the first zero-crossing signal generated by the first zero-crossing detection circuit, resetting a count value of the first counter and a count value of the fourth counter, and generating a first interrupt signal based on a reset operation of the fourth counter.

The first zero-crossing signal may be a high-level signal, the processor sends a reset instruction to the first counter and the fourth counter when detecting that the first zero-crossing detection circuit outputs the high-level signal, the first counter and the fourth counter reset the count value to zero according to the reset instruction, the fourth counter generates a reset interrupt signal when executing a reset operation, and the reset interrupt signal is the first interrupt signal of the present application to execute a subsequent interrupt processing flow. The first zero-crossing detection circuit periodically generates the first zero-crossing signal, so the fourth counter is periodically reset, and the first interrupt signal also occurs periodically.

Further, when the first interrupt signal is detected, the third counter is reset after a preset time is delayed.

And S303, resetting the count value of the second counter when the second zero-crossing signal generated by the second zero-crossing detection circuit is detected.

The second zero-crossing signal may be a high-level signal, and the processor sends a reset instruction to the second counter when detecting that the second zero-crossing detection circuit outputs a high-level signal, and the second counter resets the count value to zero according to the reset instruction. The second zero crossing detection circuit periodically generates a second zero crossing signal and thus periodically resets the second counter.

S304, determining a current period value of the first counter in response to the first interrupt signal generated the ith time, and determining a current phase angle value between the first PWM signal generator and the second PWM signal generator.

For example, referring to the timing diagram of signals shown in fig. 5, when the first interrupt signal occurs periodically, the processor detects the first interrupt signal generated the ith time in fig. 5, reads the current count value CNT3 (i) of the third counter, determines the current period value P _ PWM1 (i) of the first counter according to CNT3 (i), and further determines the current period value of the first counter by using the following formula: p _ PWM1 (i) = CNT3 (i) + D _ Comp; where D _ Comp is a predetermined delay compensation amount and is a constant. Meanwhile, the processor detects the first interrupt signal generated at the ith time, reads the current count value CNT2 (i) of the second counter, and takes the read current count value CNT2 (i) as the current phase angle error value E _ CNT1 (i) between the first PWM signal generator and the second PWM signal generator, i.e., E _ CNT1 (i) = CNT2 (i).

S305, calculating the current first adjustment amount.

Wherein, a first adjustment value Adj _ CMP1 (i) is calculated according to (E _ CNT1 (i) -P _ PWM1 (i)/2) × Kx, kx is a preset adjustment coefficient, is a constant, and has a value range of 0 < Kx < 1.

S306, if the first adjustment quantity is larger than the preset maximum step limiting coefficient, updating the first adjustment quantity into the maximum step limiting coefficient.

If Adj _ CMP1 (i) in S305 satisfies: adj _ CMP1 (i) > MAX _ SET, then Adj _ CMP1 (i) is updated to MAX _ SET, i.e., adj _ CMP1 (i) = MAX _ SET.

S307, if the first adjustment amount is smaller than the preset maximum step limiting coefficient, updating the first adjustment amount to the minimum step limiting coefficient.

If Adj _ CMP1 (i) in S305 satisfies: adj _ CMP1 (i) < MIN _ SET, and Adj _ CMP1 (i) is updated to MIN _ SET, that is, adj _ CMP1 (i) = MIN _ SET.

And S308, adjusting the current duty ratio of the first PWM signal generator and the current duty ratio of the second PWM signal generator by using the updated first adjustment amount.

The current Duty ratio of the first PWM signal generator is adjusted according to a formula PWM1_ CMP (i) = Duty1 (i) -Adj _ CMP1 (i), where Duty1 (i) is the current Duty ratio of the first PWM signal generator, and PWM1_ CMP (i) is the adjusted Duty ratio of the first PWM signal generator.

And adjusting the current Duty ratio of the second PWM signal generator according to the formula PWM2_ CMP (i) = Duty2 (i) + Adj _ CMP1 (i), where Duty2 (i) is the current Duty ratio of the second PWM signal generator, and PWM2_ CMP (i) is the adjusted Duty ratio of the second PWM signal generator.

Further, in the case that there is enough margin for the loop time, on the basis of fig. 3, the present application may also adjust the duty ratio of the PWM signals of the master and the slave by using the method of fig. 4, where the method includes:

and S401, indicating the fifth counter, the sixth counter, the fifth PWM signal generator and the sixth PWM signal generator to work.

The fifth counter is used for counting the PWM signals output by the fifth PWM signal generator, and the sixth counter is used for counting the PWM signals output by the sixth PWM signal generator.

S402, when the second zero-crossing signal generated by the second zero-crossing detection circuit is detected, resetting the count value of the sixth counter, and generating a second interrupt signal based on the resetting operation of the sixth counter.

Since the second zero-crossing signal is generated continuously, the sixth counter is also reset continuously, and accordingly, the second interrupt signal is generated periodically. The first interrupt signal and the second interrupt signal may or may not be generated simultaneously in this application.

S403, determining a current period value of the second counter in response to the second interrupt signal generated at the jth time, and determining a current phase angle error value between the first PWM signal generator and the second PWM signal generator.

For example, referring to the timing diagram shown in fig. 6, when the processor detects the j-th generated second interrupt signal, the processor reads the current count value CNT5 (j) of the fifth counter, determines the current period value P _ PWM2 (j) of the second counter according to CNT5 (j), and further determines the current period value of the second counter according to the following formula: p _ PWM2 (j) = CNT5 (j) + D _ Comp; wherein D _ Comp is a preset delay compensation amount. Meanwhile, when the second interrupt signal generated at the jth time is detected, the current count value CNT1 (j) of the first counter is read, and CNT1 (j) is used as the current phase angle error value E _ CNT2 (j) between the first PWM signal generator and the second PWM signal generator, that is, E _ CNT2 (j) = CNT1 (j).

Furthermore, after the second interrupt signal generated for the jth time is detected, the fifth counter is reset after a preset time is delayed.

And S404, calculating the current second adjustment amount.

Wherein, the current second adjustment amount is calculated according to the formula: adj _ CMP2 (j) = (E _ CNT2 (j) -P _ PWM2 (j)/2) × Kx, kx is an adjustment coefficient and is a constant.

S405, if the second adjustment quantity is larger than the preset maximum step limiting coefficient, updating the second adjustment quantity into the maximum step limiting coefficient.

How to satisfy the following conditions according to Adj _ CMP2 (j) calculated in S404: adj _ CMP2 (j) > MAX _ SET, and Adj _ CMP2 (j) is updated to MAX _ SET, that is, adj _ CMP2 (j) = MAX _ SET.

And S406, if the second adjustment amount is smaller than the preset minimum step limiting coefficient, updating the second adjustment amount to the minimum step limiting coefficient.

Wherein, according to Adj _ CMP2 (j) calculated in S404, if: adj _ CMP2 (j) is smaller than MIN _ SET, and Adj _ CMP2 (j) is updated to MIN _ SET, i.e., adj _ CMP2 (j) = MIN _ SET.

And S407, adjusting the current duty ratio of the first PWM signal generator and the current duty ratio of the second PWM signal generator by using the updated second adjustment amount.

The current Duty ratio of the first PWM signal generator is adjusted according to a formula PWM1_ CMP (j) = Duty1 (j) -Adj _ CMP1 (j), where Duty1 (j) is the current Duty ratio of the first PWM signal generator, and PWM1_ CMP (j) is the Duty ratio adjusted by the first PWM signal generator.

And adjusting the current Duty ratio of the second PWM signal generator according to a formula PWM2_ CMP (j) = Duty2 (j) + Adj _ CMP1 (j), wherein Duty2 (j) is the current Duty ratio of the second PWM signal generator, and PWM2_ CMP (j) is the adjusted Duty ratio of the second PWM signal generator.

Referring to the signal timing diagram shown in fig. 7, the PWM signal duty ratios of the master path and the slave path are adjusted by the method of the present application, and finally, two paths of interleaved 180 PWM signals are formed, and the phases of the counting waveforms of the first counter and the second counter are also staggered by 180 degrees.

Further, in the embodiment of the present application, the initial duty ratios of the first PWM signal generator to the sixth PWM signal generator are also determined according to actual requirements, and the present application is not limited, for example: in the initial state, the duty ratios of the signal generators are equal, and the rising edges or the falling edges of the signals are aligned.

Furthermore, the first to sixth counters in the present application may be software counters built in the processor, or may be hardware counters external to the processor, and are not limited herein.

In the scheme of the embodiment of the application, during execution, a plurality of PWM signal generators and counters which play an auxiliary role are introduced, PWM signals output by the PWM signal generators and count values of the counters are used as reference, and the calculation and adjustment of duty ratio adjustment quantity of two PWM signals are triggered by interrupt signals.

The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.

Referring to fig. 8, a schematic structural diagram of a PWM signal generating apparatus of a PFC circuit according to an exemplary embodiment of the present application is shown, which is hereinafter referred to as the apparatus 8 for short. The apparatus 8 may be implemented as all or part of an electronic device by software, hardware or a combination of both. The device 8 comprises: an indication unit 801, a reset unit 802, an interrupt processing unit 803, a calculation unit 804, an update unit 805, an adjustment unit 806.

The indicating unit 801 is configured to indicate, after being powered on, the first counter, the second counter, the third counter, the fourth counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the fourth PWM signal generator, the first zero-cross detection circuit, and the second zero-cross detection circuit to start working;

a reset unit 802 configured to reset a count value of the first counter and a count value of the fourth counter when the first zero-cross signal generated by the first zero-cross detection circuit is detected, and generate a first interrupt signal based on a reset operation of the fourth counter;

the reset unit 802 is further configured to reset a count value of the second counter when the second zero-crossing signal generated by the second zero-crossing detection circuit is detected;

an interrupt processing unit 803, configured to read a current count value CNT3 (i) of the third counter in response to the first interrupt signal generated for the ith time, and determine a current period value P _ PWM1 (i) of the first counter according to the CNT3 (i); reading a current count value CNT2 (i) of the second counter, taking the read current count value CNT2 (i) as a current phase angle error value E _ CNT1 (i) between the first PWM signal generator and the second PWM signal generator;

a calculating unit 804, configured to calculate a first adjustment amount Adj _ CMP1 (i) according to (E _ CNT1 (i) -P _ PWM1 (i)/2) × Kx;

an updating unit 805, configured to update Adj _ CMP1 (i) to MAX _ SET if Adj _ CMP1 (i) is greater than a preset maximum step size limiting coefficient MAX _ SET; if Adj _ CMP1 is smaller than a preset minimum step limiting coefficient MIN _ SET, updating Adj _ CMP1 (i) to MIN _ SET;

an adjusting unit 806 for adjusting a current duty cycle of the first PWM signal generator and a current duty cycle of the second PWM signal generator with the updated Adj _ CMP1 (i); where, PWM1_ CMP (i) = Duty1 (i) -Adj _ CMP1 (i), and PWM2_ CMP (i) = Duty2 (i) + Adj _ CMP1 (i).

In one or more possible embodiments, the indication unit 801 is further configured to:

indicating the fifth counter, the sixth counter, the fifth PWM signal generator and the sixth PWM signal generator to work;

a reset unit 802, further configured to reset a count value of a sixth counter when detecting a second zero-crossing signal generated by the second zero-crossing detection circuit, and generate a second interrupt signal based on a reset operation of the sixth counter;

the interrupt processing unit 803 is also configured to: reading a current count value CNT5 (j) of the fifth counter in response to the second interrupt signal generated for the jth time, and determining a current period value P _ PWM2 (j) of the second counter according to the CNT5 (j); reading a current count value CNT1 (j) of the first counter, using CNT1 (j) as a current phase angle error value E _ CNT2 (j) between the first PWM signal generator and the second PWM signal generator;

the computing unit 804 is further configured to: calculating a current second adjustment amount Adj _ CMP2 (j); wherein Adj _ CMP2 (j) = (E _ CNT2 (j) -P _ PWM2 (j)/2) × Kx

The update unit 805 is further configured to: if Adj _ CMP2 (j) is larger than a preset maximum step limiting coefficient MAX _ SET, updating Adj _ CMP2 (j) to MAX _ SET;

if Adj _ CMP2 is smaller than the preset minimum step limiting coefficient MIN _ SET, updating Adj _ CMP2 (j) to MIN _ SET;

the adjusting unit 806 is further configured to: adjusting the current duty cycle of the first PWM signal generator and the current duty cycle of the second PWM signal generator by using the updated Adj _ CMP1 (j); where, PWM1_ CMP (j) = Duty1 (j) -Adj _ CMP2 (j), and PWM2_ CMP (j) = Duty2 (j) + Adj _ CMP2.

In one or more possible embodiments, said determining the current period value P _ PWM1 (i) of said first counter from CNT3 (i) comprises:

determining a current period value of the first counter according to the following formula:

p _ PWM1 (i) = CNT3 (i) + D _ Comp; wherein D _ Comp is a preset delay compensation amount.

In one or more possible embodiments, determining the current period value pwwm 2 (j) of the second counter from CNT6 (j) includes:

determining a current period value of the second counter according to the following formula:

p _ PWM2 (j) = CNT5 (j) + D _ Comp; wherein D _ Comp is a preset delay compensation amount.

In one or more possible embodiments, the method further comprises:

a configuration unit, configured to configure initial duty ratios of the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, and the fourth PWM signal generator.

In one or more possible embodiments, the initial duty cycles of the first PWM signal generator and the second PWM signal generator are equal.

It should be noted that, when the apparatus 8 provided in the foregoing embodiment executes the method for correcting the phase difference of the PWM signal based on the zero-crossing detection signal, only the division of the above functional blocks is taken as an example, in practical applications, the above function distribution may be performed by different functional blocks according to needs, that is, the internal structure of the device may be divided into different functional blocks, so as to perform all or part of the above described functions. In addition, the PWM signal generating apparatus of the PFC circuit provided in the above embodiment and the embodiment of the method for correcting the phase difference of the PWM signal based on the zero-crossing detection signal belong to the same concept, and details of the implementation process are referred to in the embodiment of the method, which is not described herein again.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

An embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are suitable for being loaded by a processor and executing the method steps in the embodiment shown in fig. 3, and a specific execution process may refer to a specific description of the embodiment shown in fig. 3, which is not described herein again.

The present application further provides a computer program product storing at least one instruction, which is loaded and executed by the processor to implement the method for correcting the phase difference of the PWM signal based on the zero-crossing detection signal according to the above embodiments.

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 5, the electronic device 900 may include: at least one processor 901, at least one communication interface 903, memory 904, at least one communication bus 902.

Wherein a communication bus 902 is used to enable connective communication between these components.

The communication interface 903 is used for communication between external devices or apparatuses, and optionally may include a standard wired interface or a wireless interface (e.g., a WI-FI interface).

The electronic device 900 further includes a PFC circuit, first to sixth PWM signal generators, first to sixth counters, a first zero-crossing detection circuit, and a second zero-crossing detection circuit. The first PWM signal generator is connected to the first counter and the power transistor in the main circuit, respectively, and the processor 900 is connected to the first counter. The second PWM signal generator is connected to the second counter and the power tube in the slave path, respectively, and the processor 900 is connected to the second counter. The third PWM signal generator to the sixth PWM signal generator are respectively connected with the third counter to the sixth counter in a one-to-one mode, and the processor is respectively connected with the third counter to the sixth counter.

The first zero-crossing detection circuit is connected to the processor 901 and the inductor in the master circuit, respectively, and the second zero-crossing detection circuit is connected to the processor 901 and the inductor in the slave circuit, respectively.

Processor 901 may include one or more processing cores, among other things. The processor 901 interfaces with various interfaces and circuitry throughout the electronic device 900 to perform various functions of the electronic device 900 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 904 and invoking data stored in the memory 904. Optionally, the processor 901 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable gate Array (FPGA), and Programmable Logic Array (PLA). The processor 901 may integrate one or a combination of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is understood that the above modem may not be integrated into the processor 901, and may be implemented by a single chip.

The Memory 904 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 904 includes a non-transitory computer-readable medium. The memory 904 may be used to store instructions, programs, code sets, or instruction sets. The memory 904 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 904 may optionally also be at least one storage device located remotely from the aforementioned processor 901. As shown in fig. 9, the memory 904, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and an application program.

In the electronic device 900 shown in fig. 9, the user interface 903 is mainly used for providing an input interface for a user to obtain data input by the user; the processor 901 may be configured to call the application program stored in the memory 904 and specifically execute the method shown in fig. 3 and fig. 4, and specific procedures may be shown in fig. 3 and fig. 4 and are not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, an optical disk, a read-only memory or a random access memory.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.

Claims (9)

1. A method of correcting a phase difference of PWM signals based on a zero-cross detection signal, the method comprising:

after the power is on, indicating a first counter, a second counter, a third counter, a fourth counter, a first PWM signal generator, a second PWM signal generator, a third PWM signal generator, a fourth PWM signal generator, a first zero-crossing detection circuit and a second zero-crossing detection circuit to start working;

resetting the count value of the first counter and the count value of the fourth counter upon detection of a first zero-cross signal generated by the first zero-cross detection circuit, and generating a first interrupt signal based on a reset operation of the fourth counter;

resetting the count value of the second counter when a second zero-crossing signal generated by the second zero-crossing detection circuit is detected;

reading a current count value CNT3 (i) of the third counter in response to the first interrupt signal generated at the ith time, and determining a current period value P _ PWM1 (i) of the first counter according to the CNT3 (i); reading a current count value CNT2 (i) of the second counter, taking the read current count value CNT2 (i) as a current phase angle error value E _ CNT1 (i) between the first and second PWM signal generators;

calculating a first adjustment amount Adj _ CMP1 (i) according to (E _ CNT1 (i) -P _ PWM1 (i)/2) × Kx;

if Adj _ CMP1 (i) is greater than the preset maximum step size limiting coefficient MAX _ SET;

updating Adj _ CMP1 (i) to MAX _ SET;

if Adj _ CMP1 is smaller than a preset minimum step limiting coefficient MIN _ SET, updating Adj _ CMP1 (i) to MIN _ SET;

adjusting a current duty cycle of the first PWM signal generator and a current duty cycle of the second PWM signal generator using the updated Adj _ CMP1 (i); where, PWM1_ CMP (i) = Duty1 (i) -Adj _ CMP1 (i), and PWM2_ CMP (i) = Duty2 (i) + Adj _ CMP1 (i).

2. The method of claim 1, further comprising:

indicating the fifth counter, the sixth counter, the fifth PWM signal generator and the sixth PWM signal generator to work;

resetting a count value of a sixth counter when a second zero-crossing signal generated by the second zero-crossing detection circuit is detected, and generating a second interrupt signal based on a reset operation of the sixth counter;

reading a current count value CNT5 (j) of the fifth counter in response to the jth generated second interrupt signal, and determining a current period value P _ PWM2 (j) of the second counter according to the CNT5 (j); reading a current count value CNT1 (j) of the first counter, using CNT1 (j) as a current phase angle error value E _ CNT2 (j) between the first PWM signal generator and the second PWM signal generator;

calculating a current second adjustment amount Adj _ CMP2 (j); wherein Adj _ CMP2 (j) = (E _ CNT2 (j) -P _ PWM2 (j)/2) × Kx

If the Adj _ CMP2 (j) is larger than a preset maximum step limiting coefficient MAX _ SET, updating the Adj _ CMP2 (j) to MAX _ SET;

if Adj _ CMP2 is smaller than the preset minimum step limiting coefficient MIN _ SET, updating Adj _ CMP2 (j) to MIN _ SET;

adjusting the current duty cycle of the first PWM signal generator and the current duty cycle of the second PWM signal generator by using the updated Adj _ CMP1 (j); where, PWM1_ CMP (j) = Duty1 (j) -Adj _ CMP2 (j), and PWM2_ CMP (j) = Duty2 (j) + Adj _ CMP2.

3. The method according to claim 1 or 2, wherein said determining a current period value P _ PWM1 (i) of said first counter according to CNT3 (i) comprises:

determining a current period value of the first counter according to the following formula:

p _ PWM1 (i) = CNT3 (i) + D _ Comp; wherein D _ Comp is a preset delay compensation amount.

4. The method of claim 2, wherein determining the current period value of the second counter, pmPWM 2 (j), from CNT5 (j) comprises:

determining a current period value of the second counter according to the following formula:

p _ PWM2 (j) = CNT5 (j) + D _ Comp; wherein, D _ Comp is a preset delay compensation amount.

5. The method of claim 1, 2 or 4, further comprising:

configuring initial duty cycles of the first, second, third, and fourth PWM signal generators.

6. The method of claim 5, wherein the initial duty cycles of the first and second PWM signal generators are equal.

7. An apparatus for correcting a phase difference of a PWM signal based on a zero-cross detection signal, the apparatus comprising:

the indicating unit is used for indicating the first counter, the second counter, the third counter, the fourth counter, the first PWM signal generator, the second PWM signal generator, the third PWM signal generator, the fourth PWM signal generator, the first zero-crossing detection circuit and the second zero-crossing detection circuit to start working after being electrified;

a reset unit configured to reset a count value of the first counter and a count value of the fourth counter when the first zero-cross signal generated by the first zero-cross detection circuit is detected, and generate a first interrupt signal based on a reset operation of the fourth counter;

the reset unit is further configured to reset a count value of the second counter when a second zero-crossing signal generated by the second zero-crossing detection circuit is detected;

the interrupt processing unit is used for responding to the first interrupt signal generated at the ith time, reading the current count value CNT3 (i) of the third counter, and determining the current period value P _ PWM1 (i) of the first counter according to the CNT3 (i); reading a current count value CNT2 (i) of the second counter, taking the read current count value CNT2 (i) as a current phase angle error value E _ CNT1 (i) between the first PWM signal generator and the second PWM signal generator;

a calculation unit configured to calculate a first adjustment amount Adj _ CMP1 (i) according to (E _ CNT1 (i) -P _ PWM1 (i)/2) × Kx;

an updating unit, configured to update Adj _ CMP1 (i) to MAX _ SET if Adj _ CMP1 (i) is greater than a preset maximum step size limiting coefficient MAX _ SET; if Adj _ CMP1 is smaller than a preset minimum step limiting coefficient MIN _ SET, updating Adj _ CMP1 (i) to MIN _ SET;

an adjusting unit for adjusting the current duty cycle of the first PWM signal generator and the current duty cycle of the second PWM signal generator using the updated Adj _ CMP1 (i); where, PWM1_ CMP (i) = Duty1 (i) -Adj _ CMP1 (i), and PWM2_ CMP (i) = Duty2 (i) + Adj _ CMP1 (i).

8. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the method steps according to any one of claims 1 to 6.

9. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 6.

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