CN110649801B - Bus voltage sampling method, PFC control circuit and power conversion circuit - Google Patents
Bus voltage sampling method, PFC control circuit and power conversion circuit Download PDFInfo
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- CN110649801B CN110649801B CN201910745359.4A CN201910745359A CN110649801B CN 110649801 B CN110649801 B CN 110649801B CN 201910745359 A CN201910745359 A CN 201910745359A CN 110649801 B CN110649801 B CN 110649801B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention is suitable for the technical field of power control, and provides a bus voltage sampling method, a PFC control circuit and a power conversion circuit, which comprise: firstly sampling the wave voltage of the steamed bread in real time to obtain a plurality of detection voltage values; then acquiring characteristic points of the steamed bread wave voltage according to the plurality of detected voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points; and finally, acquiring a sampling value of the corresponding bus voltage according to the sampling time point. The method has the advantages that the cost of the PFC control circuit is very small, the possibility of oscillation does not exist in an open-loop mode, the algorithm design is simple, the output is stable, a general microprocessor is adopted, a special high-speed DSP is not needed, the voltage loop of the PFC bus can be timely compensated, a large amount of computing resources are saved, and the freedom degree of the type selection of a chip is large.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a bus voltage sampling method, a PFC (power factor correction) control circuit and a power conversion circuit.
Background
In the digital control, a software phase-locked loop is adopted to replace a traditional analog phase-locked loop so as to reduce errors generated in the phase-locked process of a hardware circuit, which brings the expense of CPU computing resources and relates to the work of discretization conversion of analog quantity and the like, so that the whole design work is more complicated.
The digital PFC circuit based on DSP control is the same as the traditional circuit topology controlled by an analog chip, and the difference lies in that the former control of a loop circuit samples input voltage, input current and output voltage (bus voltage) through analog-to-digital conversion and then carries out discretization conversion, the input of a PWM control circuit is obtained through software calculation according to the loop control rule and is used for driving a switch tube to complete the voltage stabilization of PFC output voltage, meanwhile, the input current is enabled to follow the input voltage of sinusoidal conversion, the function of power conversion with the power factor close to 1 is completed, the traditional analog control mode has similar flow, but the realization part is an analog device, the flexibility is far lower than that of digital control, such as frequency conversion, voltage transformation and the like.
Although a digitally controlled Power Factor Corrector (PFC) achieves highly flexible adjustment, it has certain requirements on DSP resources, on one hand, because an excessively high processor frequency causes an excessively high power consumption, and at the same time, there is a direct proportional relationship in cost, so that when a DSP model is selected, a relatively low-frequency CPU core is generally selected to reduce power consumption and cost.
However, if the DSP index after the compromise is not optimized in design, it will have a certain influence on the operation performance, so how to try to save the computation resource and simultaneously achieve the purpose of not influencing the performance of the DPFC, such as stability and dynamic response characteristics, is a topic worth discussing.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a bus voltage sampling method, a PFC control circuit, and a power conversion circuit, and aims to solve the problem in the prior art that the performance requirement on the CPU core of the DSP is too high due to the fact that the bus voltage is subjected to discretization conversion and the input of the PWM control circuit is obtained through software calculation according to the loop control law.
A first aspect of an embodiment of the present invention provides a method for sampling a bus voltage, where an input voltage of a PFC control circuit is a steamed bread wave voltage, and another input voltage is a bus voltage, where the method includes:
sampling the steamed bread wave voltage in real time to obtain a plurality of detection voltage values;
acquiring characteristic points of the steamed bread wave voltage according to the detection voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points;
and acquiring a corresponding sampling value of the bus voltage according to the sampling time point.
A second aspect of the embodiments of the present invention provides a PFC control circuit, including a voltage loop compensation circuit, a current loop compensation circuit, and a PWM control circuit, further including: the bus voltage sampling circuit inputs the steamed bread wave voltage and the bus voltage and is used for realizing the bus voltage sampling method;
the input of the voltage loop compensation circuit is the steamed bread wave voltage and the output of the bus voltage sampling circuit, and the voltage loop compensation circuit is used for performing voltage compensation on the bus voltage;
the input of the current loop compensation circuit is the output of the voltage loop compensation circuit and is used for carrying out current compensation on the bus voltage;
the input of the PWM control circuit is the output of the current loop compensation circuit and is used for outputting a PWM control signal so as to realize power factor correction of the steamed bread wave voltage on the bus voltage.
A third aspect of the embodiments of the present invention provides a power conversion circuit, which is characterized by including an inductor and a diode connected in series, wherein the other end of the inductor is connected with a voltage of a header wave, a cathode of the diode is a bus voltage, the bus voltage is electrically connected to the DC-DC conversion circuit, and the bus voltage is grounded through a capacitor; the anode of the diode is grounded through a switch tube;
the input of the PFC control circuit is the steamed bread wave voltage and the bus voltage, the output of the PFC control circuit is a PWM control signal, and the PFC control circuit is connected with the control end of the switching tube.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: firstly sampling the wave voltage of the steamed bread in real time to obtain a plurality of detection voltage values; then acquiring characteristic points of the steamed bread wave voltage according to the plurality of detected voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points; finally, acquiring a sampling value of the corresponding bus voltage according to the sampling time point; the method has the advantages that the cost of the PFC control circuit is very small, the possibility of oscillation does not exist in an open loop mode, the algorithm design is simple, the output is stable, a general microprocessor is adopted, a special high-speed DSP is not needed, the voltage loop of the PFC bus can be timely compensated, a large amount of computing resources are saved, and the freedom degree of selection of a chip is large.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flow chart of an implementation of a bus voltage sampling method according to an embodiment of the present invention;
FIG. 2 is a schematic of a steamed bun wave voltage and an average value of the steamed bun wave voltage;
fig. 3 is a schematic flow chart of another implementation of the bus voltage sampling method provided by the embodiment of the present invention;
fig. 4 is a block diagram of an internal structure of a PFC control circuit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a power conversion circuit according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 shows an implementation flow of a bus voltage sampling method provided by an embodiment of the present invention, and for convenience of description, only a part related to the embodiment of the present invention is shown, and the following details are described:
one input voltage of the PFC control circuit is a steamed bread wave voltage, the other input voltage is a bus voltage,
in step 101, sampling the steamed bread wave voltage in real time to obtain a plurality of detection voltage values;
In step 102, feature points of the steamed bread wave voltage are obtained according to the multiple detected voltage values, the feature points are zero-crossing points and/or maximum values, and corresponding sampling time points are found according to the feature points.
In a specific implementation, step 102 includes step 102-1, step 102-2a, and step 102-2 b.
In step 102-1, the currently sampled bus voltage value is compared to the last sampled bus voltage value.
In step 102-2a, if the difference between the currently sampled bus voltage value and the bus voltage value sampled last time is greater than the preset value, it is determined that the bus voltage is in a large disturbance state, feature points of the steamed bread wave voltage are obtained according to a plurality of detected voltage values, the feature points are zero-crossing points and maximum values, and corresponding sampling time points are found according to the feature points.
When large dynamic disturbance occurs, loop compensation is performed except for a zero crossing point, compensation is also performed at a peak value, time-varying response is generated by dynamic response, the bus voltage is restored to a stable state more quickly, and the dynamic performance of the power supply is improved.
In step 102-2b, if the difference between the currently sampled bus voltage value and the bus voltage value sampled last time is not greater than the preset value, it is determined that the bus voltage is in a steady state, a feature point of the voltage of the steamed bread wave is obtained according to the multiple detected voltage values, the feature point is a zero-crossing point or a maximum value, and a corresponding sampling time point is found according to the feature point.
Because the loop control of the PFC is expected to be carried out on the average value of the voltage waveform of the bus, the stable requirement of the loop can be met only by adopting a zero crossing point and selecting half of control bandwidth in a stable state, and the strategy of controlling both the wave crest and the zero crossing point is used in a large disturbance state, so that the calculation bandwidth is further saved in the stable state, the transient response effect is improved in a dynamic state, the purpose of time-varying control is essentially finished, and the performance of a digital control power supply is obviously improved.
Wherein, 1) the sampling time point corresponding to the zero-crossing point of the steamed bread wave voltage is obtained, which specifically comprises the following steps: and acquiring a corresponding sampling time point when the voltage of the steamed bread wave is zero.
Wherein, the method for 2) acquiring the maximum value of the steamed bread wave voltage comprises the steps A to E.
A. The peak value holder and the counter are preset, and the initial value in the peak value holder is 0, and the initial value of the counter is 0.
B. It is determined whether the current detected voltage value is greater than the voltage value stored in the peak value holder.
C. If the current detected voltage value is greater than the voltage value stored in the peak value holder, the current detected voltage value is updated to the voltage value stored in the peak value holder.
D. If the current detected voltage value is not greater than the voltage value stored in the peak value keeper, the peak value keeper is not updated, and the counter is increased by 1.
E. And when the counting of the counter reaches a preset value, stopping judging, wherein the voltage value stored in the peak value retainer is the maximum value of the steamed bun wave voltage. The preset value of the counter may be 3.
In specific implementation, if the preset value of the counter is too small, due to the randomness of sampling errors, the defect that the maximum value of the obtained steamed bread wave voltage is inaccurate exists, and the sampling accuracy of the PFC control circuit on the bus voltage is influenced; if the preset value of the counter is too large, the sampling time is inaccurate due to too many sampling times, and the maximum value of the voltage of the head wave is also not searched for, so that the accuracy of the PFC control circuit for sampling the voltage of the bus is influenced.
In the specific implementation, step a may further include steps F to I.
F. Carrying out low-pass filtering on the steamed bread wave voltage to obtain an average value of the steamed bread wave voltage; judging whether the current detection voltage value is larger than the average value of the steamed bread wave voltage or not; .
G. If the current detection voltage value is larger than the average value of the steamed bread wave voltage, the function of the peak value retainer is started; and step a is performed.
H. And if the current detection voltage value is not larger than the average value of the steamed bread wave voltage, the function of the peak value retainer is closed.
As shown in fig. 2, the maximum value of the steamed bread wave voltage is greater than the average value of the steamed bread wave voltage, and when the current detected voltage value is not greater than the average value of the steamed bread wave voltage, the function of the peak value keeper is closed, and at this time, the acquisition of the maximum value of the steamed bread wave voltage is stopped, so that the algorithm steps can be simplified, and the efficiency of the bus voltage sampling method can be improved.
In step 103, sampling values of the corresponding bus voltage are obtained according to the sampling time points.
In the embodiment of the invention, because the zero crossing point (minimum) and the peak value (maximum) of the steamed bread wave voltage correspond to the ideal average value of the PFC bus, the bus voltage is found by utilizing the detection of the zero crossing point (minimum) and the peak value (maximum) of the steamed bread wave voltage, thereby realizing the accurate control of the PFC bus voltage.
Because extra processor resources are not needed to process the operations such as closed loop, second-order dispersion and the like, the frequency, the maximum value and the minimum value of the bus voltage can be identified only by the large and small operations of the power frequency (100-120Hz, frequency after rectification) level, and the accurate closed loop control is carried out on the output PFC bus near the extreme value, so that the voltage loop of the PFC always obtains loop compensation calculation near the ideal average value, the execution rate of the loop can be minimized, the sufficient response bandwidth (10-15Hz) can be ensured to be output, and the calculation resources of a single chip microcomputer or a DSP are greatly saved.
In a specific implementation, as shown in fig. 3, step 101 further includes step 101-2 and step 101-3.
In step 101-2, a fixed time period is set if the steamed bread wave voltage is briefly powered down.
In step 101-3, sampling values of corresponding bus voltages are obtained every fixed time period until the steamed bread wave voltage returns to normal. The fixed time period can be 5-10 ms.
In a certain period of time, the correct steamed bread wave voltage is not found all the time, namely the short power failure of the steamed bread wave voltage is judged; and sampling the bus voltage once every preset time period, keeping loop compensation and maintaining the bus voltage stable. If the correct steamed bread wave voltage is not found at a longer time (such as 30ms), the shutdown is carried out.
According to the embodiment of the invention, steamed bread wave voltage is sampled in real time to obtain a plurality of detection voltage values; then acquiring characteristic points of the steamed bread wave voltage according to the plurality of detected voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points; finally, acquiring a sampling value of the corresponding bus voltage according to the sampling time point; the DSP of the high-performance CPU core is not required to be selected to carry out discretization transformation on the bus voltage, and the input of the PWM control circuit is obtained through software calculation according to the loop control rule. The method has the advantages that the cost of the PFC control circuit is very small, the possibility of oscillation does not exist in an open-loop mode, the algorithm design is simple, the output is stable, a general microprocessor is adopted, a special high-speed DSP is not needed, the voltage loop of the PFC bus can be timely compensated, a large amount of computing resources are saved, and the freedom degree of the type selection of a chip is large.
In order to implement the above method for sampling the bus voltage, an embodiment of the present invention further provides a PFC control circuit, as shown in fig. 4, including a voltage loop compensation circuit 01, a current loop compensation circuit 02, and a PWM control circuit 03, and further including: the bus voltage sampling circuit 04 is used for sampling the bus voltage, and the input of the bus voltage sampling circuit 04 is the steamed bread wave voltage and the bus voltage;
the input of the voltage loop compensation circuit 01 is the output of the steamed bun wave voltage and bus voltage sampling circuit, and is used for performing voltage compensation on the bus voltage;
the input of the current loop compensation circuit 02 is the output of the voltage loop compensation circuit, and is used for performing current compensation on the bus voltage;
the input of the PWM control circuit 03 is the output of the current loop compensation circuit, and is used to output a PWM control signal, so as to realize the power factor correction of the voltage of the steamed bread wave on the voltage of the bus.
In order to implement the above method for sampling the bus voltage, an embodiment of the present invention further provides a power conversion circuit, as shown in fig. 5, including an inductor L1, a diode D1, a switching tube M1, a capacitor C1, and a DC-DC conversion circuit 06; one end of an inductor L1 is connected with the anode of a diode D1, the other end of the inductor L1 is connected with the voltage of a bus, the cathode of the diode D1 is the voltage of the bus, the voltage of the bus is connected with the DC-DC conversion circuit 06, and the voltage of the bus is grounded through a capacitor C1; the anode of the diode D1 is grounded through a switch tube M1; the input of the PFC control circuit 00 is a steamed bread wave voltage and a bus voltage, the output of the PFC control circuit 00 is a PWM control signal, and the PWM control signal is connected with a control end of a switch tube M1.
After acquiring the sampling value of the corresponding bus voltage, the PFC control circuit 00 generates a PWM control signal of a target duty ratio according to the sampling value and the preset voltage value to control the switching tube M1 to be turned on or off.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. . Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (9)
1. A method for sampling bus voltage, one input voltage of a PFC control circuit is a steamed bread wave voltage, and the other input voltage is the bus voltage, and the method is characterized by comprising the following steps:
sampling the steamed bread wave voltage in real time to obtain a plurality of detection voltage values;
acquiring characteristic points of the steamed bread wave voltage according to the detection voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points;
acquiring a sampling value of the corresponding bus voltage according to the sampling time point;
the acquiring the characteristic points of the steamed bun wave voltage according to the plurality of detected voltage values, wherein the characteristic points are zero-crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points specifically comprises:
comparing the bus voltage value sampled at present with the bus voltage value sampled last time;
if the difference value between the bus voltage value sampled at present and the bus voltage value sampled at last time is larger than a preset value, judging that the bus voltage is in a large disturbance state, acquiring characteristic points of the steamed bread wave voltage according to a plurality of detected voltage values, wherein the characteristic points are zero-crossing points and maximum values, and finding corresponding sampling time points according to the characteristic points;
if the difference value between the bus voltage value sampled at present and the bus voltage value sampled at last time is not larger than a preset value, the bus voltage is judged to be in a stable state, characteristic points of the steamed bun wave voltage are obtained according to a plurality of detected voltage values, the characteristic points are zero-crossing points or maximum values, and corresponding sampling time points are found according to the characteristic points.
2. The method for sampling bus voltage according to claim 1, wherein the obtaining of the sampling time point corresponding to the zero-crossing point of the steamed bread wave voltage specifically comprises: and acquiring a corresponding sampling time point when the steamed bread wave voltage is zero.
3. The method for sampling bus voltage according to claim 1, wherein the method for obtaining the maximum value of the steamed bread wave voltage comprises:
presetting a peak value holder and a counter, wherein the initial value in the peak value holder is 0, and the initial value of the counter is 0;
judging whether the current detection voltage value is larger than the voltage value stored in the peak value holder;
if the current detection voltage value is larger than the voltage value stored in the peak value holder, updating the current detection voltage value to the voltage value stored in the peak value holder;
if the current detection voltage value is not larger than the voltage value stored in the peak value holder, the peak value holder is not updated, and a counter is increased by 1;
and when the counting of the counter reaches a preset value, stopping judging, wherein the voltage value stored in the peak value retainer is the maximum value of the steamed bread wave voltage.
4. A method for sampling bus voltage as claimed in claim 3, wherein the preset value of the counter is 3.
5. The method for sampling bus voltage according to claim 3, wherein the peak value holder and the counter are preset, and the initial value in the peak value holder is 0, and before the initial value in the counter is 0, the method further comprises:
carrying out low-pass filtering on the steamed bread wave voltage to obtain an average value of the steamed bread wave voltage; judging whether the current detection voltage value is larger than the average value of the steamed bread wave voltage;
if the current detection voltage value is larger than the average value of the steamed bread wave voltage, the function of the peak value retainer is started;
if the current detection voltage value is not larger than the average value of the steamed bread wave voltage, the function of the peak value retainer is closed.
6. The method for sampling bus voltage according to claim 1, wherein said sampling said steamed bread wave voltage in real time to obtain a plurality of detected voltage values further comprises:
if the steamed bread wave voltage is temporarily powered off, setting a fixed time period;
and acquiring corresponding sampling values of the bus voltage every other fixed time period until the steamed bread wave voltage returns to normal.
7. The method for sampling bus voltage according to claim 6, wherein the fixed time period is 5-10 ms.
8. A PFC control circuit comprises a voltage loop compensation circuit, a current loop compensation circuit and a PWM control circuit, and further comprises: the bus voltage sampling circuit has the input of the steamed bread wave voltage and the bus voltage and is used for realizing the bus voltage sampling method according to any one of claims 1 to 7;
the input of the voltage loop compensation circuit is the steamed bread wave voltage and the output of the bus voltage sampling circuit, and the voltage loop compensation circuit is used for performing voltage compensation on the bus voltage;
the input of the current loop compensation circuit is the output of the voltage loop compensation circuit and is used for carrying out current compensation on the bus voltage;
the input of the PWM control circuit is the output of the current loop compensation circuit and is used for outputting a PWM control signal so as to realize power factor correction of the steamed bread wave voltage on the bus voltage.
9. A power conversion circuit is characterized by comprising an inductor, a diode, a switching tube, a capacitor and a DC-DC conversion circuit;
one end of the inductor is connected with the anode of the diode, the other end of the inductor is connected with the voltage of the steamed bread wave, the cathode of the diode is the voltage of a bus, the bus is electrically connected with the DC-DC conversion circuit in a voltage mode, and the voltage of the bus is grounded through a capacitor; the anode of the diode is grounded through a switch tube;
the PFC control circuit of claim 8, further comprising a PWM control signal coupled to the control terminal of the switching tube, wherein the inputs of the PFC control circuit are a steamed-bread voltage and the bus voltage.
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