CN103684031A - Current hysteresis control digital implementation system for PWM rectifier - Google Patents
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Abstract
The invention discloses a current hysteresis control digital implementation system for a PWM rectifier. TMS320F28069 DSP of Piccolo series of TI is adopted to achieve current hysteresis control, the functions of a chip dual-core processor are fully utilized, logic control, communication and three-phase current given generation for the PWM rectifier are achieved in a main CPU, a current hysteresis control strategy is achieved in a control rate accelerator, PWM pulses are generated to drive a power switch tube of a major loop, and the functions of the PWM rectifier are achieved. The control rate accelerator introduces the concurrent control loop execution function into a C28x series device. In this way, time delay existing from ADC damping to output is greatly reduced, and faster system response and a higher-frequency control loop are achieved. CLA is used for providing services for the control loop with strict time requirements, so that the main CPU freely processes other system tasks such as communication and diagnosis.
Description
Technical field
The present invention relates to power electronics control technology field, be specifically related to the stagnant ring control figure of a kind of PWM rectifier current and realize system.
Background technology
Current PWM rectifier, with plurality of advantages such as the operation of its to and fro flow of power, grid side unity power factor, input current sine degree are good, obtains a wide range of applications in fields such as AC speed regulating, uninterrupted power supply, reactive power compensation, new forms of energy.The control strategy that PWM rectifier is conventional has Hysteresis Current control, sine pulse width modulation (PWM) control, space vector PWM control etc.Hysteresis Current control method has controls the advantages such as simple, response is fast, tracking accuracy is high, the stability of a system is good, so in the controlling unit of PWM rectifier current output, it is a kind of conventional control method.Traditional Hysteresis Current is controlled the general analog circuit that adopts and is realized, but analog circuit has open defect than digital circuit, as the interference of the drift of circuit, noise, false triggering etc.Adopting maximum methods is at present to utilize conventional fixed frequency sampling to carry out stagnant ring control, control cycle is approximately tens to hundreds of microsecond, but fixing owing to selecting switching time, same instruction only can be followed the tracks of once, cause actual current burr suddenly big or suddenly small, Current Control precision is not high, controls effect undesirable; Conventional digital sample, each s operation control module can not require to regulate according to response, and the stability of control system and Ability of Resisting Disturbance are not high; And conventional control, if the major cycle computing of DSP and interrupt coordinating between computing bad will have a strong impact on the real-time of Current Control and the synchronism that Hysteresis Current is followed the tracks of.
Summary of the invention
Object of the present invention provides the stagnant ring control figure of a kind of PWM rectifier current to realize system, adopt the TMS320F28069 DSP of the Piccolo series of TI to complete Hysteresis Current control, make full use of the function of this chip dual core processor, in host CPU, complete the given generation of logic control, communication and three-phase current of PWM rectifier equipment, in control rate accelerator, complete Hysteresis Current Control Strategy, produce the power switch pipe that pwm pulse removes to drive major loop, realize PWM rectifier function.Control law accelerator is an independence, complete programmable 32 floating-point mathematics processors, and it is carried out function by parallel control ring and is incorporated into C28x family device.The low interruption delay of CLA makes it can immediately read ADC sampling.This has just greatly reduced the time delay that ADC samples output, has realized the control loop of system responses and higher frequency faster.By utilizing CLA to serve the strict control loop of time requirement, host CPU just can freely be processed other system task such as communication, diagnosis.
In order to overcome deficiency of the prior art, the invention provides the solution that the stagnant ring control figure of a kind of PWM rectifier current is realized system, specific as follows:
The stagnant ring control figure of a kind of PWM rectifier current is realized system, comprise the PWM drive circuit 2 connecting successively, three-phase voltage-type inverter 1, voltage and current signals collecting part 3, outputting inductance 4 and three-phase alternating current electrical network 5, power network current and direct voltage are sampled through the A/D circuit 6 of voltage and current signal collecting part 3 to TI F28069DSP chips, CLA module 6 in sheet directly reads the result of A/D sampling by A/D value fetch program module 11, and by mean computation routine module 12, calculate the mean value of 100 microseconds, store in CLA-to-CPU RAM memory 10, host CPU module 8 can every 100 microseconds read these sampled values by CLA-to-CPU RAM memory 10, in conjunction with these sampled values, pass through the phase-locked module 15 of line voltage, DC voltage control module 16, switching frequency control module 17 and given current generating module 18 calculate in the given and given CPU-to-CLA of storing into the RAM of the hysteresis band memory 9 of three-phase current, it is given given with hysteresis band that every 100 microseconds of CLA module 6 read three-phase current by CPU-to-CLA RAM memory 9, by Hysteresis Current control module 14, producing PWM exports, the conducting of three-phase inverter IGBT in PWM rectifier is controlled in PWM output by PWM drive circuit 2, switching frequency computing module 13 in CLA module 6 calculates the switching frequency of each phase by adding up the on-off times of each switching tube, and can pass to host CPU module 8 by CLA-to-CPU RAM memory 10, the switching frequency that host CPU module 8 reads every phase participates in that in switching frequency control module 17, to produce hysteresis band given.
The sampling element that the stagnant ring control figure of described PWM rectifier current is realized system is to be 5 microseconds by configuring the cycle of CPU timer 0, the trigger source of AD is chosen as CPU timer 0, adopt the time of reducing AD sampling window to guarantee that the sampling of 16 passages completes in 5 microseconds, by Hysteresis Current control module, carry out the conducting of control switch pipe, simultaneously 5 microseconds have also realized on a phase brachium pontis the Dead Time of pipe under pipe and a phase brachium pontis.
The present invention adopts the TMS320F28069 DSP of the Piccolo series of TI to control, and makes full use of the function of this chip dual core processor.In the F28069 processor that contains CLA, CLA can free CPU, automatically controls the running of peripheral hardware, reaches higher control precision and better real-time.Overcome single cpu system of traditional control method, between DSP major cycle computing and interruption computing, transmission of information need to take the overhead time of CPU, the scheme that the present invention proposes can be parallel in DSP work, between CLA and host CPU, be independent of each other, carry out the algorithm computing Peripheral Interface different with access simultaneously.In host CPU, complete every 5 microseconds and start a CLA, the configuration of AD sampling simultaneously also guarantees that 5 microseconds complete once; The logic control of PWM rectifier systems, error protection, direct voltage closed-loop control, the generation of the given electric current of three-phase, the closed-loop control of switching frequency all complete in host CPU.The control cycle of host CPU is 100 microseconds, and every 100 microsecond host CPUs and CLA exchange a secondary data.In CLA, complete the reading of AD sampled data, mean value calculation, Hysteresis Current Control Strategy, PWM output and switching frequency calculating etc.To each given value of current, can complete the tracking of maximum 20 times like this, make Hysteresis Current follow the tracks of control related operation separated with given electric current related operation, to make full use of the dual core processor function of DSP, guaranteed real-time, synchronism and the control precision of current tracking.
Accompanying drawing explanation
Fig. 1 is that the digital control strategy that the present invention adopts is realized schematic diagram;
Fig. 2 is control system sampling element schematic diagram;
Fig. 3 is that the stagnant ring of a phase current is controlled software flow pattern;
Fig. 4 is single leg inverter principle topological diagram;
Fig. 5 is Hysteresis Current control principle drawing;
Fig. 6 is switching frequency control principle block diagram;
Fig. 7 is that line voltage is phase-locked, DC voltage control, given current generating module theory diagram.
Current tracking waveform when Fig. 8 is traditional SVPWM control mode PWM rectifier output 8A reactive current stable state.
Fig. 9 be the present invention adopt Hysteresis Current control method PWM rectifier output 8A reactive current stable state time current tracking waveform.
Figure 10 is that Hysteresis Current control method PWM rectifier output 8A reactive current starts tracking waveform.
Embodiment
Below in conjunction with accompanying drawing, summary of the invention is described further:
The stagnant ring control figure of PWM rectifier current is realized system, comprise the PWM drive circuit 2 connecting successively, three-phase voltage-type inverter 1, voltage and current signals collecting part 3, outputting inductance 4 and three-phase alternating current electrical network 5, power network current and direct voltage are sampled through the A/D circuit 6 of voltage and current signal collecting part 3 to TI F28069 dsp chips, CLA module 6 in sheet directly reads the result of A/D sampling by A/D value fetch program module 11, and by mean computation routine module 12, calculate the mean value of 100 microseconds, store in CLA-to-CPU RAM memory 10, host CPU module 8 can every 100 microseconds read these sampled values by CLA-to-CPU RAM memory 10, in conjunction with these sampled values, pass through the phase-locked module 15 of line voltage, DC voltage control module 16, switching frequency control module 17 and given current generating module 18 calculate in the given and given CPU-to-CLA of storing into the RAM of the hysteresis band memory 9 of three-phase current, it is given given with hysteresis band that every 100 microseconds of CLA module 6 read three-phase current by CPU-to-CLA RAM memory 9, by Hysteresis Current control module 14, producing PWM exports, the conducting of three-phase inverter IGBT in PWM rectifier is controlled in PWM output by PWM drive circuit 2, switching frequency computing module 13 in CLA module 6 calculates the switching frequency of each phase by adding up the on-off times of each switching tube, and can pass to host CPU module 8 by CLA-to-CPU RAM memory 10, the switching frequency that host CPU module 8 reads every phase participates in that in switching frequency control module 17, to produce hysteresis band given.
The sampling element that the stagnant ring control figure of described PWM rectifier current is realized system as shown in Figure 2, to be 5 microseconds by configuring the cycle of CPU timer 0, the trigger source of AD is chosen as CPU timer 0, adopt the time of reducing AD sampling window to guarantee that the sampling of 16 passages completes in 5 microseconds, by Hysteresis Current control module, carry out the conducting of control switch pipe, in Fig. 2, VT1 represents on a phase brachium pontis and manages, VT2 represents under a phase brachium pontis and manages, simultaneously 5 microseconds have also realized on a phase brachium pontis the Dead Time of pipe under pipe and a phase brachium pontis, the control time of 5 microseconds approaches analog circuit Hysteresis Current and controls, the stagnant ring of more conventional fixed frequency sampling is controlled, solved and detected the impact that delay brings, improved the precision of Current Control simultaneously.
The stagnant ring control flow chart of a phase current that the stagnant ring control figure of described PWM rectifier current is realized system as shown in Figure 3, is set forth Hysteresis Current control principle of the present invention in conjunction with the mono-leg inverter topological sum of Fig. 4 Fig. 5 Hysteresis Current control principle: at inductive current i
lpositive half cycle, works as i
l-i
*<=-h changes the state of power switch, the pulse signal triggering and conducting of generation, and inductive current starts to increase, until i
l-i
*during >=h, switch VT1 manages shutoff, when VT2 turn-offs or opens, and i
lwill be by VD2 afterflow, under the effect of input voltage and line voltage, inductive current starts to reduce, in like manner known, at inductive current i
lnegative half period, works as i
l-i
*during >=h, change the state of power switch pipe, the pulse signal of generation triggers VT2 conducting, and inductive current starts to reduce, until i
l-i
*during <=-h, switching tube VT2 turn-offs, when VT1 turn-offs or opens, and i
lwill be by VD1 afterflow, under the effect of input voltage and line voltage, inductive current starts to increase, be sent to like this public exchange electrical network current i
lhysteresis band with 2h is followed the tracks of sinusoidal reference electric current.The control procedure of b phase and c phase is with a phase.According to above-mentioned control principle, in the situation of IGBT high level conducting, list the control procedure of every phase:
Under Iaact>IaRef+Ihref, manage open-mindedly, upper pipe turn-offs, and PWM1 is low level, and PWM2 is high level;
The upper pipe of Iaact<IaRef-Ihref is open-minded, and turn-off in ShiShimonoseki, and PWM1 is high level, and PWM2 is low level;
Under Ibact>IbRef+Ihref, manage open-mindedly, upper pipe turn-offs, and PWM3 is low level, and PWM4 is high level;
The upper pipe of Ibact<IbRef-Ihref is open-minded, and turn-off in ShiShimonoseki, and PWM3 is high level, and PWM4 is low level;
Under Icact>IcRef+Ihref, manage open-mindedly, upper pipe turn-offs, and PWM5 is low level, and PWM6 is high level;
The upper pipe of Icact<IcRef-Ihref is open-minded, and turn-off in ShiShimonoseki, and PWM5 is high level, and PWM6 is low level.
Iaact, Ibact and Icact are the AD sampled value that every 5 microseconds of CLA read, and IaRef, IbRef, IcRef and Ihref are that the three-phase current that reads from host CPU of every 100 microsecond CLA is given and hysteresis band is given.Due to the power switch pipe impact of intrinsic switching time, service time is often less than the turn-off time, therefore, when the complementary control of upper and lower bridge arm, the short trouble with the conducting simultaneously of two power switch pipes of arm easily occurs.For preventing the straight-through of two power switch pipes of same brachium pontis, in pwm control signal, must set " break-before-make " PWM switch dead band.K in flow chart and j are in order to guarantee to manage up and down while switching, the counter that adds dead band to control.Whole Hysteresis Current is controlled and is completed in CLA, is totally independent of host CPU operation, and control cycle is 5 microseconds, can carry out much 20 secondary trackings to same instruction, has guaranteed real-time, synchronism and the control precision of current tracking.
See and in Fig. 1 host CPU, mainly comprise the phase-locked module 15 of line voltage, DC voltage control module 16, switching frequency control module 17, given current generating module 18.Switching frequency control module as shown in Figure 6, mainly comprises maximum switching frequency statistics 1, pi regulator 2 and adjuster output violent change 3.It leads comparison by the maximum of the threephase switch frequency of calculating in CLA and given switch lock Fref, by pi regulator 2, produce the given Ihref of hysteresis band, the given Ihref of hysteresis band is passed to CLA, and the Hysteresis Current control module in CLA guarantees that actual switching frequency does not transfinite.Other module in host CPU as shown in Figure 7, DC voltage control module 1 completes the closed-loop adjustment of PWM rectifier output dc voltage, the given UdcRef of direct voltage and actual DC voltage U dc are compared, their deviation is carried out PI and is regulated control, and the output of direct current pressure ring is the given IdRef of net side active current; The phase-locked module 2 of line voltage completes the detection of electric network voltage phase and frequency, the grid line voltage U ab, the Ubc that detect is calculated to electric network voltage phase angle and frequency by software phase-lock-loop algorithm, for current transformation provides phase angle accurately; Given current generating module 3 completes net side is meritorious and the given IdRef of reactive current, IqRef and transforms to three-phase a, b, c-axis given value of current IaRef, IbRef and IcRef, and CLA receives the given and given Hysteresis Current that completes of hysteresis band of three-phase current and controls.
The control strategy that the present invention proposes verifies on the PWM of 15kW rectifier unit, and Fig. 9 and Figure 10 are that direct voltage is 600V, and steady-state current when reactive current is given as 8A follows the tracks of waveform and starting current is followed the tracks of waveform.Current tracking waveform when Fig. 8 is traditional SVPWM control mode PWM rectifier output 8A reactive current stable state.From the comparison of wave shape of Fig. 8 and Fig. 9, can find that the current tracking precision of the PWM rectifier control strategy that the present invention proposes is better than traditional control mode far away, effectively suppressed the suddenly big or suddenly small phenomenon of current spikes.From the starting current of Figure 10, following the tracks of waveform can find out, the PWM rectifier control strategy dynamic response characteristic that the present invention proposes is very good, after startup, actual current just can be followed the tracks of upper given electric current in a grid cyclic wave (20ms), has overcome traditional control method due to the slow problem of electric current dynamic response detecting and computing relay brings.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, according to technical spirit of the present invention, within the spirit and principles in the present invention, the any simple modification that above embodiment is done, be equal to replacement and improvement etc., within all still belonging to the protection range of technical solution of the present invention.
Claims (2)
1. the stagnant ring control figure of PWM rectifier current is realized system, it is characterized in that comprising the PWM drive circuit (2) connecting successively, three-phase voltage-type inverter (1), voltage and current signals collecting part (3), outputting inductance (4) and three-phase alternating current electrical network (5), power network current and direct voltage are sampled to the A/D circuit (6) of TI F28069 dsp chip through voltage and current signal collecting part (3), CLA module (6) in sheet directly reads the result of A/D sampling by A/D value fetch program module (11), and by mean computation routine module (12), calculate the mean value of 100 microseconds, store in CLA-to-CPU RAM memory (10), host CPU module (8) can every 100 microseconds read these sampled values by CLA-to-CPU RAM memory (10), in conjunction with these sampled values, pass through the phase-locked module of line voltage (15), DC voltage control module (16), switching frequency control module (17) and given current generating module (18) calculate in the given and given CPU-to-CLA of storing into the RAM of the hysteresis band memory (9) of three-phase current, it is given given with hysteresis band that every 100 microseconds of CLA module (6) read three-phase current by CPU-to-CLA RAM memory (9), by Hysteresis Current control module (14), produce PWM output, the conducting of three-phase inverter IGBT in PWM rectifier is controlled in PWM output by PWM drive circuit (2), switching frequency computing module (13) in CLA module (6) calculates the switching frequency of each phase by adding up the on-off times of each switching tube, and can pass to host CPU module (8) by CLA-to-CPU RAM memory (10), the switching frequency that host CPU module (8) reads every phase participates in that in switching frequency control module (17), to produce hysteresis band given.
2. the stagnant ring control figure of PWM rectifier current according to claim 1 is realized system, it is characterized in that the sampling element that the described stagnant ring control figure of PWM rectifier current is realized system is to be 5 microseconds by configuring the cycle of CPU timer (0), the trigger source of AD is chosen as CPU timer (0), adopt the time of reducing AD sampling window to guarantee that the sampling of 16 passages completes in 5 microseconds, by Hysteresis Current control module, carry out the conducting of control switch pipe, simultaneously 5 microseconds have also realized on a phase brachium pontis the Dead Time of pipe under pipe and a phase brachium pontis.
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| CN104660089A (en) * | 2015-02-15 | 2015-05-27 | 南京埃斯顿自动控制技术有限公司 | Feedback hysteresis control method for PWM (pulse-width modulation) rectifier for servo drive |
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| CN105871241A (en) * | 2016-04-07 | 2016-08-17 | 西安交通大学 | Sampling period online prediction-based fixed switching frequency digital hysteresis control method |
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| CN104660089A (en) * | 2015-02-15 | 2015-05-27 | 南京埃斯顿自动控制技术有限公司 | Feedback hysteresis control method for PWM (pulse-width modulation) rectifier for servo drive |
| CN104660089B (en) * | 2015-02-15 | 2017-03-22 | 南京埃斯顿自动控制技术有限公司 | Feedback hysteresis control method for PWM (pulse-width modulation) rectifier for servo drive |
| CN105048480B (en) * | 2015-08-20 | 2018-07-31 | 广州电力设计院 | Dynamic reactive compensation device |
| CN105048480A (en) * | 2015-08-20 | 2015-11-11 | 广州电力设计院 | Dynamic reactive power compensation device |
| CN105633964A (en) * | 2016-03-01 | 2016-06-01 | 天津中科华瑞电气技术开发有限公司 | APF current control method and system |
| CN105871241A (en) * | 2016-04-07 | 2016-08-17 | 西安交通大学 | Sampling period online prediction-based fixed switching frequency digital hysteresis control method |
| CN108287507A (en) * | 2018-01-31 | 2018-07-17 | 上海骄成机电设备有限公司 | A kind of supersonic generator Control card |
| CN108803406A (en) * | 2018-04-04 | 2018-11-13 | 山东大学 | Task hierarchy system and method for electrokinetic cell and analog meter |
| CN108803406B (en) * | 2018-04-04 | 2020-10-27 | 山东大学 | Task hierarchical control system and method for power battery testing and simulating instrument |
| CN108363030A (en) * | 2018-05-18 | 2018-08-03 | 福州大学 | A kind of portable three-phase voltage current calibration instrument and its control method |
| CN111130309A (en) * | 2019-12-30 | 2020-05-08 | 上海沪工焊接集团股份有限公司 | Control method for improving sampling precision, storage medium and inverter power supply |
| CN111130309B (en) * | 2019-12-30 | 2022-06-24 | 上海沪工焊接集团股份有限公司 | Control method for improving sampling precision, storage medium and inverter power supply |
| CN111624428A (en) * | 2020-06-10 | 2020-09-04 | 南方电网科学研究院有限责任公司 | Fault diagnosis device of alternating-current charging pile supporting remote cloud service |
| CN111624428B (en) * | 2020-06-10 | 2021-11-26 | 南方电网科学研究院有限责任公司 | Fault diagnosis device of alternating-current charging pile supporting remote cloud service |
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Application publication date: 20140326 |